Bridging the Gap between System & Circuit Designers

Transcription

1 Bridging the Gap between System & Circuit Designers October 27, 2004 Presented by: Kal Kalbasi Q & A Marc Petersen Copyright 2003 Agilent Technologies, Inc.

2 The Gap System Communication System Design System Specs BER/PER, EVM, CCDF, Circuit? RF Block-level Circuit Design RF Circuit Specs NF, P1dB, TOI, Problem: System Design Remains an an Island Circuit Designs Should Meet System Specifications

3 Agenda Meet the Standards & Specification System & Circuit (Design & Verification) Bridging the Gap Case Study WLAN Transmitter/Receiver Integration (RF + baseband + ) Bench Verification

4 Meet the Standards Wireless Networking x WLAN IS-95A/B GSM IS-136 cdma2000 1xEV-DO 1xEV-DV 3GPP2 2G DECT W-CDMA W-CDMA W-TDD FDD TD-SCDMA W-CDMA N-TDD CWTS 2.5G HSCSD ECSD GPRS EGPRS 3G EDGE 3GPP 4G User Device User Device Wireless Interconnect WPAN's Bluetooth, WiMedia UWB, ZigBee More Standards, Complexity, Interoperability Broadband Access WMAN's e/HPI , DOCSIS WiMax Proprietary

5 Meet The Specification Microwave Theory Signal Propagation Multiple Access Comms Theory RF System Design Test & Measurement IC Design TRX Architecture Standards Linearity Supply Voltage Noise RF Circuit Design Power Freq Gain MMIC EM/Parasitic effects Baseband Design RF Integration 3 rd party IP Other RFICs Specification Instrument In the loop Wireless Test Bench RF Verification Measurement Algorithms Off-chip modules Wireless Standards

6 Evolving Design & Verification Challenges x I/Q DSP x I/Q RFIC DSP ANALOG / DIGITAL CONTROL & PROCESSING BASEBAND DATA / VOICE Baseband Design Challenges Architecture DC Offset, baseband/rf Multi-mode On-/Off-chip Miniaturization Technology Verification Challenges Verification up to 70% of design cycle Continuous/consistent verification with key metrics BER/FER, EVM Real world signals (modulated, wideband & wide dynamic range) Tool integration (system, circuit,..instruments) is is needed

7 Improved Flow (System + Circuit) System Specs BER/PER, EVM, CCDF, Communication System Design RF Block-level Circuit Design Layout RF Circuit Specs NF, P1dB, TOI, Solution: Transplant System Test Bench (EVM, BER) On On Circuit Page Capture Circuit Distortions at at System Level

8 Bridging the Gap in ADS Circuit Subsystem on System Page ADS Ptolemy System Bench on Circuit Page Analog/RF

9 Bridging the Gap in RFDE ADS Ptolemy Wireless Test Bench Dynamic Link Circuit Schematics in Cadence Virtuoso

10 Agenda Meet the Standards & Specification System vs.. Circuit (Design & Verification) Bridging the Gap Case Study WLAN Transmitter/Receiver Integration (RF + baseband + ) Bench Verification

11 Transmitter Block Diagram Baseband Source IQ Modulator Ideal Mixer RFDE Signal Band 5.3 GHz Transmitter Output Power 12 dbm max Modulation (PSK+QAM) 4,16, 64 QAM Occupied BW 16.6 MHz Channel Spacing 20 MHz Data Rate (Mbps) 6,9,12,18,24,36,48,54 Transmitter EVM -25 db (< 5.6% rms) PA 11 db linear gain Pre-amp ~ 25 db of gain VCO Phase Noise on EVM?

12 System Level Transmitter For 54 Mbps EVM should not exceed 5.6 (%RMS) 0.38 GHz 5.2 GHz 25 db 20 MHz Gain =11 db TOI = 34 dbm 1dBc=21 dbm GHz

13 Circuit Verification

14 802.11a EVM & CCDF Bench Pin=-40 Pin=-37 Pin=-34 Pin=-31 Pass Fail 5.6 Pin=-28 Pin= dbm

15 Rx system and circuit specifications System Input Signal Band 5.3 GHz Receiver NF 6 db max Modulation (PSK+QAM) 4, 16, 64 QAM Occupied BW 16.6 MHz Data Rate 6,9,12,18,24,36,48,54 Receiver EVM -28 db PER {-30 to -80 dbm} < 10% Circuit Input Signal Band Receiver NF LO Phase Noise Conversion Gain LNA Mixer IF Band IIP3 (Mixer) P1dB Input Dynamic Range 5.3 GHz < 6 db -110 MHz 30 db 8 db 12 db 100 MHz > 5 dbm -10 dbm -80 to -30 dbm

16 System Level Receiver (Baseband + RF) Transmitter Receiver (BB) Receiver (IF) Glacier Software RF Behavioral Transistor Level --Verilog

17 Receiver Front-end Matching Network Baseband Measurement EVM BER Eye Spectrum 2 Receiver

18 LNA Circuit Analysis S-parameter Gain and Match Noise Figure Group delay 2.6 db Noise figure Corresponds to 9.14 db Gain Maximum Gain = 14.5 db AC Analysis AC Voltage gain AC Noise Analysis Harmonic Balance Pin / Pout -1 db compression Two tone analysis

19 Harmonic Balance Analysis 100 khz fc 5.3 GHz

20 Envelope Analysis w Modulated Source

21 LNA Subsystem with Modulated Source

22 Different Nodes LNA + Noise

23 IQ Imbalance & Filter Bandwidth

24 LNA a Tx Test Bench Analysis

25

26 CCDF, Peak/Ave Power Ratio, EVM

27 802.11a Rx Input Level & Sensitivity Minimum input level (Sensitivity) the minimum RF signal level required to achieve a Packet Error Rate (PER) <10% at PSDU length of 1000 bytes. Maximum input level The receiver shall provide a maximum PER of 10% at a PSDU length of 1000 bytes, for maximum input level of 30dBm at the antenna for all data rates. Data Rate (Mbps) Minimum sensitivity (dbm)

28 Modeling Accuracy Behavioral Model Model Verification Models Simulator Data Model (VME & AVM) Transistor level Models Simulator Dat a Model Measurement-based Models Speed

29 Modeling for Efficient Verification input phase Frequency Input Magnitude Static nonlinearity (output is strictly dependent on the input.) Colored noise modeled as input noise source. An FIR filter at the input or the output.

30 LNA Subsystem Model Simulation time (AVM) using stored model =7 sec Simulation time (standard cosim) = 420 sec 60 times Faster!

31 LNA Model Accuracy

32 LNA Receiver Sensitivity Bench

33 LNA Subsystem Receiver Sensitivity Circuit noise ON Source 16 deg C (Eb/N0 defined at input) Date Length =1000 Bursts = 100 Data Rate = 54 Mbps

34 Down Converter Test Bench

35 BER/PER vs. Gain Imbalance Ph Im = 0 Ph Im = 10 Ph Im = 20

36 Agenda Meet the Standards & Specification System vs.. Circuit (Design & Verification) Bridging the Gap Case Study WLAN Transmitter/Receiver Integration (RF + baseband + ) Bench Verification

37 Integration & Verification Challenges C++, System C C++, System C Baseband Communication System Design System Specs BER/PER, EVM, CCDF, EM RF Block-Level Circuit Design Integration Problem How to to Seamlessly Integrate RF RF & Baseband? How to to Reduce the High Verification Cost? System Verification

38 Agilent Tools for Design & Verification Ptolemy Ptolemy Opt Opt TSDF TSDF ENV ENV HB HB Tran Tran Simulation Technology SP SP AC/DC AC/DC MoM MoM RF Cosimulation IP integration Connected Solutions

39 Baseband Integration Fixed point Filter HDL Cosim Symbolic Defined Components Compiled and Script Options

40 Updating Test Bench (Phase Noise) Ideal -3dB linewidth=30hz =0.01% of subcarrier spacing -3dB linewidth=3hz =0.001% of subcarrier spacing Simulate 3 Phase noise options Ideal Oscillator 30 Hz 3dB BW 3Hz 3dB BW With potential transmitter EVM impact

41 Exporting Modified Test Bench pre/post-tapeout 1. Modify a template design 2. Leave circuit out with ports 3. Place desired measurements 4. Verify before export 5. Export

42 EVM Results with Phase Noise -37 dbm -34 dbm Pass Fail 5.6 Max %EVM (rms) for 54 Mbps is 5.6% The new test bench includes Oscillator PN as a new option

43 Agenda Meet the Standards & Specification System vs.. Circuit (Design & Verification) Bridging the Gap Case Study WLAN Transmitter/Receiver Integration (RF + baseband + ) Bench Verification

44 On Bench Verification Signal To ESG ESG Sig. Gen. Connection Manager Signal Analyzer

45 Simulated vs. Measured for Tx Amplifier Measured % EVM % EVM Max, 54 Mbps Fail Pass Simulated Input Power dbm Power amplifier behavior under system conditions shows good agreement with system simulation results.

46 Measured Results with Phase Noise RF Input Simulated EVM w/o Phase Noise Measured EVM w/o Phase Noise Simulated EVM with Phase Noise Measured EVM with Phase Noise -34 dbm 4.38% 4.33% 5.36% 5.07%

47 Summary System Circuit Meeting the wireless specifications is a must for circuit & system designers Using an improved flow system designers can communicate specs more effectively circuit designers can verify system specs in their own home base ADS provides system level analysis + test bench export RFDE provides verification in the Cadence flow

48 Q & A

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