Design considerations for charge-compensated power MOSFET in the medium-voltage range

Transcription

1 Desig cosideratios for charge-comesated ower MOSFET i the medium-voltage rage Ralf Siemieiec, Cesar Braz, Oliver Blak Power Maagemet ad Multimarket Ifieo Techologies Austria AG. Villach, Austria Abstract Low-voltage ower MOSFET based o charge-comesatio usig a field-late offer a sigificat reductio of the area-secific o-resistace. The extesio of their blockig caability ito the so-called medium-voltage rage of 150 V V romises devices with excellet roerties beig attractive for a wide rage of alicatios. There are two aroaches how this voltage-rage extesio ca be realized. Both cocets are liked to differet device erformace ad differet develomet effort. This work discusses both cocets o examle of the 150 V device class ad comares the gaied erformace o device ad alicatio level. Keywords: MOSFET, ower device, alicatio requiremets, device desig, device erformace INTRODUCTION The geeral tred i the idustry towards the reductio i size of ower systems imoses challeges o the desig from the system dow to the semicoductor level. The advaces i ower semicoductor techologies target to lower the system s associated losses. These allows for a geeral size reductio by various meas ragig from the use of smaller magetic comoets due to the use of higher switchig frequecies to the ossibility of reducig the size of, or eve elimiatig, the heatsiks. This icrease i ower desity traslates ito more ad more challegig coditios for the ower devices. Not oly the o-resistace of the devices is reduced but also the geeral Figure of Merit (FOM G = R DS(o) Q G ), the Switchig Figure of Merit (FOM GD = RDS(o) Q GD ) ad the Figure of Merit with resect to outut charge (FOM OSS = RDS(o) Q OSS ) are miimized. I may alicatios this results i large imrovemets of the switchig seed, however this is i usually liked to higher curret ad/or voltage slew rates (di/dt ad dv/dt). At the same time the curret desity i the devices icreases (see Fig. 1) which all calls for maitaiig a high ruggedess of the devices. Low-voltage ower MOSFET exerieced dramatic imrovemets over the ast decade thaks to the alicatio of the charge-comesatio ricile to this device class. Steig forward i the wafer maufacturig techology the breakdow voltage was exteded over the years towards the voltage rage betwee 150 V 300 V. Differet to the lower voltage rage where a large umber of these devices are used i just oe or two mai alicatio fields this is fudametally differet i the higher voltage rage. Here the devices are used i may differet toologies targetig a wide rage of alicatio fields, ad markets are sigificatly more fragmeted betwee the differet tyes of alicatio. di/dt Prim./ mai switch Syc. Rect. Tyical alicatio oeratig coditios: high curret I - low di/dt high di/dt - low curret I Drives Basic relatioshi betwee arameters: high curret I - high d v/dt high d i/dt - high d v/dt I 1. Wo rs t c as e co d it io s i t h e alicatios(i, d i/dt) maybeliked to a arrow d v/dtrage 2. d v/dt secificatio has bee a tyical arameterimosfets datasheets Fig. 1: Tyical relatioshis betwee di/dt, dv/dt ad curret

2 APPLICATION REQUIREMENTS I case of the 150 V device class, a bigger market segmet is formed by ower sulies for telecommuicatio aliaces. Here the devices are usually foud i the sychroous rectificatio stage of the AC/DC coverter of ower sulies (Fig. 2) ad also at the rimary side of the isolated DC/DC brick coverters (Fig. 3). I both cases a high ower desity ad a high efficiecy are required. As voltage overshoots (sikes) should be miimized at the same time also the roerties of the iteral body diode are from imortace. The MOSFET are used both i hardad soft-switchig coditios. Low-voltage drives ruig at a battery voltage of 72 V ad 80 V are a secod alicatio field. Such devices are maily used i forklifts ad light electric vehicles (LEV), for examle battery drive vehicles at airorts ad the like. I case of low-voltage drives as schematically illustrated i Fig. 4 high currets must be cotrolled ad arallelig of devices should be easy. It is imortat to maitai a good thermal maagemet ad to offer a high ruggedess of the devices at a cometitive rice. Usually hard-switchig toologies are used. Micro iverters ad ower otimizers i solar alicatios (Fig. 5) form aother major market segmet. Mai requiremets for this alicatio are a good reliability, a high efficiecy, a high ower desity ad a cometitive ricig. Deedig o the customer hard- ad softswitchig toologies are foud. I additio a large umber of idustrial alicatios are foud, each with varyig requiremets which makes it difficult to summarize the eeds. Due to the may differet alicatio fields a methodlogy is eeded which hels to idetify the device roerties which are beeficial for all alicatios i order to focus o the imrovemet of the right device features. Such a methodology may also deliver if the device eeds to be otimized i oosig directios for differet alicatios, thereby idicatig eeds for techology derivatives. Established methodologies for such a aalysis are offered i geeral by the Quality Fuctio Deloymet [1,2]. The House-of-Quality Matrix as oe art of it ca be emloyed as a aid i determiig how roducts live u to customer eeds [3]. Fig. 6 illustrates the basic worksheet used i this rocess for aalysig the relatioshi betwee customer wishes ad roduct caabilities ad their iteractios, idetifyig develomet riorities ad icludig a bechmarkig of the ew cocets agaist redecessor ad cometitor roducts. As the required iuts are delivered from differet fuctioal uits such as marketig, egieerig ad maufacturig, the methodology also icreases the cross-fuctioal itegratio withi the orgaizatio. A examle for the alicatio of this rocedure to aalyse the alicatio requiremets with resect to ower MOSFET develomet ca be foud i earlier work [4]. Sychroous rectificatio PFC + LLC Isolated DC/DC +24 V / -48 V / -60 V systems Isolated DC/DC Fig. 2: Sychroous rectificatio stage of a ower suly uit Fig. 3: Isolated DC/DC brick coverter V DC ~ 80 V DC Fig. 4: Low-voltage drives for forklift ad LEV Fig. 5: Solar ower otimizer

3 5. Correlatio Matrix 4. Directio of Imrovemet 2. Device Characteristics thick layer field late 1. Voice of Customer By hel of the briefly described alicatio requiremet aalysis, the otimizatio criteria for a 150 V MOSFET device iteded to be used i the reviously discussed alicatio fields are derived. As such a suitable ower MOSFET device should fulfil the followig requiremets: low o-resistace R DS(o) low outut charge Q OSS low -drai charge Q GD low reverse-recovery charge Q RR high avalache ruggedess wide ackage ortfolio icl. SMD DEVICE CONCEPT 3. Relatioshi Matrix Fig. 6: House-of-Quality matrix 6. Target Values 8. Techical Assessmet 10. Imortace Ratig 7. Bech Markig 9. Imortace Ratig Basics of charge-comesatio usig a field-late Low-voltage ower MOSFETs based o chargecomesatio usig a field-late offer a sigificat reductio of the area-secific o-resistace. Such devices etered the market more tha 10 years ago ad develoed ito a kid of stadard techology for fast-switchig devices. The basics ad roerties of these devices have bee discussed i various details i may ublicatios field-late + -ei source body + -substrate Fig. 7: Schematic cross sectio of a charge-comesated device usig a field-late field-late Fig. 8: Pricile of charge-comesatio by a field-late over the years, e.g [5] - [13]. Fig. 7 gives a schematic cross sectio of such a device. I field-late tye devices, a isolated field-late rovides the mobile charges required to comesate the drift regio doors uder blockig coditios as idicated i Fig. 8. Comared to a device usig a simle laar -juctio, the electric field ow also has a comoet i the lateral directio. Fig. 9 exlais the basic differeces i the electric field for a simle -juctio ad for the case where a field-late comesates the doors i the drift regio. The alicatio of a field-late leads to a almost costat field distributio i the vertical directio sice the ioized doats i the drift regio are laterally comesated by mobile carriers i the field-late, thereby reducig the ecessary drift regio legth ad icreasig the allowed drift regio doig for a give breakdow voltage. Both cotribute to the sigificatly reduced area-secific oresistace. Sice the field-late electrode is coected to the source electrode of the MOSFET ad the is formed by a searate electrode, such a device offers a outstadig area-secific o-resistace ad a low charge at the same time. Directios of further device imrovemets To imrove the overall efficiecy i most alicatios both, o-resistace ad switchig losses, eed to be miimized at the same time i order to meet the efficiecy targets at low ad medium load coditios. It was show that those targets ca be reached by the use of imroved maufacturig setus liked to better rocess cotrol caabilities i combiatio with a otimized cell structure leadig to a icrease of the overall efficiecy level without comromisig the ruggedess of the device [14]. The extesio of the breakdow voltage rage of devices based o the ricile is without doubt very attractive, however a umber of roblems related to maufacturability ad device characteristics imose a umber of challeges.

4 E y E y y y E x E x x x Fig. 9: a) Electric field for a -juctio Aroach 1 additioal ei layer The targeted additioal blockig caability ca be realized by a secod lower-doed drift regio uder the actual comesatio structure as schematically show i Fig. 10. This allows the reutilizatio of a existig cell, but the exected area-secific o-resistace will be higher as oly a art of the structure is charge-comesated. Additioally such a aroach may also hel to avoid wafer bow issues. Fig. 11 idicates the risig wafer bow with icreasig blockig voltage withi a give device maufacturig techology usig the field-late aroach. The wafer bow is a critical issue as above a certai limit the wafers caot be rocessed aymore. The mai reasos for the rise of the bow are give by the icreasig trech deth ad icreasig field- thickess. So if the wafer bow is close to the limit, the additioal lowerdoed drift regio is a easy way to circumvet related roblems while targetig higher blockig voltages. However, there is still the eed for some additioal develomet effort as a aroriate edge-termiatio b) Electric field for a field-late structure structure is eeded. Oce this issue is addressed such a aroach allows a comaratively fast develomet of differet voltage classes at the cost of erformace, esecially at cost of area-secific o-resistace. Aroach 2 full redesig of device The required higher blockig caability ca be achieved by a aroriate desig of the device as deicted i Fig. 12. Amog other measures, the trech deth as well as the thickess of the field layer iside the trech must be icreased. Without coutermeasures, this might be liked to oe or all of the followig roblems: the wafer bow will become too large for the wafers ca be hadled i the roductio facilities as already discussed the iduced stress by the mismatch of ad silico i the trech exceeds the material limits ad leads to cracks as show i Fig. 13 the cotrol of the trech deth which is imortat for a accetable arameter tolerace becomes either + source body field-late -ei field-late - -ei + -substrate Fig. 10: Schematic cross sectio of a charge-comesated device with icreased blockig due to a additioal drift layer Fig. 11: Icrease of wafer bow with breakdow voltage for charge-comesated devices usig a field-late

5 + source body field-late field-late -ei + -substrate Fig. 12: Schematic cross sectio of a charge-comesated device desiged for a higher blockig voltage more difficult or leads to log rocess times liked to higher costs O the other had, this device will offer the best areasecific o-resistace as the full drift-regio legth is comesated. As such the cocet eables the best ossible otimizatio of the device with resect to differet alicatio requiremets. Obviously, ay effort which was set before to gai better cotrol over rocess arameters to imrove the device arameters [15] will be helful here as well. The aforemetioed roblems related to wafer bow ad cracks may be solved by a careful otimizatio of rocess arameters, aroriate selectio of used material or eve a reorderig of rocess stes. COMPARISON OF DEVICE PROPERTIES For choosig the right aroach it is from iterest to evaluate the realized device erformace o roduct level which icludes the ackage cotributio to the overall oresistace of the device. The comariso reseted i this work is doe for fully rocessed devices with a omial blockig voltage of 150 V. Fig. 14: Comariso of the roduct o-resistace of 150 V devices with resect to the discussed cocet aroaches Fig. 14 comares the o-resistace i differet ackages. All devices are so-called best-i-class devices. This meas that for each ackage tye the largest ossible chi area is used. As to be exected the devices based o a full redesig with resect to the targeted omial blockig voltage (aroach 2) show a clearly reduced o-resistace for the roduct. Fig. 15 shows imortat figure-of-merits i order to evaluate the dyamic device roerties. This comariso is imortat as the devices are widely used i alicatios where fast-switchig is required ad high switchig frequecies are demaded. As such the better oresistace of the device must ot be comromised by a high -charge, a large miller caacitace or a icreased outut charge. The comariso is doe for besti-class devices i a SSO8 ackage. Also for the dyamic roerties the devices based o a full redesig yield imroved device arameters. Sice a good avalache ruggedess is required by may alicatios it is iterestig to see if there is a differece i the behaviour for the two differet aroaches. For this ivestigatio, devices with differet active areas were characterized. I the UIS (uclamed iductive switchig) test differet values of the avalache iductor were used Fig. 13: Stress-iduced crack through a thick i the fieldlate trech Fig. 15: Comariso of the most imortat figure-of-merits of best-i-class devices i a SSO8 ackage with a omial blockig voltage of 150 V

6 Fig. 16: Comariso of avalache destructio curret desities for devices accordig to aroach 1 ad aroach 2 to cover a large rage of curret desities ad test coditios. Fig. 16 gives the comariso betwee both device cocets ad does ot reveal a sigificatly differet avalache ruggedess. Based o the reseted umbers it ca be cocluded that the additioal techological develomet effort set o a dedicated device desig for the resective voltage class is aid-off by sigificatly better overall device roerties. DEVICE PERFORMANCE IN APPLICATION The imrovemet of the device arameters gives a clear idicatio that the use of the desig aroach 2 is advatageous. However, it is fially imortat how the differet device roerties will imact the behaviour of the real alicatio. A lowered o-resistace ca hel to reduce the umber of eeded comoets which simlifies the circuitry, but also lowered voltage overshoots durig the switchig of the device may reduce desig-i efforts or hels savig costs o the assive comoet size. A better efficiecy may simlify the coolig cocet ad eable additioal savigs here. Fig. 17: Basic schematic of the secodary side of the ower suly uit usig two iterleaved LLC stages outut caacitace. The DC iut voltage is omially 380 V, the outut voltage is omially 54 V ad the outut curret is betwee 0 A ad 55 A. The switchig frequecy varies i the 100 khz rage. Fig. 17 shows the basic schematic of the secodary side of the ower suly for better uderstadig. Test results. Fig. 18 shows the efficiecy measuremet for each of the two desig aroaches. The efficiecy curves show some kiks which are related to the oeratio of the LLC coverter with its two stages: the 1 st kik shows u whe the 2 d LLC stage gets activated the 2 d kik is caused by the activatio of sychroous rectificatio i the 1 st LLC stage the 3 rd kik is due to the activatio of sychroous rectificatio i the 2 d LLC stage Device erformace i sychroous rectifier stage Test latform. The used test board reresets the AC/DC coverter of a ower suly usig two iterleaved LLC stages with 1500 W outut ower each. Details o the basic cocet of this aroach may be foud i literature [16]. The switchig frequecies of both stages ru asychroous, the curret sharig is cotrolled digitally. The rimary side uses a half-bridge toology. O the secodary side, where the devices uder test are located, a ceter-taed toology is used. The LLC uses a digital cotrol loo with automatic comesatio of the total Fig. 18: Comariso of the efficiecy of the AC/DC coverter stage usig 150 V devices of a. idetical area with differet desig aroaches

7 Fig. 19: Comariso of voltage overshoot due to body diode commutatio usig 150 V devices of idetical o-resistace with differet desig aroaches (V IN = 390 V, I OUT = 20 A) The higher effort to realize the device aroach 2 gives a clear beefit i this alicatio the eak efficiecy is icreased by 0.2 % while the efficiecy at full load icreases eve by 0.25 %. Fig. 19 idicates the voltage overshoot liked to the body diode commutatio. For the device followig aroach 2 the voltage overshoot is reduced by 5 V while at the same time the reverse recovery curret eak is smaller. Device erformace i hard-switched alicatios Test latform. The test board used to assess the devices erformace i hard-switched alicatios is a 250 W buck coverter board. The board reroduces the oeratio of a solar ower otimizer as show i Fig. 5 beig oerated i buck mode, a aroach beig discussed i Fig. 21: Comariso of the half-bridge hase ode voltage overshoot due to the body diode commutatio usig 150 V devices of idetical o-resistace (V IN = 75 V, I OUT = 4 A). more details i literature [17,18]. The iut voltage is 75 V, the outut voltage is 42 V ad the switchig frequecy is 200 khz. All switches have a idetical oresistace. Test results. Fig. 20 shows the efficiecy measuremet for each of the two MOSFET desig aroaches. Oce agai, the aroach 2 shows better erformace eve i hard-switched alicatios: the eak efficiecy is icreased by almost 0.2 % while the efficiecy at full load icreases slightly above it. Fig. 21 shows the voltage overshoot liked to the body diode commutatio. For the device followig the aroach 2, the voltage overshoot is reduced by 8 V. CONCLUSION Fig. 20: Comariso of the efficiecy of the buck coverter usig 150 V devices of a. idetical area with differet desig aroaches. This article discusses two differet device desig aroaches for extedig the blockig voltage caability of low-voltage ower MOSFETs based o the chargecomesatio ricile usig a field late. The discussed devices ited to meet the so-called medium-voltage rage of 150 V 300 V. Potetial target alicatios iclude rimary side switches ad sychroous rectificatio stages of switch-mode ower sulies, motor drives or solar ower otimizers. Devices are used both i hard- ad soft-switchig toologies. The first ad simler aroach achieved the required additioal blockig caability by havig a secod lowerdoed drift regio added uder its actual comesatio structure. This allowed the reutilizatio of existig cells at the exese of icreased area-secific o-resistace but requires the develomet of a suitable edge termiatio structure.

8 The secod aroach is based o a aroriate desig of the device. Amog other measures, icreased trech deth ad a adated field layer thickess has bee show to meet the required blockig caability. This aroach offers the best area-secific o-resistace as the full driftregio legth is comesated. As such it is exected that this secod desig cocet eables the best ossible otimizatio of the device erformace with resect to a wide rage of differet alicatio requiremets. Both desig cocets were comared o examle of devices with a blockig voltage of 150 V. As cofirmed by the reseted exerimetal results for sychroous rectificatio ad hard-switched alicatios, the secod aroach based o a secific desig for a give voltage class delivers a better overall erformace. Cosequetly, the higher develomet effort is clearly justified by the better roerties ad behaviour of the realized ower MOSFET. ACKNOWLEDGEMENTS The authors would like to thak O. Guillemat, for measuremets erformed o the Telecom rectifier, ad Abhimayu Mada, for measuremets erformed o the buck coverter. REFERENCES [1] Akao, Y.: QFD - Quality Fuctio Deloymet. Verlag Modere Idustrie, Ladsberg / Lech, 1992 [2] htt:// [3] htt:// [4] Siemieiec, R., Hutzler, M., Blak, O., Laforet, D., Yi, L.J., Huag, A. ad Walter, R.: Develomet of low-voltage ower MOSFET based o alicatio requiremet aalysis. [5] Schlögl, A., Hirler, F., Roohl, J., Hiller, U., Rösch, M., Soufi-Amlashi, N. ad Siemieiec, R.: A ew robust ower MOSFET family i the voltage rage 80 V-150 V with suerior low RDSo, excellet switchig roerties ad imroved body diode, i Proc. EPE 2005, Dresde, 2005 [6] Che, Y., Liag, Y. ad Samudra, G.: Theoretical Aalyses of Oxide-Byassed Suerjuctio Power Metal Oxide Semicoductor Field Effect Trasistor Devices, Jaaese Joural of Alied Physics, 44, 2005, [7] Pattayak, D.: Low Voltage Suer Juctio techology, i Proc. ISPS 2006, Prague, 2006 [8] Tog, F., Mawby, P. A., Covigto, J.A. ad Pérez-Tomás, A.: Ivestigatio o Slit-Gate RSO MOSFET for 30V Breakdow, i Proc. ISPS 2008, Prague, 2008 [9] Yediak, J., Probst, D., Doly, G., Challa, A. ad Adrews, J.: Otimizig Oxide Charge Balaced Devices for Uclamed Iductive Switchig (UIS), i Proc. ISPSD 2010, Hiroshima, 2010 [10] Roig, J., Lee, D., Bauwes, F., Burra, B., Rialdi, A., McDoald, J. ad Desoete, B.: Suitable Oeratio Coditios for Differet 100V Trech-Based Power MOSFETs i 48Viut Sychroous Buck Coverters, i Proc. EPE 2011, Birmigham, 2011 [11] Hossai, Z., Burra, B., Sellers, J., Pratt, B., Vekatram, P., Loechelt, G. ad Salih, A.: Process & desig imact o BVDSS stability of a shielded trech ower MOSFET, i Proc. ISPSD 2014, Waikkoloa, 2014 [12] Kobayashi, K., Nishiguchi, T., Katoh, S., Kawao, T. ad Kawaguchi, Y.: 100 V class multile steed field late trech MOSFET (MSO-FP-MOSFET) aimed to ultimate structure realizatio, i Proc. ISPSD 2015, Hog Kog, 2015 [13] Park, C., Havaur, S., Shibib, A. ad Terrill, K.: 60 V ratig slit trech MOSFETs havig best-i-class secific resistace ad figure-of-merit, i Proc. ISPSD 2016, Prague, 2016 [14] Siemieiec, R. ad Blak, O.: Power MOSFET Desig for Sychroous Rectificatio, Proc. ISPS 2012, Prague, Czech Reublic [15] Siemieiec, R., Mößlacher, C., Blak, O., Rösch, M., Frak, M. ad Hutzler, M.: A ew Power MOSFET Geeratio desiged for Sychroous Rectificatio, i Proc. EPE 2011, Birmigham, 2011 [16] Orietti, E., Mattavelli, P., Siazzi, G., Adraga, C. ad Gattavari, G.: Aalysis of multi-hase LLEC resot coverters, i Proc. Brazilia Power Electroics Coferece, Boito-Mato Grosso do Sul, 2009 [17] Berardo, P.C.M., Peixoto, Z.M.A. ad Machado Neto, L.V.B.: Ahigh efficiet micro-cotrolled buck coverter with maximum ower oit trackig for hotovoltaic systems, i Proc. ICREPQ 2009, Valecia, 2009 [18] Kaser, M., Bortis, D., Friedli, T. ad Kolar, J.W.: Classificatio ad comarative evaluatio of PV ael itegrated DC-DC coverter cocets, i Proc. EPE-PEMC 2012 ECCE Euroe, Novi Sad, 2012 Addresses of the authors Ralf Siemieiec, Ifieo Techologies Austria AG, Siemesstrasse 2, A-9500 Villach, Austria, ralf.siemieiec@ifieo.com Oliver Blak, Ifieo Techologies Austria AG, Siemesstrasse 2, A-9500 Villach, Austria, oliver.blak@ifieo.com Cesar Braz, Ifieo Techologies Austria AG, Siemesstrasse 2, A-9500 Villach, cesar.braz@ifieo.com