Optimal P/N Width Ratio Selection for Standard Cell Libraries

Transcription

1 Otimal P/N Width Ratio Selectio for Stadard Cell Libraries David S. Kug ad Ruchir Puri IBM T. J. Watso Research Ceter Yorktow Heights, NY 0598 ABSTRACT The effectiveess of logic sythesis to satisfy icreasigly tight timig costraits i dee-submicro high-erformace circuits heavily deeds o the rage ad variety of logic gates available i the stadard cell library. Primarily, research i the desig of higherformace stadard cell libraries has bee focused o drive stregth selectio of various logic gates. Sice CMOS logic circuit delays ot oly deed o the drive stregth of each gate but also o its P/N width ratio, it is crucial to rovide good P/N width ratios for each cell. The mai cotributio of this aer is the develomet of a theoretical framework through which library desigers ca determie otimal P/N width ratio for each logic gate i their high-erformace stadard cell library. This theoretical framework utilizes ew gate delay models that exlicitly rereset the deedece of delay o P/N width ratio ad load. These delay models yield highly accurate delay for CMOS gates i a 0.m L ef f dee-submicro techology. INTRODUCTION The reletless ursuit of high erformace has ushed logic ad circuit desigers to utilize every delay ad area otimizatio techique at their disosal. To emulate the flexibility of custom desigs, ASIC ad semi-custom desigers are rovidig high-erformace stadard cell libraries that ot oly offer a wide rage ad variety of gate sizes (or drive stregths) but also a wide rage of P/N width ratios for each gate size [][]. Traditioally i logic sythesis, delay otimizatio techiques have heavily relied o gate sizig algorithms [][][5] which vary drive stregths of gates to otimize circuit delay. Sice the delay i CMOS logic circuits ot oly deeds o the drive stregth of each stage but also o its P/N width ratio, it is crucial to rovide good P/N width ratios for each cell i the ASIC library for satisfyig icreasigly tight timig costraits of dee-submicro high-erformace circuits. Recet research i the area of stadard cell library desig [][7][8] has maily focused o drive stregth selectio of various logic gates. Ufortuately, there has bee o research i the directio of develoig a theoretical framework for selectig otimal P/N width ratios. I geeral, for selectig P/N width ratios of CMOS logic cells, library desigers are ofte cocered with miimizig the average of the risig ad fallig ath delays because a trasitio through a chai of CMOS gates icurs alteratig risig ad fallig trasitios [5][9][]. It is kow that achievig miimum delay through a chai of iverters requires asymmetric risig ad fallig trasitio delays [0]. Asymmetric rise ad fall delays through a CMOS gate ca be obtaied by icreasig the size of NMOS devices at the exese of PMOS device sizes or vice-versa. Due to the slower mobility of holes tha electros, the fallig gate delay through the NMOS ull-dow is more sesitive to device size chages tha the risig gate delay through the PMOS ull-u. This is illustrated i Figure which shows the variatio of fallig ad risig trasitio delays through a iverter with varyig NMOS ad PMOS device I the case of a chai of CMOS stages with eve umber of gates of same logic tye, average delay of risig ad fallig trasitio delays is equivalet to the worst case delay. However, for short aths, the average delay may differ slightly from the worst case delay i the case of asymmetric risig ad fallig gate delays. Delay (s) Risig outut trasitio delay variatio with PMOS device width 0.00 Fallig outut trasitio delay variatio with NMOS device width Device Width Icremet (um) Figure : Fallig, risig outut trasitio delay variatio with NMOS, PMOS device width resectively for a iverter i 0.m L ef f CMOS techology. width resectively. It ca be see that icreasig the size of NMOS by Wm will result i a larger decrease i fallig outut gate delay as comared to the reductio i risig outut gate delay due to same Wm icrease i PMOS size. For logic gates such as iverter, NAND, ad NORs, the PMOS device cotributes more to the iut i caacitace tha the NMOS device for equal rise ad fall delays. Thus, for these gates it is ossible to reduce the average delay by skewig the P/N width ratio i favor of ull-dow NMOS devices. However, i the case of gates such as high fai NANDs, the NMOS device cotributes more to the iut i caacitace tha the PMOS device for equal rise ad fall delays. For these gates the P/N width ratio is skewed i favor of ull-u PMOS devices to miimize average delay. There is a iheret tradeoff i makig the P/N width too small or too large. If the P/N width ratio is made too small, the risig trasitio delay becomes too large; if this ratio is made too large, it will result i a large iut i caacitace which will slow dow the driver gate. I this aer, we develo a theoretical framework through which library desigers ca determie otimal P/N width ratio for each logic gate i their high-erformace stadard cell library. This framework utilizes ew gate delay models discussed i detail i the followig Sectio. First, we roose a aalytical delay model that searates the delay deedece o load from the delay deedece o P/N width ratio. We the geeralize this aalytical delay model to accurately model device behavior i dee-submicro techologies. The results show that this geeralized delay model ca yield highly accurate delay for gates i a 0.m L ef f CMOS techology whe comared with device level simulatio results. I Sectio, these aalytical ad geeralized delay models are utilized to formulate the P/N width ratio otimizatio roblem. We show that uder the aalytical delay model, the otimal P/N width ratio of a logic gate for miimum average ath delay is ideedet of its ositio alog the circuit ath ad the etwork toology. We the exted this result to the geeralized delay model to fid otimal P/N width ratios accurately. I this case the otimal P/N width ratio of a logic gate for miimum ath delay is deedet o its load ad iut slew. However, the variatio of otimal P/N X /99/$ IEEE.

2 width ratio over the etire desig rage causes a egligible chage i the miimum delay as show by exerimetal results give i Sectio 4. For each i to i timig arc of each gate i a stadard cell library (i a 0.m L ef f CMOS techology), we rovide a otimal P/N width ratio for miimum ath delay. DELAY MODEL A W W Vdd β = W W C P (a) Y C L A B W _eff W _eff β *W _eff *W _eff Vdd C P (b) Figure : Schematic of (a) Iverter (b) NAND. = W _eff W _eff The delay of a trasitio through a CMOS logic gate is a fuctio of its load ad iut i caacitace,its P/N width ratio, ad its iut trasitio time (iutslew). I ouraalysis, we first usea delay model that is derived from a ste trasitio resose (zero iut slew) of a iverter show i Figure (a). Subsequetly, this model is geeralized to iclude exlicitly P/N width ratio (deoted as i this aer) for modelig asymmetric rise ad fall delays. Thus, we model rise-fall ad fall-rise gate delays as a exlicit fuctio of. Sice iut slew has sigificat effect o gate delays, we model slew deedece of delay by usig differet coefficiets for various slew values i our delay model. We will show that this geeralized delay model is very accurate desite its simlicity. Assumig a o-liear I-V MOSFET model: I ds = k (V gs, V t)v ds, V ds, the delay of a risig or a fallig iut ste trasitio through a iverter with outut load C l is give by: t d = C l + C k Y C L jv T j (V DD,jV T j) + V DD,jV T j l V DD, jv T j V DD where C is the iteral arasitic caacitace, V DD is the suly voltage, V T is the threshold voltage ad k is the device trascoductace. The factor jv T j k (V DD,jV T j) + V DD,jV T j l V DD,jV T j V DD ca be iterreted as the device resistace R, so the above equatio ca be simlified as t d = R(C l + C ). This simle R-C delay equatio is also kow as Elmore delay model [4][]. For a MOSFET, trascoductace arameter k is deedet o device size W, carrier mobility, ad gate caacitace er uit area Cox L W ad is give by C ox (i.e., k L = Cox W ). Sice arameters L V DD, V T,adC ox are fixed for ay give techology, we rereset T L V Cox (V DD,V T ) + V DD,V T l V DD,V T V DD as a costat k 0, assumig that all MOSFETs withi the techology are of costat legth L. This further simlifies delay t d to yield: t d = k 0 Cl + C W It is kow that both gate caacitace ad the arasitic caacitace (i.e., diffusio caacitace) of a MOSFET scale with its size. Thus, it is reasoable to assume that the ratio of arasitic caacitace (C ) of a logic gate to its iut i caacitace (C i) remais C Ci costat, i.e., = costat (K). Figure shows the variatio i the ratio of arasitic caacitace to its iut i caacitace (i.e., (Parasitic Caacitace)/(Iut Pi Caacitace) Iverter Size (total NFET ad PFET width i um) Figure : Variatio i ratio of arasitic caacitace ad iut i caacitace ( C ) with icreasig iverter size. Ci C Ci C ) for a iverter with the icrease i iverter size. It ca be see Ci that C is almost ivariat with ay chage i iverter size. We Ci utilize this ivariace of C to obtai the aalytical delay model Ci give i equatios ad. However, as discussed later, due to oliear ature of dee-submicro MOSFET, miller effect etc., may ot remai ivariat for all cases i a dee-submicro techology. Thus, we do ot utilize this ivariace i obtaiig a more ractical gate delay model give i equatios 4 ad 5. I geeral, desigers reaso about delays i terms of gai rather tha load ad iut i caacitace [][]. I this aer, we assume that the techology library i questio is desiged usig the semi-custom methodology []. Therefore we arameterize logic gates usig gai istead of size, so that gates with differet sizes of the same tye ca be modeled by the same delay equatio []. The gai from a iut i to the outut i of a CMOS gate is defied as the ratio of gate load caacitace (C l) to the iut i caacitace (C i), i.e., gai g = C l. Thus, delay td ca be Ci rewritte by substitutig C l = g C i ad C = K C i i the delay equatio above, i.e.: t d = k 0 g + K C i W I a CMOS gate, a risig iut trasitio causes the gate outut to be discharged to GND through the NMOS ull-dow tree. Similarly, a fallig iut trasitio i a CMOS gate causes the gate outut to be charged to V DD through the PMOS ull-u tree. Let W ad W be the width of the NMOS ad PMOS devices i a iverter ad let ad be the mobility of electros ad holes resectively. The, fallig ad risig ste iut delaysthrough the iverter are give by: t rf = k 0 g + K C i ; t fr = k 0 g + K C i W W The above delay equatio ca be alied to comlex CMOS gates as well by relacig W by the effective N width of ull-dow tree W eff ad relacig W by the effective P width of ull-u tree W eff. Thus, for a comlex CMOS gate: t rf = k C 0 g + K i ;t fr = k 0 g + K C i : () W eff W eff Cosider a two-iut NAND gate show i Figure (b) with effective N width W eff ad effective P width W eff ad P/N width

3 ratio = W eff. Sice the resistace through a trasistor is iversely roortioal to its width, each NMOS device i the ull- W eff dow tree has a width of W eff ad each PMOS device i the ull-u tree has a width of W eff. Thus, the caacitace of a NAND iut i is give by C i =(W eff +W eff )LC ox. Substitutig W eff = W eff, C i =(W eff +W eff ) L C ox, adk 00 = k 0 L C ox i rise ad fall delay equatios, we get the followig rise ad fall delays for a NAND: t rf = k 00 ( + )(g + K) ; t fr = k 00 ( + )(g + K) I geeral, a NMOS device i a comlex gate is assiged a width of M W eff ad a PMOS device is assiged a width of M W eff, where M ad M deote the NMOS ad PMOS multilicatio factors for a give iut i of the comlex gate []. For examle, i the case of a iverter, M =ad M =. Similarly, i the case of a NAND, M =ad M =. Due to the o-liear ature of MOSFET resistaces, the effective width of two series NMOS devices, with a width of W each, is actually more tha W. Thus, i ractice, these multilicatio factors are obtaied from AS/X simulatios of gates i a give techology. Usig these N ad P multilicatio factors, the iut i caacitace C i is exressed as (M W eff + M W eff ) L C ox. Substitutig W eff = W eff, C i =(M W eff +M W eff ) LC ox, ad k 00 = k 0 L C ox i rise ad fall delay equatios, we get the followig rise ad fall delays for a geeral CMOS comlex gate: t rf = k 00 (M + M )(g + K) ;t fr = k 00 (M + M )(g + K) The delay equatios above ca be rewritte as: t rf = k 00 MK t fr = k 00 MK + M K + MK + M + M g + M g + M g ; () g : () I the remaider of this aer, delay equatios ad are referred as aalytical delay model. It is iterestig to ote that for a fixed P/N width ratio, our aalytical delay model above actually reduces to the liear gai-delay model, delay = + l gai, emloyed i [4] ad [6]. The aalytical delay model equatios ad rovide a useful uderstadig of delay deedece o gai, P/N width ratio, carrier mobility, ad toology of CMOS gates. However, they give a over-simlified view of the CMOS gate behavior i dee-submicro techologies i additio to the fact that zero iut slew has bee assumed. I geeral, a MOSFET does ot behave as a liear resistor eve if drive by a ste iut. I additio, caacitaces i MOSFETs are time ad voltage deedet, i.e., they are dyamic i ature ad do ot have fixed values. The carrier mobility i dee-submicro techologies is modulated by high electric field effects. Also, Miller effect ca cause sigificat deviatio from the simlified view of real delays. As a result, the coefficiets of gai ad variables i delay equatios ad deviate from their simlified values. I site of these effects, we ostulate thatthe delaydeedeceogaiad retais the form of equatios ad. That meas for each timig arc (iut i to outut i coectio) of a logic gate, the rise-fall ad fall-rise delay equatios ca be writte as: t rf = 0 + arf + arf g + arf g; (4) AS/X is IBM s electrical-level simulator similar to SPICE. t fr = a fr 0 + afr + afr g + afr g (5) Sice iut slew has sigificat effect o gate delays, we model slew deedece of delay by usig a differet set of coefficiets for each iut slew value. I the remaider of this aer, delay equatios 4 ad 5 are referred as geeralized delay model. Table : Average % error ad worst case error (s) for fallig ad risig trasitio delays from geeralized delay model i comariso to AS/X simulated delays. Cell Fall-rise delay Error Rise-fall delay Error Tye Arc Average Absolute Average Absolute %Error Worst (s) %Error Worst (s) iv A ad A ad B ad A ad B ad C ad4 A ad4 B ad4 C ad4 D or A or B or A or B or C aoi A aoi A aoi B aoi A aoi A aoi B aoi A aoi A aoi B aoi B oai A oai A oai B oai A oai A oai B oai A oai A oai B oai B For every logic gate i a high-erformace stadard cell library, the delay vs. gai ad data of each timig arc are obtaied usig AS/X simulatio i a 0.m L ef f dee-submicro CMOS techology for the iut slew values 50, 00, 50, 00, 50, 00, 50 icosecods. The simulatios were erformed for omial techology arameters, i.e., a suly voltage of.8v ad a temerature of 75 o C. Tyically, desigers limit maximum gai allowed for ay give CMOS cell to 0 i order to avoid slew limit violatios; ad a gai rage of to 0 is cosidered to be reresetative of loadig coditios i high-erformace circuits [][]. I additio, desigers limit the P/N width ratio (i.e., ) of logic gates betwee ad 4 i order to avoid oise margi violatios [][]. Thus, while erformig simulatios, the gai was varied from to 0 i icremets of ad the was varied from to 4 i icremets of 0.. A least square fit is used to extract the coefficiets of the delay equatios (equatios 4 ad 5) for each set of data. For each slew value, the geeralized delay equatios 4 ad 5 model the delay behavior with very high degree of accuracy, for all the CMOS gates i the library over the etire rage of gai,, ad slew. Table shows the average % error ad worst case delay error i icosecods derived by comarig delay values The logic gates cosidered are: iverter, ad, ad, ad4, or, or, aoi, aoi, aoi, oai, oai, ad oai.

4 0.5 5 GAIN GAIN 00 DELAY s BETA (b) DELAY s BETA Figure 4: Deedece of delay (simulated) o gai ad for a AOI, i A to outut Y (a) Risig iut trasitio (b) Fallig iut trasitio. from geeralized delay model with resect to AS/X simulated delays (for a reresetative slew of 50 icosecods). It ca be see from Table that the average error i all cases is less tha.6%. Surrisigly, as show i Table our delay equatios yield eve higher degree of accuracy for comlex gates such as AOIs, OAIs, ad high fai NANDs ad NORs. Figure 4(a) shows the lot of simulated risig iut A delay of a AOI as a fuctio of gai ad P/N width ratio for a fixed slew of 50 icosecods. As discussed above, this delay ca be fitted usig the delay equatio t rf =0: :076 +0:0047 g +0:0047 g, resultig i a maximum error of. icosecods ad a average error of 0.% i comariso to the simulated delay results show i Figure 4(a). Similarly, Figure 4(b) shows the lot of simulated fallig iut A delay of a AOI as a fuctio of gai ad for a fixed slew of 50 icosecods. This delay ca be fitted usig the delay equatio t fr =0: :047 +0:0 g +0:08 g, resultig i a maximum error of.4 icosecods ad a average error of 0.% i comariso to the simulated delay results show i Figure 4(b). I the followig sectio, we utilize the delay models derived above to formulate the P/N width otimizatio roblem alog a geeral ath i CMOS logic circuits; ad develo a theoretical framework through which library desigers ca determie otimal P/N width ratio for each logic gate i their high-erformace stadard cell library. OPTIMIZING P/N WIDTH RATIO i i+ Cf Cf Cf i C C i+ C C C C C PO i (a) Figure 5: A geeral circuit ath with faouts. I this sectio, we focus o the ath delay otimizatio roblem. Cosider a geeral circuit ath show i Figure 5 where: C i deotes the i caacitace of the o-ath iut i of the i th stage. Cf i deotes the off-ath faout caacitive load drive by the i th stage. i deotes the P/N width ratio of the i th stage. C PO deotes the caacitive load of the last ( th ) stage i the ath. For the ath show i Figure 5, the gai of each CMOS stage ca be writte as: g = Cf + C ;g = C Cf + C Cfi + Ci+ ;:::g i = ;::: C C i Cf, + C :::g, = ;g = CPO C, C The risig iut ad the fallig iut delay alog the ath are give by: T r = t rf + t fr + t rf + :::; T f = t fr + t rf + t fr + ::: where t rfi ad t fri are the rise-fall ad fall-rise delay equatios for the i th gate give by equatios 4 ad 5 resectively. The average of risig ad fallig iut delays alog the ath is T av = Tr + Tf = NX i= (t rfi + t fri ): The ath delay otimizatio roblem is stated as follows: Give a ath of CMOS logic gates i a geeral logic etwork, fid a assigmet of P/N width ratio ad gai value to each logic gate such that the average of risig ad fallig iut delays alog the ath is miimized uder the costrait that C is less tha or equal to the rimary iut caacitace limit C PI. We assert that the miimum delay solutio must saturate the rimary iut caacitace limit, i.e., C = C PI at the miimum. If the miimum occurred at C <C PI, we could icrease C to C PI ad reduce g. Thus the delay of the first stage could be reduced ad we would arrive at a solutio with ath delay less tha the miimum, which is a cotradictio. I terms of the gai variables, the rimary iut caacitace costrait traslates to C PO,C PI Y i= g i +Cf Y i= g i +:::Cf j Y i=j g i +:::Cf, g +Cf = 0 (6) Therefore the cost fuctio of the ath delay otimizatio roblem ca be formulated as T = T av, f(g ;:::g ;Cf ;:::Cf ;C PO;C PI); where reresets the Lagrage multilier ad the fuctio f is the left had side of equatio 6. Although the gai ad the P/N width ratio variables are ot ideedet of each other, we show i Aedix A =0; i =0: (7) still holds at the miimum. Sice f (g ;:::g ;Cf ;:::Cf ;C PO;C PI) is ot exlicitly a fuctio : (8) I the followig subsectios, we aly equatios 7 ad 8 to to obtai the otimal P/N width ratio of each gate i the ath delay otimizatio roblem.

5 . Miimizig delay uder aalytical delay model The aalytical delay equatios for risig ad fallig iut gate delay is give by equatios ad. I this subsectio, we focus o the i th stage of the ath where the i multiliers M ad M refer to those of the i th stage. From equatios 7 ad 8 we kow that at the oit of miimum k 00 (g i + K i ) M + i =0. Thus:, (M i + M ) =0 i Solvig for i i the above equatio, we obtai a surrisigly simle result for P/N width ratio of a gate at miimum delay, i.e.: r M i = : (9) M The sigificace of this result is that the otimal P/N width ratio of ay CMOS gate deeds oly o the gate tye ad the corresodig timig arc but is etirely ideedet of the structure of the circuit ath. For examle, M =ad M =for a iverter, M = N ad M =for a N-iut NAND ad M = ad M = N for a N-iut NOR. It follows that the otimal P/N widthq ratios for q a iverter, qa N-iut NAND ad a N-iut NOR are, N ad resectively. Thus, the otimal P/N width ratio of a NOR gate is always less tha that of a N iverter while the otimal P/N width ratio of a NAND gate is always larger tha that of a iverter. As discussed i sectio, the aalytical delay model over-simlifies the realities of device behavior i dee-submicro techologies. I the ext subsectio we use the geeralized delay equatios (equatios 4 ad 5) to obtai more realistic otimal P/N width ratio for miimum average delays.. Miimizig delay uder geeralized delay model The geeralized delay equatios for risig ad fallig iut gate delay is give by equatios 4 ad 5. Agai we will focus o the i th stage of the ath. So for the rest of the subsectio, the coefficiets (a s) refer to those of the i th stage. As i the revious subsectio, the ecessary coditio at the miimum is give = Thus, at the miimum + arf gi, afr i, a fr gi i =0: (0) Comarig aalytical delay model (equatios ad ) ad the geeralized delay model (equatios 4 ad 5), we ifer that if the geeralized model followed the aalytical delay model, we will have a fr = afr ad the otimal P/N width ratio would be a fr. Let us rereset the ratio a fr =arf by a costat, i.e.: =arf Table : Variatio of Otimal P/N Width Ratio over etire gai (-0) ad slew (50s-50s) rage. Otimal P/N Ratio Max % gate delay Cell Lower Uer Recom- variatio for Tye Arc boud boud meded usig r w.r.t l u r usig l or u iv A ad A ad B ad A ad B ad C ad4 A ad4 B ad4 C ad4 D or A or B or A or B or C aoi A aoi A aoi B aoi A aoi A aoi B aoi A aoi A aoi B aoi B oai A oai A oai B oai A oai A oai B oai A oai A oai B oai B Substitutig ad i equatio0, we get:, i + g i + g i, i =0 Solvig for i i the above equatio yields: i, g = i + () + a rf g i This result shows that i ractice, the otimal P/N width ratio at which T av is miimum deeds o the gai distributio alog the ath. The amout of deedece is a fuctio of, a measure of the deviatio of the geeralized delay model from the aalytic delay model. However, the exerimetal results i the ext sectio reveal that the variatio of otimal (equatio ) over the etire gai ad slew desig rage has a egligible imact i the miimum average delay. 4 EXPERIMENTAL RESULTS = afr ; ad let us dee by a fr = : We defie aother costat that measures the deviatio of the geeralized delay model from its ideal aalytical behavior =+ Thus reduces to 0, if the geeralized delay model follows the aalytical delay model (i.e., a fr =arf = a fr =arf ). I this sectio, we discuss the effect of gai ad slew variatio o otimal P/N width ratios ad average delays of various logic gates i a 0.m L ef f dee-submicro CMOS techology. We show that usig otimal P/N width ratios for various gates i the stadard cell library ca sigificatly imrove the timig erformace of high-erformace CMOS circuits. Based o the delay coefficiets extracted i sectio, we use equatio to comute the otimal P/N width ratio as a fuctio of gai for each iut slew value. Table shows the uer ad lower bouds of the otimal P/N width ratio ( u ad l resectively) over the etire gai-slew rage

6 (i.e., gai values betwee ad 0 ad slew values betwee 50 ad 50 icosecods). Tyically, i critical regio of otimized CMOS circuits, the most frequet gai occurs i the gai iterval of to [][]. I additio, i otimized CMOS circuits, tyical slew values rage from 00 to 00s. Thus, we select a gai of ad iut slew of 50s to be the most frequetly occurrig gai, slew data values. The fifth colum i Table gives the recommeded P/N width ratio which is the otimal P/N width ratio at gai ad iut slew 50 icosecods. The last colum i Table gives the worst case ercetage delay error icurred over the etire gai-slew rage as a result of usig the recommeded P/N width ratio istead of the otimal P/N width ratio at that gai ad slew value. Although the recommeded value of otimal P/N width ratio ( r) is based o fixed gai ad slew values, the % error i delay due to selectig r istead of selectig the for that secific gai ad slew value is egligible. We illustrate this oit further i Figure 6(a) which shows the delay variatio over the lower ad uer bouds of otimal P/N width ratio [ l; u] for a secific timig arc (iut i A, outut i Y) for the NANDs ad NORs. The delay curves are all early flat, reiforcig the data i Table. However, timig arc delays are ot totally isesitive to variatios. I Figure 6(b) we exted the lot of Figure 6(a) to a much larger rage of. It is clear that if a P/N width ratio is chose i the stee art of the curves, the gate delay ca be substatially larger tha the otimal oe. Therefore it is articularly imortat to select a P/N width ratio close to the value recommeded ( r)itable. Table : Imact of otimal P/N ratio o real desigs Stadard cell library with: Desig P/N width ratio for P/N width ratio equal balaced rise/fall delay to otimal value (i.e., r) Worst Slack(s) Area Worst Slack(s) Area d d d d d d d d Total We ow ivestigate the imact our theoretical results have o real desigs. I geeral, for every logic gate, a library cell with value that yields balaced rise ad fall trasitio delays is always reset i the stadard cell library. Although a value yieldig equal rise ad fall trasitio delays is otimum for oise, most ofte, it is ot otimum for seed 4. We exerimeted with several desig artitios from cotrol logic of a 800MHz microrocessor desig i 0.m L ef f dee-submicro techology. Each desig artitio was sythesized twice. First, we sythesized the desig with a stadard cell library that cotais logic cells with P/N width ratios yieldig balaced rise/fall trasitio gate delays. The P/N width ratios corresodig to balaced rise/fall delays for various gates i this library were: iverter (.7), ad (.6), ad (4.), ad4(5.0), or (.95), or (.5), aoi (.7), aoi (.7), aoi (.7), oai (.7), oai (.78), ad oai (.58). Subsequetly, we sythesized the desigs usig the library with otimal P/N width ratios show i Table. For almost all desig artitios, the library with otimal P/N width ratio yielded sigificatly better worst case delay (slack) with almost o ealty i area. Results o some of the desig artitios are show i Table. As show, o a average, the worst slack imroved by.5% with oly a.6% icrease i area by usig otimal P/N width ratio cells as comared to balaced rise/fall delay cells. Thus, it is crucial for library desigers 4 Some critical circuit aths may yield better worst case delay with values differet from the otimal oes due to differet risig ad fallig trasitio arrival times assertios o rimary iuts. to iclude library cells with otimal P/N width ratios i their higherformace desig library. 5 CONCLUSION I this aer, we develoed a theoretical framework through which library desigers ca determie otimal P/N width ratio for each logic gate i their high-erformace stadard cell library. This theoretical framework utilizes ew gate delay models that exlicitly rereset the deedece of delay o P/N width ratio ad load. These delay models yield highly accurate delay for CMOS gates i a 0.m L ef f dee-submicro techology. For each timig arc of a set of commoly used cells i a high-erformace stadard cell library (i 0.m L ef f CMOS techology), we derived a P/N width ratio that gives ractically otimal delay withi a ormal rage of iut slew ad outut load. Exerimetal results with real desigs demostrated that selectio of good P/N width ratios i stadard cell library is crucial for achievig higher-erformace. It is well kow that delay trades off with oise margi through varyig the P/N width ratio. Usig our theoretical framework to study oise issues is a atural extesio of this work. Aedix A The gai of the i th stage deeds o the P/N width ratio of the i th ad i + th stage through the i caacitaces. However, we ca formulate the ath delay miimizatio roblem i terms of ideedet variables such as the effective N-fet widths (W i s) ad the P/N width ratios ( i s). The g i is a fuctio of W i, i, W i+, i+. For examle, uder the aalytic delay model g i = Cfi + M i+ W i+ + M i+ i+w i+ M iw i + M i iw i ; Let the ath delay cost fuctio T be formulated as a fuctio of g s ad s, F ( ;::: ;g ;:::g ), ad equivaletly as a fuctio of W s ad s, F 0 ( ;::: ;W ;:::W ). That meas F ad F 0 ca be trasformed ito oe aother by a chage of variable. The artial derivatives of the two equivalet fuctios are related by the followig air of equatios @gi, i where i rus from to. Sice ad W are ideedetvariables the miimum of F 0 occurs at i =0: for each i accordig to the Kuh-Tucker coditio. The Jacobia of the chage of variable is o-zero, therefore at the miimum of F =0; i = 0 also hold for each i: [] F. Beeftik, P. Kudva, D. Kug, ad L. Stok. Gate-Size Selectio for Stadard Cell Libraries. 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