Summary of pn-junction (Lec )

Transcription

1 Lecture #12 OUTLNE iode aalysis ad applicatios cotiued The MOSFET The MOSFET as a cotrolled resistor Pich-off ad curret saturatio Chael-legth modulatio Velocity saturatio i a short-chael MOSFET Readig Rabaey Sectio 3.3 (page ) Hambley Chapter 10 EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 1 Summary of p-juctio (Lec ) Two major currets i a p juctio iffusio curret: carriers flow from where there are may to where there are few Electros diffuse from -side to p-side ad holes diffuse from p-side to -side both result i positive curret from p to side rift curret: carriers flow due to electric field Electric field exists i the depletio regio oly (this is the depletio approximatio) Electric field poits from side to p side, sweepig electros from p- side (miority) to -side ad holes from -side (miority also) to p- side resultig positive curret from to p side V p EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 2

2 Summary of p-juctio (Lec ) Uder zero bias (0V), the two currets are equal et curret =0 Uder forward bias, the potetial barrier is reduced drift curret is reduced ad diffusio curret icreases (positive et curret) Curret icreases expoetially with icreasig forward bias The carriers become miority carriers oce they cross the juctio; as they diffuse i the quasi-eutral regios, they recombie with majority carriers (supplied by the metal cotacts) Uder reverse bias, the potetial barrier is icreased drift curret domiates (egative et curret) But sice the carriers that create drift currets are miority carriers, drift curret is carrier limited ad remais to be very small ad saturates with large reverse bias V (A) V (V) EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 3 Light Emittig iode (LE) LEs are made of compoud semicoductor materials Carriers diffuse across a forward-biased juctio ad recombie i the quasi-eutral regios optical emissio EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 4

3 Solar cell: Example of simple PN juctio What is a solar cell? evice that coverts sulight ito electricity How does it work? simple cofiguratio, it is a diode made of PN juctio cidet light is absorbed by material Creates electro-hole pairs that trasport through the material through iffusio (cocetratio gradiet) rift (due to electric field) PN Juctio iode EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 5 Optoelectroic iodes (cot d) Light icidet o a p juctio geerates electro-hole pairs The carriers that are geerated i the depletio regio ad the miority carriers that are geerated i the quasi-eutral regios that diffuse ito the depletio regio ad are swept across the juctio by the electric field This results i a additioal compoet of curret flowig i the diode: qv kt = S ( e 1) optical where optical is proportioal to the itesity of the light EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 6

4 Photovoltaic (Solar) Cell qv kt = S ( e 1) optical (A) i the dark V (V) with icidet light operatig poit EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 7 Photodiode A itrisic regio is placed betwee the p-type ad -type regios W j W i-regio, so that most of the electro-hole pairs are geerated i the depletio regio faster respose time (~10 GHz operatio) (A) i the dark operatig poit V (V) with icidet light EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 8

5 Photodetector Circuit Usig Load Lie V Th R Th V operatig poits uder differet light coditios. As light itesity icreases. Why? As light shies o the photodiode, carriers are geerated by absorptio. These excess carriers are swept by the electric field at the juctio creatig drift curret, which is same directio as the reverse bias curret ad hece egative curret. The curret is proportioal to light itesity ad hece ca provide a direct measuremet of light itesity photodetector. - What happes whe R th is too large? - Why use Vth? V Th V Th /R Th load lie V EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 9 iodes i Circuits Use piece-wise liear model EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 10

6 Power Coversio Circuits Covertig AC to C Potetial applicatios: Chargig a battery V =V m si (ωt) R V o EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 11 Equivalet circuit V>0.6V, diode = short circuit V o =V -0.6 V<0.6V, diode = ope circuit Vo=0 EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 12

7 Half-wave Rectifier Circuits Addig a capacitor: what does it do? V m si (ωt) C R V 0 - EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 13 Half-wave Rectifier Curret chargig up capacitor EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 14

8 Why are p Juctios mportat for Cs? The basic buildig block i digital Cs is the MOS trasistor, whose structure cotais reverse-biased diodes. p juctios are importat for electrical isolatio of trasistors located ext to each other at the surface of a Si wafer. The juctio capacitace of these diodes ca limit the performace (operatig speed) of digital circuits EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 15 evice solatio usig p Juctios regios of -type Si p-type Si No curret flows if voltages are applied betwee -type regios, because two p juctios are back-to-back -regio -regio p-regio => -type regios isolated i p-type substrate ad vice versa EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 16

9 Trasistor A Trasistor B p-type Si We ca build large circuits cosistig of may trasistors without worryig about curret flow betwee devices. The p- juctios isolate the trasistors because there is always at least oe reverse-biased p- juctio i every potetial curret path. EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 17 Moder Field Effect Trasistor (FET) A electric field is applied ormal to the surface of the semicoductor (by applyig a voltage to a overlyig gate electrode), to modulate the coductace of the semicoductor Modulate drift curret flowig betwee 2 cotacts ( source ad drai ) by varyig the voltage o the gate electrode Metal-oxide-semicoductor (MOS) FET: EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 18

10 MOSFET NMOS: N-chael Metal Oxide Semicoductor GATE W L L = chael legth W = chael width Metal (heavily doped poly-si) oxide isulator p-type silico RAN SOURCE A GATE electrode is placed above (electrically isulated from) the silico surface, ad is used to cotrol the resistace betwee the SOURCE ad RAN regios EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 19 N-chael MOSFET S G gate oxide isulator p Without a gate voltage applied, o curret ca flow betwee the source ad drai regios. Above a certai gate-to-source voltage (threshold voltage V T ), a coductig layer of mobile electros is formed at the Si surface beeath the oxide. These electros ca carry curret betwee the source ad drai. EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 20

11 N-chael vs. P-chael MOSFETs NMOS poly-si PMOS p poly-si p p p-type Si -type Si For curret to flow, V GS > V T Ehacemet mode: V T > 0 epletio mode: V T < 0 Trasistor is ON whe V G =0V For curret to flow, V GS < V T Ehacemet mode: V T < 0 epletio mode: V T > 0 Trasistor is ON whe V G =0V ( deotes very heavily doped -type material; p deotes very heavily doped p-type material) EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 21 MOSFET Circuit Symbols NMOS G G poly-si S S p-type Si PMOS p poly-si G G p p S S -type Si EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 22

12 MOSFET Termials The voltage applied to the GATE termial determies whether curret ca flow betwee the SOURCE & RAN termials. For a -chael MOSFET, the SOURCE is biased at a lower potetial (ofte 0 V) tha the RAN (Electros flow from SOURCE to RAN whe V G > V T ) For a p-chael MOSFET, the SOURCE is biased at a higher potetial (ofte the supply voltage V ) tha the RAN (Holes flow from SOURCE to RAN whe V G < V T ) The BOY termial is usually coected to a fixed potetial. For a -chael MOSFET, the BOY is coected to 0 V For a p-chael MOSFET, the BOY is coected to V EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 23 NMOSFET G vs. V GS Characteristic Cosider the curret G (flowig ito G) versus V GS : V GS G S G oxide semicoductor V S G always zero! The gate is isulated from the semicoductor, so there is o sigificat (steady) gate curret. V GS EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 24

13 The MOSFET as a Cotrolled Resistor The MOSFET behaves as a resistor whe V S is low: rai curret icreases liearly with V S Resistace R S betwee SOURCE & RAN depeds o V GS R S is lowered as V GS icreases above V T oxide thickess t ox NMOSFET Example: V GS = 2 V V GS = 1 V > V T V S S = 0 if V GS < V T versio charge desity Q i (x) = -C ox [V GS -V T -V(x)] where C ox ε ox / t ox EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 25 Sheet Resistace Revisited Cosider a sample of -type semicoductor: V _ W homogeeously doped sample t L R s ρ = = = = t σt qµ t µ Q where Q is the charge per uit area EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 26

14 NMOSFET vs. V S Characteristics Next cosider (flowig ito ) versus V S, as V GS is varied: V GS S G oxide semicoductor V S V GS > V T zero if V GS < V T V S Above threshold (V GS > V T ): iversio layer of electros appears, so coductio betwee S ad is possible Below threshold (V GS < V T ): o charge o coductio EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 27 MOSFET as a Cotrolled Resistor (cot d) V = R R S = R S S s ( L / W ) = L / W µ Q We ca make R S low by W L i µ C ( V L / W applyig a large gate drive (V GS V T ) makig W large ad/or L small = ox GS V 2 V S = µ Cox ( VGS VT ) T V V 2 S S ) average value of V(x) EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 28

15 Charge i a N-Chael MOSFET V GS < V T : depletio regio (o iversio layer at surface) V GS > V T : V S 0 V S > 0 (small) = WQ = WQ = WQ iv iv µ iv v E V µ L S Average electro velocity v is proportioal to lateral electric field E EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 29 What Happes at Larger V S? V GS > V T : V S = V GS V T versio-layer is piched-off at the drai ed V S > V GS V T As V S icreases above V GS V T V SAT, the legth of the pich-off regio L icreases: extra voltage (V S V sat ) is dropped across the distace L the voltage dropped across the iversio-layer resistor remais V sat the drai curret saturates Note: Electros are swept ito the drai by the E-field whe they eter the pich-off regio. EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 30

16 Summary of vs. V S As V S icreases, the iversio-layer charge desity at the drai ed of the chael is reduced; therefore, does ot icrease liearly with V S. Whe V S reaches V GS V T, the chael is piched off at the drai ed, ad saturates (i.e. it does ot icrease with further icreases i V S ). V GS S G V S > V GS - V T SAT = µ C ox W 2L ( V V ) 2 GS T - V GS - V T pich-off regio EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 31 vs. V S Characteristics The MOSFET -V S curve cosists of two regios: 1) Resistive or Triode Regio: 0 < V S < V GS V T = k where W L k 2) Saturatio Regio: V S > V GS V T k W SAT = VGS V 2 L where k = µ C VGS V = µ C ( ) ox ox T V 2 T S 2 V process trascoductace parameter S CUTOFF regio: V G < V T EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 32

17 Chael-Legth Modulatio f L is small, the effect of L to reduce the iversio-layer resistor legth is sigificat icreases oticeably with L (i.e. with V S ) = (1 λv S ) λ is the slope is the itercept V S EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 33 P-Chael MOSFET vs. V S As compared to a -chael MOSFET, the sigs of all the voltages ad the currets are reversed: Short-chael PMOSFET -V Note that the effects of velocity saturatio are less proouced tha for a NMOSFET. Why is this the case? EE40 Summer 2006: Lecture 12 structor: Octavia Florescu 34