HEXFET MOSFET TECHNOLOGY

Transcription

1 PD A POWER MOSFET SURFACE MOUNT (SMD-1) IRFNG V, N-CHANNEL HEXFET MOSFET TECHNOLOGY Product Summary Part Number RDS(o) ID IRFNG40 3.5Ω 3.9A HEXFET MOSFET techology is the key to Iteratioal Rectifier s advaced lie of power MOSFET trasistors. The efficiet geometry desig achieves very low o-state resistace combied with high trascoductace. HEXFET trasistors also feature all of the well-established advatages of MOSFETs, such as voltage cotrol, very fast switchig, ease of parallelig ad electrical parameter temperature stability. They are well-suited for applicatios such as switchig power supplies, motor cotrols, iverters, choppers, audio amplifiers, high eergy pulse circuits, ad virtually ay applicatio where high reliability is required. The HEXFET trasistor s totally isolated package elimiates the eed for additioal isolatig material betwee the device ad the heatsik. This improves thermal efficiecy ad reduces drai capacitace. SMD-1 Features: Simple Drive Requiremets Ease of Parallelig Hermetically Sealed Electrically Isolated Dyamic dv/dt Ratig Surface mout Light-weight Absolute Maximum Ratigs Parameter VGS = 10V, TC = 25 C Cotiuous Drai Curret 3.9 VGS = 10V, TC = 100 C Cotiuous Drai Curret 2.5 IDM Pulsed Drai Curret ➀ 15.6 TC = 25 C Max. Power Dissipatio 125 W Uits Liear Deratig Factor 1.0 W/ C VGS Gate-to-Source Voltage ±20 V EAS Sigle Pulse Avalache Eergy ➁ 530 mj IAR Avalache Curret ➀ 3.9 A EAR Repetitive Avalache Eergy ➀ 12.5 mj dv/dt Peak Diode Recovery dv/dt ➂ 1.0 V/s TJ Operatig Juctio -55 to 150 TSTG Storage Temperature Rage Package Moutig Surface Temperature 300(for 5 secods) o C Weight 2.6 (Typical) g A For foototes refer to the last page 1 2/11/02

2 Electrical Tj = 25 C (Uless Otherwise Specified) Parameter Mi Typ Max Uits Test Coditios BVDSS Drai-to-Source Breakdow Voltage 1000 V VGS = 0V, ID = 1.0mA BVDSS/ TJ Temperature Coefficiet of Breakdow 1.4 V/ C Referece to 25 C, ID = 1.0mA Voltage RDS(o) Static Drai-to-Source O-State 3.5 VGS = 10V, ID = 2.5A Ω Resistace 4.2 VGS = 10V, ID = 3.9A ➃ VGS(th) Gate Threshold Voltage V VDS = VGS, ID = 250µA gfs Forward Trascoductace 3.3 S ( ) VDS > 15V, IDS = 2.5A ➃ IDSS Zero Gate Voltage Drai Curret 25 VDS= 800V,VGS=0V 250 µa VDS = 800V, VGS = 0V, TJ = 125 C IGSS Gate-to-Source Leakage Forward 100 VGS = 20V IGSS Gate-to-Source Leakage Reverse -100 A VGS = -20V Qg Total Gate Charge 120 VGS =10V, ID =3.9A Qgs Gate-to-Source Charge 12 C VDS = 500V Qgd Gate-to-Drai ( Miller ) Charge 66 td(o) Tur-O Delay Time 30 VDD = 500V, ID = 3.9A, tr Rise Time 50 VGS =10V,RG = 9.1Ω td(off) Tur-Off Delay Time 170 s tf Fall Time 50 LS + LD Total Iductace 4.0 H Measured from the ceter of drai pad to ceter of source pad. Ciss Iput Capacitace 1700 VGS = 0V, VDS = 25V Coss Output Capacitace 250 pf f = 1.0MHz Crss Reverse Trasfer Capacitace 100 Ω Source-Drai Diode Ratigs ad Characteristics Parameter Mi Typ Max Uits Test Coditios IS Cotiuous Source Curret (Body Diode) 3.9 A ISM Pulse Source Curret (Body Diode) ➀ 15.6 VSD Diode Forward Voltage 1.8 V Tj = 25 C, IS = 3.9A, VGS = 0V ➃ trr Reverse Recovery Time 1000 S Tj = 25 C, IF = 3.9A, di/dt 100A/µs QRR Reverse Recovery Charge 5.6 µc VDD 50V ➃ to Forward Tur-O Time Itrisic tur-o time is egligible. Tur-o speed is substatially cotrolled by LS + LD. Thermal Resistace Parameter Mi Typ Max Uits Test Coditios RthJC Juctio-to-Case 1.0 C/W For foototes refer to the last page 2

3 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 3.9A Fig 3. Typical Trasfer Characteristics Fig 4. Normalized O-Resistace Vs. Temperature 3

4 ID =3.9A 13a & b Fig 5. Typical Capacitace Vs. Drai-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 7. Typical Source-Drai Diode Forward Voltage Fig 8. Maximum Safe Operatig Area 4

5 V DS R D R G V GS D.U.T. + - V DD 10V Pulse Width 1 µs Duty Factor 0.1 % Fig 10a. Switchig Time Test Circuit V DS 90% Fig 9. Maximum Drai Curret Vs. Case Temperature 10% V GS t d(o) t r t d(off) t f Fig 10b. Switchig Time Waveforms 10 Thermal Respose (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc + TC t 1, Rectagular Pulse Duratio (sec) PDM t1 t2 Fig 11. Maximum Effective Trasiet Thermal Impedace, Juctio-to-Case 5

6 15V V DS L DRIVER R G 20V 1 tp D.U.T. I AS 0.01Ω + - V DD A Fig 12a. Uclamped Iductive Test Circuit tp V (BR)DSS Fig 12c. Maximum Avalache Eergy Vs. Drai Curret I AS Fig 12b. Uclamped Iductive Waveforms Curret Regulator Same Type as D.U.T. 50KΩ 10 V Q GS Q G Q GD 12V 0.2µF.3µF D.U.T. + V - DS V G V GS 3mA Charge I G I D Curret Samplig Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6

7 Foototes: ➀ Repetitive Ratig; Pulse width limited by maximum juctio temperature. ➁ VDD = 50V, startig TJ = 25 C, L= 69mH Peak IL = 3.9A, VGS = 10V ➂ ISD 3.9A, di/dt 100A/µs, VDD 1000V, TJ 150 C ➃ Pulse width 300 µs; Duty Cycle 2% Case Outlie ad Dimesios SMD-1 PAD ASSIGNMENTS 1- DRAIN 2- GATE 3- SOURCE IR WORLD HEADQUARTERS: 233 Kasas St., El Segudo, Califoria 90245, USA Tel: (310) TAC Fax: (310) Visit us at for sales cotact iformatio. Data ad specificatios subject to chage without otice. 02/02 7