RAD-Hard HEXFET TECHNOLOGY. n Single Event Effect (SEE) Hardened n n n n n n n n

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1 PD F RADIATION HARDENED POWER MOSFET THRU-HOLE (TO-39) IRHF930 JANSR2N7389 0V, P-CHANNEL REF: MIL-PRF-9500/630 RAD-Hard HEXFET TECHNOLOGY Product Summary Part Number Radiatio Level RDS(o) ID QPL Part Number IRHF930 0K Rads (Si) 0.30Ω -6.5A JANSR2N7389 IRHF K Rads (Si) 0.30Ω -6.5A JANSF2N7389 Iteratioal Rectifier s RAD-Hard HEXFET TM techology provides high performace power MOSFETs for space applicatios. This techology has over a decade of prove performace ad reliability i satellite applicatios. These devices have bee characterized for both Total Dose ad Sigle Evet Effects (SEE). The combiatio of low Rds(o) ad low gate charge reduces the power losses i switchig applicatios such as DC to DC coverters ad motor cotrol. These devices retai all of the well established advatages of MOSFETs such as voltage cotrol, fast switchig, ease of parallelig ad temperature stability of electrical parameters. TO-39 Features: Sigle Evet Effect (SEE) Hardeed Low RDS(o) Low Total Gate Charge Proto Tolerat Simple Drive Requiremets Ease of Parallelig Hermetically Sealed Ceramic Package Light Weight Absolute Maximum Ratigs Parameter VGS = -2V, TC = 25 C Cotiuous Drai Curret -6.5 VGS = -2V, TC = 0 C Cotiuous Drai Curret -4. IDM Pulsed Drai Curret ➀ -26 Pre-Irradiatio Uits TC = 25 C Max. Power Dissipatio 25 W Liear Deratig Factor 0.2 W/ C VGS Gate-to-Source Voltage ±20 V EAS Sigle Pulse Avalache Eergy ➁ 65 mj IAR Avalache Curret ➀ -6.5 A EAR Repetitive Avalache Eergy ➀ 2.5 mj dv/dt Peak Diode Recovery dv/dt ➂ -22 V/s TJ Operatig Juctio -55 to 50 TSTG Storage Temperature Rage Lead Temperature 300 ( i. (.6mm) from case for s) o C Weight 0.98 (typical) g For foototes refer to the last page A 2/8/03

2 IRHF930 Pre-Irradiatio Electrical Tj = 25 C (Uless Otherwise Specified) Parameter Mi Typ Max Uits Test Coditios BVDSS Drai-to-Source Breakdow Voltage V VGS = 0V, ID =-.0mA BVDSS/ TJ Temperature Coefficiet of Breakdow -0.2 V/ C Referece to 25 C, ID = -.0mA Voltage RDS(o) Static Drai-to-Source O-State 0.30 VGS = -2V, ID = -4.A➃ Resistace 0.35 Ω VGS = -2V, ID = -6.5A➃ VGS(th) Gate Threshold Voltage V VDS = VGS, ID = -.0mA gfs Forward Trascoductace 2.5 S ( ) VDS >-5V, IDS = -4.A ➃ IDSS Zero Gate Voltage Drai Curret -25 VDS= -80V,VGS=0V µa -250 VDS = -80V, VGS = 0V, TJ = 25 C IGSS Gate-to-Source Leakage Forward VGS = -20V A IGSS Gate-to-Source Leakage Reverse 0 VGS = 20V Qg Total Gate Charge 45 VGS =-2V, ID = -6.5A Qgs Gate-to-Source Charge C VDS = -50V Qgd Gate-to-Drai ( Miller ) Charge 25 td(o) Tur-O Delay Time 30 VDD = -50V, ID = -6.5A, tr Rise Time 50 VGS =-2V, RG = 7.5Ω s td(off) Tur-Off Delay Time 70 tf Fall Time 70 LS + LD Total Iductace 7.0 H Measured from drai lead (6mm/0.25i. from package) to source lead (6mm/0.25i. from package) Ciss Iput Capacitace 200 VGS = 0V, VDS = -25V Coss Output Capacitace 290 pf f =.0MHz Crss Reverse Trasfer Capacitace 76 Source-Drai Diode Ratigs ad Characteristics Parameter Mi Typ Max Uits Test Coditios IS Cotiuous Source Curret (Body Diode) -6.5 ISM Pulse Source Curret (Body Diode) ➀ -26 A Ω VSD Diode Forward Voltage -3.0 V Tj = 25 C, IS = -6.5A, VGS = 0V ➃ trr Reverse Recovery Time 250 S Tj = 25 C, IF = -6.5A, di/dt A/µs QRR Reverse Recovery Charge 0.74 µc VDD -50V ➃ to Forward Tur-O Time Itrisic tur-o time is egligible. Tur-o speed is substatially cotrolled by LS + LD. Thermal Resistace Parameter Mi Typ Max Uits Test Coditios RthJC Juctio-to-Case 5.0 C/W RthJA Juctio-to-Ambiet 75 Typical socket mout Note: Correspodig Spice ad Saber models are available o the G&S Website. For foototes refer to the last page 2

3 Pre-Irradiatio Radiatio Characteristics IRHF930 Iteratioal Rectifier Radiatio Hardeed MOSFETs are tested to verify their radiatio hardess capability. The hardess assurace program at Iteratioal Rectifier is comprised of two radiatio eviromets. Every maufacturig lot is tested for total ioizig dose (per otes 5 ad 6) usig the TO-3 package. Both pre- ad post-irradiatio performace are tested ad specified usig the same drive circuitry ad test coditios i order to provide a direct compariso. Table. Electrical Tj = 25 C, Post Total Dose Irradiatio ➄➅ Parameter 0K Rads(Si) 300K Rads (Si) 2 Uits Test Coditios Mi Max Mi Max BV DSS Drai-to-Source Breakdow Voltage V V GS = 0V, I D = -.0mA VGS(th) Gate Threshold Voltage VGS = V DS, I D = -.0mA I GSS Gate-to-Source Leakage Forward A V GS = -20V I GSS Gate-to-Source Leakage Reverse 0 0 V GS = 20 V I DSS Zero Gate Voltage Drai Curret µa V DS =-80V, V GS =0V R DS(o) Static Drai-to-Source ➃ Ω VGS = -2V, I D =-4.A O-State Resistace (TO-3) R DS(o) Static Drai-to-Source ➃ Ω VGS = -2V, I D =-4.A O-State Resistace (TO-39) V SD Diode Forward Voltage ➃ V V GS = 0V, IS = -6.5A. Part umber IRHF930 (JANSR2N7389) 2. Part umber IRHF9330 (JANSF2N7389) Iteratioal Rectifier radiatio hardeed MOSFETs have bee characterized i heavy io eviromet for Sigle Evet Effects (SEE). Sigle Evet Effects characterizatio is illustrated i Fig. a ad Table 2. Table 2. Sigle Evet Effect Safe Operatig Area Io LET MeV/(mg/cm²)) Eergy (MeV) Rage VGS=5V Cu Br I VDS Cu Br I Fig a. Sigle Evet Effect, Safe Operatig Area For foototes refer to the last page 3 VGS

4 IRHF930 Pre-Irradiatio -I D, Drai-to-Source Curret (A) 0 VGS TOP -5V -2V -V -9.0V -8.0V -7.0V -6.0V BOTTOM -5.0V -5.0V 20µs PULSE WIDTH T J = 25 C 0 -V DS, Drai-to-Source Voltage (V) -I D, Drai-to-Source Curret (A) 0 VGS TOP -5V -2V -V -9.0V -8.0V -7.0V -6.0V BOTTOM -5.0V -5.0V 20µs PULSE WIDTH T J = 50 C 0 -V DS, Drai-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics -I D, Drai-to-Source Curret (A) 0 T J = 25 C T J = 50 C V DS= -50V 20µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(o), Drai-to-Source O Resistace (Normalized) 2.5 I D = -6.5A V GS = -2V T J, Juctio Temperature ( C) Fig 3. Typical Trasfer Characteristics Fig 4. Normalized O-Resistace Vs. Temperature 4

5 Pre-Irradiatio IRHF930 C, Capacitace (pf) 2000 VGS = 0V, f = MHz Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd 500 C iss 00 C oss 500 C rss 0 0 -V DS, Drai-to-Source Voltage (V) -V GS, Gate-to-Source Voltage (V) I = D -6.5 V DS =-80V V DS =-50V V DS =-20V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (C) Fig 5. Typical Capacitace Vs. Drai-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage -I SD, Reverse Drai Curret (A) 0 T J = 50 C T J = 25 C V GS = 0 V V SD,Source-to-Drai Voltage (V) -I I D, Drai Curret (A) 0 OPERATION IN THIS AREA LIMITED BY R DS(o) 0us ms TC = 25 C TJ = 50 C Sigle Pulse ms V DS, Drai-to-Source Voltage (V) Fig 7. Typical Source-Drai Diode Forward Voltage Fig 8. Maximum Safe Operatig Area 5

6 IRHF930 Pre-Irradiatio 7.0 V DS R D -I D, Drai Curret (A) R G V GS V GS Pulse Width µs Duty Factor 0. % D.U.T. Fig a. Switchig Time Test Circuit + - V DD T, Case Temperature ( C C) Fig 9. Maximum Drai Curret Vs. Case Temperature t d(o) t r t d(off) t f % 90% V DS Fig b. Switchig Time Waveforms Thermal Respose (Z thjc ) SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc + TC t, Rectagular Pulse Duratio (sec) PDM t t2 Fig. Maximum Effective Trasiet Thermal Impedace, Juctio-to-Case 6

7 Pre-Irradiatio IRHF930 Fig 2a. Uclamped Iductive Test Circuit I AS V DS L R G D.U.T V DD I AS A -20V V GS DRIVER t p 0.0Ω 5V E AS, Sigle Pulse Avalache Eergy (mj) I D TOP -2.9A -4.A BOTTOM -6.5A Startig T, Juctio Temperature ( J C) Fig 2c. Maximum Avalache Eergy Vs. Drai Curret tp V (BR)DSS Fig 2b. Uclamped Iductive Waveforms Curret Regulator Same Type as D.U.T. -2V Q G -2V.2µF 50KΩ.3µF Q GS Q GD D.U.T. + V DS - V G V GS -3mA Charge I G I D Curret Samplig Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 7

8 IRHF930 Foot Notes: ➀ Repetitive Ratig; Pulse width limited by maximum juctio temperature. ➁ VDD = -25V, startig TJ = 25 C, L=7.8mH Peak IL = -6.5A, VGS =-2V ➂ ISD -6.5A, di/dt -430A/µs, VDD V, TJ 50 C Pre-Irradiatio ➃ Pulse width 300 µs; Duty Cycle 2% ➄ Total Dose Irradiatio with VGS Bias. -2 volt VGS applied ad VDS = 0 durig irradiatio per MIL-STD-750, method 9, coditio A. ➅ Total Dose Irradiatio with VDS Bias. -80 volt VDS applied ad VGS = 0 durig irradiatio per MlL-STD-750, method 9, coditio A. Case Outlie ad Dimesios TO-205AF(Modified TO-39) LEGEND - SOURCE 2- GATE 3- DRAIN IR WORLD HEADQUARTERS: 233 Kasas St., El Segudo, Califoria 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales cotact iformatio. Data ad specificatios subject to chage without otice. 02/03 8