RAD-Hard HEXFET TECHNOLOGY. n n n n n n n n

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1 PD D RADIATION HARDENED POWER MOSFET THRU-HOLE (TO-257AA) JANSR2N738 V, N-CHANNEL REF: MIL-PRF-95/64 RAD-Hard HEXFET TECHNOLOGY Product Summary Part Number Radiatio Level RDS(o) ID QPL Part Number K Rads (Si).8Ω 4.4A JANSR2N738 IRHY33CM 3K Rads (Si).8Ω 4.4A JANSF2N738 IRHY43CM 6K Rads (Si).8Ω 4.4A JANSG2N738 IRHY83CM K Rads (Si).8Ω 4.4A JANSH2N738 Iteratioal Rectifier s RADHard HEXFET techology provides high performace power MOSFETs for space applicatios. This techology has over a decade of prove performace ad reliability i satellite applicatios. These devices have bee characterized for both Total Dose ad Sigle Evet Effects (SEE). The combiatio of low Rds(o) ad low gate charge reduces the power losses i switchig applicatios such as DC to DC coverters ad motor cotrol. These devices retai all of the well established advatages of MOSFETs such as voltage cotrol, fast switchig, ease of parallelig ad temperature stability of electrical parameters. Absolute Maximum Ratigs Parameter VGS = 2V, TC = 25 C Cotiuous Drai Curret 4.4 VGS = 2V, TC = C Cotiuous Drai Curret 9. IDM Pulsed Drai Curret ➀ 58 TO-257AA Features: Sigle Evet Effect (SEE) Hardeed Uits TC = 25 C Max. Power Dissipatio 75 W Liear Deratig Factor.6 W/ C VGS Gate-to-Source Voltage ±2 V EAS Sigle Pulse Avalache Eergy ➁ 5 mj IAR Avalache Curret ➀ A EAR Repetitive Avalache Eergy ➀ mj dv/dt Peak Diode Recovery dv/dt ➂ 6. V/s TJ Operatig Juctio -55 to 5 TSTG Storage Temperature Rage Lead Temperature 3 (.63 i.(.6mm) from case for s) o C Weight 7. (Typical ) g Low RDS(o) Low Total Gate Charge Proto Tolerat Simple Drive Requiremets Ease of Parallelig Hermetically Sealed Ceramic Eyelets Light Weight A For foototes refer to the last page 2/7/

2 Electrical Tj = 25 C (Uless Otherwise Specified) Parameter Mi Typ Max Uits Test Coditios BVDSS Drai-to-Source Breakdow Voltage V VGS = V, ID =.ma BVDSS/ TJ Temperature Coefficiet of Breakdow. V/ C Referece to 25 C, ID =.ma Voltage RDS(o) Static Drai-to-Source O-State.8 VGS = 2V, ID =9.A Ω ➃ Resistace.2 VGS = 2V, ID = 4.4A VGS(th) Gate Threshold Voltage V VDS = VGS, ID =.ma gfs Forward Trascoductace 2.5 S ( ) VDS > 5V, IDS = 9.A ➃ IDSS Zero Gate Voltage Drai Curret 25 VDS= 8V,VGS=V µa 25 VDS = 8V, VGS = V, TJ = 25 C IGSS Gate-to-Source Leakage Forward VGS = 2V A IGSS Gate-to-Source Leakage Reverse - VGS = -2V Qg Total Gate Charge 5 VGS =2V, ID =4.4A Qgs Gate-to-Source Charge C VDS = 5V Qgd Gate-to-Drai ( Miller ) Charge 2 td(o) Tur-O Delay Time 35 VDD = 5V, ID =4.4A tr Rise Time 75 VGS =2V, RG = 7.5Ω s td(off) Tur-Off Delay Time 7 tf Fall Time 6 LS + LD Total Iductace 7. H Measured from drai lead (6mm/.25i. from package) to source lead (6mm/.25i. from package) Ω Ciss Iput Capacitace 96 VGS = V, VDS = 25V Coss Output Capacitace 34 pf f =.MHz Crss Reverse Trasfer Capacitace 85 Source-Drai Diode Ratigs ad Characteristics Parameter Mi Typ Max Uits Test Coditios IS Cotiuous Source Curret (Body Diode) 4.4 ISM Pulse Source Curret (Body Diode) ➀ 58 A VSD Diode Forward Voltage.8 V Tj = 25 C, IS = 4.4A, VGS = V ➃ trr Reverse Recovery Time 275 S Tj = 25 C, IF = 4.4A, di/dt A/µs QRR Reverse Recovery Charge 2.5 µc VDD 5V ➃ to Forward Tur-O Time Itrisic tur-o time is egligible. Tur-o speed is substatially cotrolled by LS + LD. Thermal Resistace Parameter Mi Typ Max Uits Test Coditios RthJC Juctio-to-Case.67 C/W RthJA Juctio-to-Ambiet 8 Typical socket mout Note: Correspodig Spice ad Saber models are available o the G&S Website. For foototes refer to the last page 2

3 Radiatio Characteristics Iteratioal Rectifier Radiatio Hardeed MOSFETs are tested to verify their radiatio hardess capability. The hardess assurace program at Iteratioal Rectifier is comprised of two radiatio eviromets. Every maufacturig lot is tested for total ioizig dose (per otes 5 ad 6) usig the TO-3 package. Both pre- ad post-irradiatio performace are tested ad specified usig the same drive circuitry ad test coditios i order to provide a direct compariso. Table. Electrical Tj = 25 C, Post Total Dose Irradiatio ➄➅ Parameter K Rads(Si) 3 - K Rads (Si) 2 Uits Test Coditios Mi Max Mi Max BV DSS Drai-to-Source Breakdow Voltage V V GS = V, I D =.ma VGS(th) Gate Threshold Voltage VGS = V DS, I D =.ma I GSS Gate-to-Source Leakage Forward A V GS = 2V I GSS Gate-to-Source Leakage Reverse - - V GS = -2 V I DSS Zero Gate Voltage Drai Curret µa V DS =8V, V GS =V R DS(o) Static Drai-to-Source ➃.8.24 Ω VGS = 2V, I D =9.A O-State Resistace (TO-3) R DS(o) Static Drai-to-Source ➃.8.24 Ω VGS = 2V, I D =9.A O-State Resistace (TO-257AA) V SD Diode Forward Voltage ➃.8.8 V V GS = V, IS = 4.4A. Part umber IRHY73, (JANSR2N738) 2. Part umbers IRHY33, IRHY43 ad IRHY83 (JANSF2N738, JANSG2N738 ad JANSH2N738) Iteratioal Rectifier radiatio hardeed MOSFETs have bee characterized i heavy io eviromet for Sigle Evet Effects (SEE). Sigle Evet Effects characterizatio is illustrated i Fig. a ad Table 2. Table 2. Sigle Evet Effect Safe Operatig Area Io LET MeV/(mg/cm²)) Eergy (MeV) Rage VGS=-5V Cu Br VDS VGS Cu Br For foototes refer to the last page Fig a. Sigle Evet Effect, Safe Operatig Area 3

4 I D, Drai-to-Source Curret (A) VGS TOP 5V 2V V 9.V 8.V 7.V 6.V BOTTOM 5.V 5.V I D, Drai-to-Source Curret (A) VGS TOP 5V 2V V 9.V 8.V 7.V 6.V BOTTOM 5.V 5.V 2µs PULSE WIDTH T J = 25 C.. V DS, Drai-to-Source Voltage (V) 2µs PULSE WIDTH T J = 5 C.. V DS, Drai-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drai-to-Source Curret (A) T J = 25 C T J = 5 C V DS = 5V 2µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(o), Drai-to-Source O Resistace (Normalized) 2.5 I D = 4.4A V GS = V T J, Juctio Temperature( C) Fig 3. Typical Trasfer Characteristics Fig 4. Normalized O-Resistace Vs. Temperature 4

5 C, Capacitace (pf) 2 VGS = V, f = MHz Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd 5 C iss 5 C oss C rss V DS, Drai-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) I = D 4 A V DS = 8V V DS = 5V V DS = 2V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (C) Fig 5. Typical Capacitace Vs. Drai-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drai Curret (A) T J = 5 C T J = 25 C V GS = V V SD,Source-to-Drai Voltage (V) I D, Drai Curret (A) OPERATION IN THIS AREA LIMITED BY R DS(o) us ms TC = 25 C ms TJ = 5 C Sigle Pulse V DS, Drai-to-Source Voltage (V) Fig 7. Typical Source-Drai Diode Forward Voltage Fig 8. Maximum Safe Operatig Area 5

6 5 V DS R D I D, Drai Curret (A) Figa. Switchig Time Test Circuit V DS 9% R G V GS V GS Pulse Width µs Duty Factor. % D.U.T. + - V DD T C, Case Temperature ( C) Fig 9. Maximum Drai Curret Vs. Case Temperature % V GS t d(o) t r t d(off) t f Fig b. Switchig Time Waveforms Thermal Respose (Z thjc ). D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc + TC t, Rectagular Pulse Duratio (sec) PDM t t2 Fig. Maximum Effective Trasiet Thermal Impedace, Juctio-to-Case 6

7 R G V DS 2V V GS tp I AS Fig 2a. Uclamped Iductive Test Circuit tp L D.U.T.Ω 5V DRIVER V (BR)DSS + - V DD A E AS, Sigle Pulse Avalache Eergy (mj) I D TOP 6.4A 9.A BOTTOM 4A Startig T, Juctio Temperature( J C) Fig 2c. Maximum Avalache Eergy Vs. Drai Curret I AS Fig 2b. Uclamped Iductive Waveforms Curret Regulator Same Type as D.U.T. 5KΩ Q G 2V.2µF.3µF 2 V Q GS Q GD D.U.T. + V - DS V G V GS 3mA Charge I G I D Curret Samplig Resistors Fig3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 7

8 Foot Notes: ➀ ➁ ➂ Repetitive Ratig; Pulse width limited by maximum juctio temperature. VDD = 25V, startig TJ = 25 C, L=.45mH Peak IL = 4.4A, VGS =2V ISD 4.4A, di/dt 395A/µs, VDD V, TJ 5 C ➃ Pulse width 3 µs; Duty Cycle 2% ➄ Total Dose Irradiatio with VGS Bias. 2 volt VGS applied ad VDS = durig irradiatio per MIL-STD-75, method 9, coditio A. ➅ Total Dose Irradiatio with VDS Bias. 8 volt VDS applied ad VGS = durig irradiatio per MlL-STD-75, method 9, coditio A. Case Outlie ad Dimesios TO-257AA.66 [.42].42 [.4] A 3X Ø 3.8 [.5] 3.56 [.4] 5.8 [.2] 4.83 [.9].3 [.5].4 [.45].89 [.35] 3.63 [.537] 3.39 [.527] 6.89 [.665] 6.39 [.645].92 [.43].42 [.4] B 2 3 C 5.88 [.625] 2.7 [.5].7 [.28] MAX [.] 2X 3X Ø.88 [.35].64 [.25] Ø.5 [.2] C A B 3.5 [.2] NOT ES:. DIMENSIONING & TOLERANCING PER ANS I Y4.5M CONTROLLING DIMENSION: INCH. 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE TO-257AA. PIN AS S IGNMENTS = DRAIN 2 = SOURCE 3 = GATE IR WORLD HEADQUARTERS: 233 Kasas St., El Segudo, Califoria 9245, USA Tel: (3) TAC Fax: (3) Visit us at for sales cotact iformatio. Data ad specificatios subject to chage without otice. 2/ 8