EXPERIMENT 3 TRANSISTORS AMPLIFIERS

Transcription

1 PH-315 XPRIMNT 3 TRANSISTORS AMPLIFIRS A. La Rosa I. PURPOS To familiarize with the characteristics of trasistors, how to roerly imlemet its D bias, ad illustrate its alicatio as small sigal amlifiers. The biolar juctio trasistor as well as the field effect trasistor will be cosidered. II. THORTIAL ONSIDRATIONS II.1 iolar Juctio Trasistor Trasistor modeled as a curret amlifier base collector emitter base collector emitter Trasistor is a 3-termial device: emitter, base, collector. They are available i two flavors: ad Diode model: A iitial uderstadig of the trasistor ca be obtaied cosiderig the baseemitter ad the base-collector as diodes. V 2 > V 1 V 2 - V 2 V 1 0 Volts 0 Volts +V 1 I that cotext, let s aalyze i more detail the trasistor. osider first the emitter-base diode. e - eergy Forward bias e - I I I o ev / kt ( e 1) Fig. 1 Left: ergy bad diagram of the (base-emitter) juctio uder equilibrium (a barrier exist for the electros to cross from the -regio to the -regio) ad uder forward bias (the V e -

2 barrier is lowered ad a bias curret is established.) eter: The forward bias curret deeds critically o the base-emitter voltage. Right: Whe the base is lightly doed base the et bias curret is maily costituted by electros (majority carriers) from the -doed emitter. The regio is made lightly doed, thus the forward curret is costituted maily by electros (majority carriers) from the -doed emitter. The regio is also made very thi (~ 0.5 m) so that few arrivig electros are lost by recombiatio with the host holes at the base. The arrivig electros imlicitly become miority carriers i the host - regio; subsequetly they move to the collector by V 1 e - e - diffusio. (The fiite time take by the miority carriers to cross the base limits the highfrequecy resose of the trasistor.) The base-collector diode. Sice V 2 > V 1, the latter beig of the order of 0.7 V, this diode is reversed biased. Thus, the role of the V voltage is just to swee the charges that, after arrivig from the emitter to the base, diffuse to the collector. For this reaso, it is foud that the collector curret varies very little with the collector voltage. e - V 2 V 2 V 1 Fig. 2 Left: Ijectio of majority carriers from the emitter. A relatively small umbers reaches the base but most are swet towards the collector. Right: quivalet icture of the left diagram, but i terms of the more formal currets. I I I Whe the trasistor is roerly electrically biased, the et result is: I is roughly roortioal to I I = I (1) The so called curret gai is tyically about 100. ( is ot a good trasistor arameter; its value ca vary from 50 to 250. It also deeds o the collector curret, collector-to-emitter voltage, ad temerature.) This reresets the usefuless of the trasistor. A small curret ito the base cotrols a much larger curret flowig ito the collector. That is, the trasistor is a curret amlifier. II.2 Field ffect Trasistor ( FT ) A field effect trasistor is a three-termial device i which the curret through two termials is cotrolled at the third (similar to the biolar juctio trasistor.) Field effect devices are cotrolled by a voltage at the third termial (rather tha by a curret like i the JT.) 2

3 FT is a uiolar device; that is, the curret ivolves oly majority carriers. The field effect trasistors come i differet forms: Juctio FT (JFT) based o cotrollig the deletio width of reversed-biased - juctios. Metal-semicoductor FT (MSFT) results whe the - juctio is relaced by a Schottky barrier (i.e. a metal-semicoductor juctio.) Whe the metal is searated from the semicoductor by a isulator, a MISFT results. Whe a oxide layer is used as the isulator the device is called a MOSFT. The various tyes of FT are characterized by high iut imedace, sice the cotrol voltage is alied to a reversed-biased juctio, or Schottky barrier, or across a isulator. FTs are well suited for cotrollig the switch betwee a coductig state ad a ocoductig state. That is, they fit very well i digital circuits. I fact MOS trasistors are used i semicoductor memory devices. II.2.1 Juctio Field ffect Trasistor A -chael JFT has three termials: gai (G), drai (D) ad source (S). The iut sigal is the voltage alied betwee the gate ad source. The outut sigal is the curret from drai to source (e - from source to drai.) D Drai Deletio regio V D + G Gate G e - - Gate V G hael V G - Iut voltage S Source Fig. 3 Left: Termials i a FT. Right: For roer oeratio the (gate-chael) juctio must be reversed biased, so that a deletio regio is formed as show. The drai is oerated at a ositive voltage relative to the source, hece the gate-drai ed is more strogly reversed biased (thicker deletio layer ad thier chael) tha the gate-source ed (thier deletio layer ad thicker chael.) The deletio regio acts as a ocoductor; the remaider of the chael acts as a resistor with eculiar roerties. S 3

4 Iut characteristics. ecause the gate-chael juctio is reversed biased, very little curret flows ito the gate. osequetly, the iut imedace of the device is extremely high, u to 10 12, ad very little eergy is required to cotrol de device. The gate cotrols the curret i the chael through a electric field that affects the deletio regio. Outut characteristics. Let s aalyze the circuit for a give fixed value of the iut voltage V GS.(gate-source voltage.) For V GS = 0 V: For small drai-source voltage V DS, the curret icreases as for a resistor (ohmic regio.) As V DS icreases, the curret begis to level off because the chael arrows at the drai ed (see Fig.3.) At a V DS = -V P (V P is called the ichoff voltage) the coductig chael reaches a miimum size. The curret remais costat uo further icreases of the V DS. This is the saturatio regio. (The electros i the chael are free to move out of the chael ad the through the deletio regio attracted by the V DS voltage. The deletio regio is free of carriers ad has a resistace similar to silico. However, a icrease of V DS (which would ted to icrease the chael curret) will also icrease the distace from drai to the ich-off oit thus icreasig the chael resistace. As a result, these two treds comesate as to kee the chael curret costat.) 1 I the saturatio regio (although it would be better to call it the active regio ) the drai curret is cotrolled totally by the iut sigal V GS i G 0 G 2k D S i D +10V I D 40 ma 30 ma 20 ma 10 ma Ohmic regio Saturatio regio V GS = 0V V GS = - 1V V GS = - 2V V GS (V) V DS, drai-source voltage V GS = V P = 4V Fig. 4 Outut characteristics of a JFT. A ich-off votage equal to -4 volts has bee assumed. For lower (egative) values of V GS, the voltage V DS at which ichoff occurs decreases. The maximum curret also decreases. For V GS < V P : The FT is cut off; o curret flows regardless of V DS. The blockage of curret occurs for the same reaso (the growth of the deletio regio due to the reversed bias). 4

5 Fig. 5 Source: htt:// III. XPRIMNTAL ONSIDRATIONS III.1 The iolar Juctio Trasistor III.1.1 Trasistor s characteristic curves. urret gai ad the value III.1.2 D bias circuit ad the oeratig oit III.1.3 Small sigal amlifier III.2 The Field ffect Trasistor III.1.1 Trasistor s characteristic curves. urret gai ad the value We will use geeral urose trasistors: 2N 2222, 2N 3906, or the 2N Use a trasistor ad setu the circuit idicated i the figure below. Select R ad R such that I fall i the rage of ma, ad I i the order of 5A to 200 A. The suggested use of variable resistors is for you to be able to do the roer chages as to kee the I costat while obtaiig the trace of oe of the curret collector curves. 5

6 I A V (+ 15 V) I (ma) R Active regio V i I A (+15V ) Ammeter R V I 3 (A) I 2 (A) I 1 (A) V Fig. 5 Grouded-emitter setu for obtaiig the collector curret characteristics. I is aroximately costat across the active regio. TASK: stimate the exerimetal value of the trasistor curret gai i. (2) i Kee i mid that usually the curret gai is described i terms of the value of the trasistor, the latter beig defied as, i i 1 i i i III.1. 2 D bias circuit ad the oeratig oit Give the trasistor curves characteristics, our objective is to bias the trasistor roerly as to make it fuctio aroud a give oeratig oit iside the active regio (oit P i the diagram below, for examle.) The rocedure will hel us uderstad how the outut voltage deeds o the iut voltage. I Active regio V (+ 15 V) 20 ma 10 ma P V 100 A 50 A V i (+ 15 V) Fig. 6 Give the collector curret characteristics. R ad R should be selected to have the trasistor oeratig aroud the oit P i the active regio. I R I R V How to choose R? Load lie aalysis 6

7 I 15V R 20 ma 10 ma P 100 A 50 A ve though we do ot kow I either V a relatioshi betwee them ca be obtaied through the Kirchhoff s law alied to the right side brach of the circuit above (ad reroduced below for coveiece.); 15V - I R - V = 0, which leads to, V + 15 V Fig. 8 Load lie suerimosed with the trasistor characteristic curves. 15V 1 R R decreases liearly with V.) I V (I I I + 15 V R I V + 15 V 15V R 20 ma 10 ma Load lie + 15 V Fig. 7 Alicatio of the Kirchhoff law to the right-side brach of the circuit gives a relatioshis to be satisfied by I ad V. V If we wat to work with, for examle, a curret base of 50, may values of Rc are ossible. Still, there is a restrictio to be satisfied, which is ot to exceed the trasistor s heat dissiatio tolerace. For examle, the data sheet may secify, V ; max I ; max < 350 mwatts Alyig this coditio to our case, oe obtais (15 V) ( 15 V/R ) < 350 mwatts Thus, i this case, a resistor R > 1 K would be good eough How to choose R? Sice we wat to oerate the trasistor at the oit P, that is a curret base of 50 A, all we have to do is to choose a R that allows deliverig a curret of that magitude 15V 0.7V R ~ 50 A which takes ito accout that, whe oeratig i the active regio, the base voltage is about 0.7 V (for silico trasistors.) The oeratig oit P results the from the itersectio of the load lie ad the trasistor curve 7

8 corresodig to 50 A. How the outut voltage deeds o the iut voltage Istead of usig a fixed V i voltage, vary its value a bit as to roduce slightly differet base currets. The diagram below hels illustrate the exected variatio of the V voltage. V i I R I V (+ 15 V) R V I I 15V R 20 ma P V I + 15 V 100 A I =50 A Fig. 9 Small variatios of I moves the oeratig oit P alog the load lie, causig a variatio of V (ad, corresodigly, a variatio i I.) V TASKS: Make a lot of vs V i (Notice, i this case, = V ) Verify that the lot looks like the grah show i the figure at the right. From this exerimetally obtaied grah, evaluate the voltage gai: / V i V Trasistor OFF Trasistor (saturated) ON Fig. 10 The greater V i, the greater I, the greater I ad greater dro of voltage across R, the lower V voltage. V i NOT: Notice from figures 9 ad 10, that the greater V i, the greater I, the greater I ad greater dro of voltage across R, the lower V (outut voltage.) Thus, small variatios of the iut voltage aroud a give value will be 180 o out of hase with the outut voltage. III.1.3 Small sigal amlifier A large sigal amlifier oerates the trasistor i its full rage of oeratio, from ear cutoff to ear saturatio (from small I currets to large currets). Such a oeratio mode is quite 8

9 suitable for digital electroics alicatio, where LOW ad HIGH sigal levels determie the 0 ad 1 biary iformatio. Other alicatios require small-sigal amlifiers. For a give cofiguratio, where the trasistor oerates at a give oit of the active regio, a small modulatio of the base-curret traslate ito a modulatio of the collector curret (icture a small audio sigal beig amlified by the trasistor). If high amlificatios are required, several small-sigal amlifiers ca be cascaded i series. I this laboratory sessio we will costruct ad aalyze just oe small-sigal amlifier stage. A small-sigal amlifiers must have: a dc bias circuit for lacig the trasistor i its amlifyig regio (VRY IMPORTANT). a mea for itroducig the iut sigal a mea for sulyig its outut sigal to the ext stage. The circuits used i the revious sectio deal with the first two asects. ut, as it turs out, such circuits are very sesitive to temerature variatio. For that reaso, we will be modify it a bit, but their equivalece with our older circuit will become trasaret i the course of the discussio. Oce the circuit is roerly D biased, we will roceed to iut a small A sigal. (The coulig of a circuit stage to aother will be addressed i Lab #4, whe we study the cocet of iut ad outut imedace). III.1.3.A Modified D-bias ircuit. Placig the trasistor i its amlifyig regio. The simle bias circuit i Fig. 9 above is geerally ot satisfactory because the oeratig oit shifts drastically with temerature.) A more satisfactory trasistor bias is obtaied whe usig a voltage divider, as show i Fig. 11. TASK: ostruct the circuit show i Fig. 11. Thevei equivalet circuit aalysis We ca use the Thevei s theorem to show the equivalece betwee the circuits i Fig. 9 ad Fig. 11. This is made more evidet by re-drawig Fig. 11 as show i Fig. 12 below. Through the Thevei theorem oe ca claim that both circuits, the oes at the left ad right sides of Fig.12 are equivalet. Aalyzig the shaded area oe obtais: The Thevei voltage V is the oe-circuit voltage (voltage across XY i the circuit whe o exteral load is alied) V =1V.) V R R 1 2 R 1. (V = (10V/55k)(5k) R 2 50K R K R desigates the Thevei equivalet series resistace. The short circuit currets (i.e. the currets whe X ad Y are shorted) are V /R 2 ad V /R resectively. Sice the V i R 1 K I V = + 10 V Fig. 11 D bias circuit (accomlished by the resistace R 1 ad R 2 ). 9

10 circuits are equivalet these two curret must be equal. Hece, value for V obtaied above, results R R R R V 2 V ; usig the 2 1 R (R = (5k x 5k) / (55k) =5 k ). R1 R2 V =+10V R 2 50K X R V = +10V R X R 1 K V = +10V R K Y V Y Fig. 12 D bias circuit ad its Thevei equivalet. The latter hels to calculate the differet arameters associated to the iteded oeratig oit of the trasistor (usig the aalysis described i the revious sectio) based o the values of R 1 ad R 2. TASKS: For the fial values that you use for R 1 ad R 2 calculate the Theveig values for V ad R. Select the roer value of R such that the trasistor work i the active regio. THIS IS VRY IMPORTANT. More secifically, choose R such that V is ~ 4 Volts. (A R ~ 1 k should work). V = + 10 V V V = +10V R 2 50K V i R 1 K I R I R I R K Fig. 13 quivalet reresetatio of the circuits i Fig. 12. III.1.3. oectig to a oscillator Oce the trasistor is roerly D biased (V ~ 4 volts), roceed to coect the voltage from a sigal geerator. See Figure 14. If the oscillator is coected directly at the V i, uwated D voltage offset from the oscillator may chage the bias level ad/or draw some curret away from I b., ad thus otetially soil the oeratio oit desiged i the revious sectio. As a 10

11 recautio, it is ormally coveiet to ut a caacitor i series with the oscillator to block the flow of D curret. (You could try 1 =1f but be aware of the frequecy rage of oeratio. Sice the imedace of the caacitor is frequecy deedet, make sure the caacitive reactace is small with resect to the other resistace you use at the iut; i.e. you eed a resistace to limit the base curret). TASK: oule a small siusoidal sigal (start usig ~0.03 V amlitude) ito the circuit show i Fig. 14 (Left diagram). Moitor the iut ad outut sigals i the oscilloscoe. It is coveiet to first moitor the outut voltage v out with the oscilloscoe set to D mode, so you ca be track whether its value is saturate or ot. Measure the A voltage amlificatio, as well as the relative hase betwee the iut ad outut voltage. (For this measuremet, you may wat to switch moitorig the outut voltage with the oscilloscoe i ac-mode). For the coulig caacitace 1 that you choose ( 1 = 1 F for examle) fid out the rage of frequecies for which the circuit works roerly. Fid out also the rage of iut-voltages amlitude tolerated by the circuit. Make the circuit to work i the low frequecy (tes of hertz) ad high frequecy rage (tes of khz or higher). You may eed a differet caacitor for each of these two cases. Notice: Your circuit may ot allow uttig a ac-sigal iut sigal v i of amlitude greater tha ~0.3 V (actually the exact value deeds o the value you select for R s ), otherwise you would drive the trasistor out of its oeratio rage (this will be reflected i the cliig of the outut sigal). V = + 10 V V = +10V R R 2 1 K V 50K I v i R s 1 R K v out v i R s i R 1 I R I v out Try R s = 1 Kork Fig. 14 Left: Small sigal amlifier circuit. Right: quivalet circuit, which hels to differetiate the additioal (A) base curret ijected by the sigal geerator from the D base curret established by the bias circuit. 11

12 valuate the maximum amlitude of the iut ac-sigal that your circuit tolerates (i.e. avoidig cliig i the outut sigal). heck whether a Rs= 1 k or Rs= 10 k works better i this regard. Moitor the voltage V at the base of the trasistor all the time (with a multi-meter or, better, with the oscilloscoe); the value should be ~ 0.7 volts. Wheever you observe the outut sigal cliig it may be because V is deviatig very much from this value (If V is too high the trasistor lead to saturatio; if V is too low the trasistor is off). vetually, you may eed to chage the value of R to have the voltage v out i the roer rage (i.e. v out has to be greater tha 0.7 volt, so it ca allow ac variatio without turig off the trasistor.) It is coveiet to first moitor the outut voltage v out without the caacitor, so it ca be tracked whether its value is saturate or ot. For that urose moitor v out with the oscilloscoe set to D mode. After you fid your circuit workig roerly, isert the caacitor 2 (Fig. 15). V = + 10 V V = +10V v i R s 1 R 2 50K R K R 1 K I 2 v out v i R s V R i 1 I R I 2 v out Try R s = 1 Kork Fig. 15 ircuit is exactly the same i Fig. 14, excet usig a out coulig caacitor. III.2 The Field ffect Trasistor We will use the FT 2N 2N5457 Imlemet the FT i the circuit outlied i Fig.4. Determie the characteristics curves, as well as the ichoff voltage V P. RFRNS J. R. ogdell, "Foudatios of lectroics," Pretice Hall (1999). See Sectios 2.3 ad 2.4, P. Horowitz ad W. Hill, "The Art of lectroics," 2d ditio, ambridge Uiversity Press 12

13 (1990). e G. Streetma, Solid State Devices, 3 rd. d. Pretice Hall. (hater 8, Field ffect Trasistor). 1 htt://e.wikiedia.org/wiki/field-effect_trasistor ve though the coductive chael formed by gate-to-source voltage o loger coects source to drai durig saturatio mode, carriers are ot blocked from flowig. osiderig agai a -chael device, a deletio regio exists i the -tye body, surroudig the coductive chael ad drai ad source regios. The electros which comrise the chael are free to move out of the chael through the deletio regio if attracted to the drai by drai-to-source voltage. The deletio regio is free of carriers ad has a resistace similar to silico. Ay icrease of the drai-to-source voltage will icrease the distace from drai to the ich-off oit, icreasig resistace due to the deletio regio roortioally to the alied drai-to-source voltage. This roortioal chage causes the drai-to-source curret to remai relatively fixed ideedet of chages to the drai-to-source voltage ad quite ulike the liear mode oeratio. Thus i saturatio mode, the FT behaves as a costat-curret source rather tha as a resistor ad ca be used most effectively as a voltage amlifier. I this case, the gate-to-source voltage determies the level of costat curret through the chael. 13