4 Interactions of the Integrated System

Transcription

1 4 Iteractios of the Itegrated System The dyamic behavior of a system ca be rereseted mathematically by state sace equatios,. Xi = AiXi + BiUi. Whe may such systems are coected to the dc bus, the order of the distributio system equatio is chaged. The system characteristic matrix A ad equatio chage accordigly, as do the eigevalues of the system. If a eigevalue moves towards the right-half lae, the system becomes oscillatory ad the iteractios occour. It is ossible to study a simle system with a few state variables i a low-order system, for a large scale distributed system, however, the system order is huge. It chages costatly because of the load chage ad ew system lug-is at ay time. Furthermore, there are systems for which the characteristics are ukow ad which sometime may be hard to describe with state sace equatios. There are two basic methods used to study the behavior of large-scale systems. Oe is to secify the iut ad outut characteristics of each box before coectio. The other is to establish the roer circuit models ad simulate the system uder various oeratio coditios. The two methods ca be used simultaeously oto a system for differet uroses. May iteractios which hae o a simle system are redictable; the system level iteractios, however, are ot as trasaret as it might aear. Usig the models develoed i the revious chater, this chater illustrates some of the system-level iteractios o the distributed ower system. They are: (1) the zero-axis circulatio curret i aralleled three-hases caused by the iterleaved discotiuous SVM, (2) the iteractios betwee load iverter ad source PFC rectifiers caused by the ubalaced load ad small sigal imedace overla, ad (3) the high frequecy commo mode oise related to SVM modulatios. The iteractios, system desig cosideratios, ad exerimets are carried out o the PEBB-based ower system test-bed. 80

2 4.1 PEBB-Based Power System Test Bed The PEBB-based ower system test bed has a three-hase boost PFC rectifier, a dc distributio bus, ad iverter loads. The testbed was costructed accordig the PEBB cocet. It demostrates the modularized system structures ad iterface. It ca be cofigured differetly to study the system-level iteractios betwee PEBB systems. Figure 4.1 (b) shows oe of the hardware cofiguratios of the testbed system. Most exerimetal results show i this chater were obtaied o this test bed. The iut voltage to the rectifier is three-hase 208 V. The rectifier is rated 20 kva with 400 V dc bus. There are six PEBB modules i the test-bed. Each module uses a IGBT module itegrated with a gate driver, which uses otical fibers for gate ad fault sigal trasmissio i order to elimiate the EMI oise coulig. The six PEBB modules ca be cofigured as a three-hase rectifier ad a iverter, or aralleled rectifiers. The dc termials of the PEBB module are coected to a commo lamiated dc bus. The lamiated bus structure, show i Figure 4.1 (a), has a ositive, a egative, ad a middle lamiates ad a series coected caacitors. A sesor board is laced o to of the PEBB modules. The structure of the sesor board is show i Figure 4.1 (c). It seses the iut three-hase voltage for the sychroizatio of the rectifier. It also seses the three-hase curret ad dc bus voltage for closed loo oeratio. The LEM sesor modules are used for voltage ad curret sesig. The followig are other system secificatios ad the hardware set-u arameters: IGBT module: Toshiba MG150J2YS50 (150 A/600 V); Iut iductor: 256 µh; Outut caacitor: 1200 µf; System switchig frequecy: 32 khz; Heatsik: water cool; Cotroller: Aalog Device ADSP2101; Because the system was built usig the modularized cocet, the system iterface is imortat, which is illustrated i Figure 4.2. Three PEBB modules icludig the gate driver ad the sesor board are defied as the ower stage block. The DSP cotroller ad the iterface board are defied as the cotroller block. The sigals betwee the two blocks are sesor, gate cotrol, ad fault sigals. The ower stage block accets a sigle ower suly for the iteral 81

3 gate driver. This block also iterfaces with the dc bus ad three-hase load/source through the ower termial ad the heat sik through the mechaical coectio. The block diagram of the cotroller block ad iterface is show i Figure 4.2 (b). The sesor sigals origiatig from the ower stage block are set to the A/D coverter. The DSP calculates the duty cycles every switchig cycle, which is iitiated by the iterrut sigal from the Altera. At each iterrut sigal, the Altera loads with the switchig state ad timig from DSP. The duty cycles are geerated by the Altera ad set to a buffer. The dead-time for the high ad low side IGBT is added after the buffer. The buffer ca be disabled by a over curret sigal. The over curret sigal also is set to the DSP to shut dow the rogram ad issue the fault sigal. 4.2 Iteractios betwee PFC Coverters Backgroud I the dc distributed ower system (DPS) with a very strict requiremet of redudacy, the dc bus ca be fed by multi-geerators. The three-hase rectifiers, as the frot-ed, ca be aralleled o either searate sources [D11] or the same source. Parallel ower coverters offers may advatages, such as higher curret caability, less curret/voltage rile, ad higher system badwidth. Previous research o arallel three-hase systems ca be foud i alicatios of UPS, motor drive ad ower factor imrovemets [D1-6]. However, uttig modules i arallel is ot risk free. Oe of the major cocers for arallel oeratio of threehase systems is the cross-curret betwee modules. Traditioally, i order to avoid this roblem, trasformers are used to isolate the direct curret flow as show i Figure 4.3 (a). Those trasformers are desiged with a certai widig turs-ratio ad a certai hase-shift, so that the cocered harmoics ca be caceled i the other side [D3,D7]. But the trasformer is heavy ad bulky for the iverters/coverters with low modulatio frequecy, esecially for a high ower alicatio. Therefore, a direct coectio betwee the ower coverter module ad ower system is desirable. Figure 4.3 (b) shows aralleled coverters with a iterleaved PWM direct coectio, which is the focus of this discussio. 82

4 Positive Negative Gate Driver Middle (a) (b) 3 Φ Curret DC Bus Voltage 3 Φ Voltage LEM I-Sesor Isolatio V-Sesor AC AC To DSP Iterface (c) Figure 4.1 The 400 V dc bus system test-bed, (a) itegrated PEBB module ad lamiated bus structure, (b) ower stage block hardware setu, ad (c) the structure of the sesor board 83

5 Sesor Sesor board Sesor Sigal To Lamiated Bus Driver (a) Gate & Fault Sigal Power Suly for Drivers Gate Sigal Ot- Fiber Trasmitter Dead Time Outut Buffer Digital Sigal Processor Fault Sigal Ot- Fiber Receiver Disable Over Curret Detectio Altera Sesor Sigal Iut Buffer A/D D/A DSP Iterface (b) (c) Figure 4.2 System iterface (a) the ower stage block, (b) the cotroller block, ad (c) hardware of the cotroller 84

6 The literature reorted three ways to reduce the cross-curret. The first way is to isert a curret sharig reactors ito the aralleled modules [D1,D5,D6,D12]. The couled iductors are o the ac side for the VSI or the dc side for the CSI. The secod way is to use the bag-bag hysteresis cotrol [D3], which cofies the curret withi a bad by varyig the switchig frequecy. The third way is to use a combied-mode curret cotrol [D6], which treats the aralleled system as oe system. The cross-curret is comesated by choosig roer voltage vectors through sesig the outut curret ad their derivatives. Ulike the existig literature, this research assumes each PEBB system module is ackaged with three PEBB modules ad a certai degree of itelligece, icludig the PWM modulatio ad the curret loo cotroller. A motherboard is used for the system, which has a switchig iterleave clock ad a curret loo referece sigal for all aralleled systems. Also, there are o other commuicatios betwee them; ad they are exected to lug ad lay. The sace vector modulatio techique, ot the SPWM, is used as the ulse width modulatio [D14] Aalysis of the Circulatig Curret System Cofiguratio The system block diagram is show i Figure 4.4. It cosists of two three-hase modules. Each oe is comosed of three PEBB modules, three iut boost iductors, ad a curret loo cotroller. The curret cotroller has the followig fuctios itegrated: (1) lie voltage ad curret sesig ad sychroizatio, (2) curret loo comesator, ad (3) sace vector modulatio. The two modules are coected to a three-hase ower suly at the ac side ad a commo dc bus at the dc side. Both modules accet two sigals from the outside motherboard: (1) a SVM iterleave sigal (180 degree), ad (2) a curret loo referece comig from the voltage comesator. A 180-degree hase shifted PWM is used i order to reduce the total iut curret rile. The commo voltage loo rovides the same curret loo referece to the ier roortioalitegral (PI) cotroller, which will track the give referece ad esure load curret sharig. I order to reduce the switchig loss, a SVM with 60-degree clamig is used, which will be discussed i detail later. Although each module ca be oerated roerly as a stad-aloe system, the iteractio occurs whe they are i arallel. Figure 4.5 shows the simulated iut 85

7 curret waveform of the two modules with 20 khz switchig frequecy ad 60 Hz lie frequecy. As ca be see from the waveform, the iut curret has a bias comoet with a 20 Hz beat-frequecy. It makes the three-hase curret deviate from the zero-lie alteratively. The bias curret tras the eergy iside the coverter ad causes extra switchig ad coductio losses The Cross-Curret Caused by Iterleaved Discotiuous SVM There are may SVM schemes for three-hase PWM coverters. The SVM with 60-degree clamig is most favorable for PFC oeratio, because the hases carryig the highest curret i each 60 degrees of lie cycle do ot switch. Calculatios show that a 50% switchig loss reductio ad a very good THD are achievable with this SVM [D13]. To illustrate the ricile, Sa, Sb, ad Sc are assumed to be the cotrol sigals for the to switches of a three-hase coverter. Whe the referece vector is i sector I, where the hase A voltage (ad the curret for PFC oeratio) becomes the maximum comared to the other two hases, the to switch of hase A will kee i coductio ad the hases B ad C will do the modulatio, as show i Figure 3.4. This meas that oly the zero-vector ca be used i this 60-degree eriod of time. Extedig this coclusio to a comlete lie cycle, the distributio of zero-vectors i the hexago ca be obtaied as show i Figure 4.6, where the ad vectors are used alteratively every 60-degrees. The averaged 60-degree clamig SVM is show i Figure It has bee show that there is a discotiuity at each trasitio of 60-degrees. Because of the iterleaved switchig clock, the referece vectors of the aralleled module do ot crossover the discotiuous oit at the same time, which is exaggerated i Figure 4.6 (b) as the shaded area. The module which asses the discotiuous oit first will use a differet zerovector comared to the module behid it. Therefore, zero vectors ca be overlaed. Whe this haes, the to switches of the oe module are coected to the ositive dc rail ad the bottom switches of the other module are coected to the egative dc rail. The three-hase currets will flow simultaeously from the dc bus caacitor through the to switches of oe module, the boost iductors, ad the bottom switches of the other module, back to the dc bus caacitor, as show 86

8 i Figure 4.7. If the overla betwee the zero vectors is t, the dc bus voltage will be alied directly to the boost iductors. It roduces the curret: module1 module1 tras. ge. module2 ge. module2 Figure 4.3 Tyical cofiguratios of PFC o a sigle source, (a) With hase-shifted trasformer, (b) With iterleaved PWM. 87

9 Module 1 Ia1,Ib1,Ic1 Curret Loo Voltage Loo& Switchig Clock (mother board) Curret Loo Ia,Ib,Ic Module 2 Figure 4.4 System block diagram. 88

10 (a) (b) Figure 4.5 Iut curret waveform of the aralleled modules 89

11 i Vdc =, 2L 0 t (4-1) where L is the iductace of the boost iductor. This shoot-through curret charges ad discharges the three-hase iductor simultaeously. Oe module icks u more curret, while the other module dros off a curret of the same magitude. This curret is the ure zero-sequece curret, which does ot show u i d ad q chaels with the trasformatio: i cos( ) 2 i d θ = si( θ) q 3 i 1/ 2 0 cos( θ 2π /3) si( θ 2π /3) 1/ 2 cos( θ + 2π /3) i + i a 0 si( θ + 2π /3) i + i b 0 1/ 2 + i i c 0 (4-2) Therefore, the effect of ad zero-vector overla i aralleled systems excites the ure zero-sequece curret to flow alog the loos formed betwee the aralleled modules. This is what haeed i oe of the discotiuous oits. As time elase, the referece vector will cross over the discotiuous oits at each 60- degree trasitio of the lie cycle. However, the referece vectors do ot ass these oits sychroously i a mootoic leadig or laggig atter. Istead, they are modulated by the lie ad switchig frequecy. Assumig that the duty cycle of the hase A of module 1 is D a1, ad the duty cycle of the hase A of module 2 is D a2, the differece of the duty cycles will be (4-3), as show i Figure 4.8 (a). D a =D a1 -D a2 (4-3) As ca be see, D a is modulated. The differece betwee the hase A curret of the aralleled modules is: i a =i a1 -i a2 (4-4) which is show i Figure 4.8 (b). As idicated by this icture, at each 60-degree trasitio oit, there is a curret jum roduced. This curret jum results from duty cycle differece at the discotiuous oits. 90

12 Module 1 Module 2 (a) (b) Figure 4.6 The duty cycle differece by the iterleaved discotiuous SVM La Lb Lc Module1 i Vdc La Lb Lc Module2 Figure 4.7 The ath of the ure zero sequece curret 91

13 Duty cycle D Differece betwee duty cycles ( D) (a) Curret differece because of D (b) Figure 4.8 Beat-frequecy oscillatio of the zero-sequece curret 92

14 93 It is also iterestig to otice that withi the cotiuous regio of the SVM, the zerosequece curret does ot stay at the revious values. This is because whe the modules are i other combiatios of vectors i the followig switchig cycle, the circulatig curret still exists, but they are differet i differet hases. This actually breaks u the ure zero-sequece curret artly ad traslates a ortio of it ito dq chaels. The dq curret loos will try to correct this art of the curret by trackig the give referece. It is show that withi the 60 degrees, as the zero-sequece curret has ot bee totally corrected, the ext excitatio is roduced agai i the followig trasitio. Therefore, there is the low frequecy comoet o the zero-axis Correlatio betwee the abc Waveform ad dq0 Cotroller The heomeo discussed above is what haeed i the ower stage. The followig examies how this is traslated to the cotroller. Suose there is a commo mode curret ridig o a balaced three-hase curret: c c b b a a i t I i i t I i i t I i + + = + = + = 3) / 2 cos( 3) / 2 cos( ) cos( π ω π ω ω (4-9) ad o o c b a i t I i i i = + = = = ) 3 cos( φ ω (4-10) O the time frame, the distorted curret is draw i Figure 4.10 (a). By erformig the followig trasformatio, ) ( = o o o c b a o i i i T i i i i i i β α (4-11) = T (4-12)

15 The maed currets i the αβ0 frame are show i Figure 4.9 (b). As show i the αβ lae, the d ad q comoets still are rotatig as a circle, but the zero-axis oscillates u ad dow. The cotroller ca oly cotrol two of the three axes, usually d ad q. This is similar to a three-hase system where oly two hases are cotrollable because the sum of the voltage or curret has to be zero. Oce there is such a ure zero-sequece curret ijected ito the system, the cotroller actually ca ot do aythig Mitigatio of the Circulatig Curret Hysteresis Cotrol o Zero-Axis To realize the zero-axis cotrol, a third curret sesor has to be iserted ito the other hase of the module, because the third hase curret caot be derived from the other two hases. With the sesed three-hase curret, the abc/dq0 trasformatio is erformed. The cocet of the zero-axis hysteresis cotrol is as follows. Before alyig the zero vectors, the zero-axis curret is comared with the give limits. If the curret is greater tha the uer limit, which meas that more curret is goig ito this module, the the vector should be used i the successive switchig cycles i order to suress the curret back. If the curret is smaller tha the lower limit, the the vector should be used. If it is iside the widow, SVM should kee the revious zero-vector. As discussed earlier, there are two differet situatios i which the zero-sequece curret is roduced. The first situatio is whe oe module uses a vector ad the other module uses a vector. The secod situatio is whe the two modules use differet vectors, but ot the combiatio of ad. However, the hysteresis cotrol ca ot differetiate betwee these two situatios. Wheever it detects that the three-hase curret does ot add u to zero, it will assume that this curret results from usig ad vectors, ad it will use these two vectors to correct it. Aaretly, the cotrol caot be accurate. Therefore, i the simulatio, the vector is more frequetly used comared to the vector. Wheever the vector is used, the equivalet circuit of the rectifier becomes a three-hase source which feeds three iductors, ad the curret will freewheel through the bottom switches. The frequet use of a vector meas more switchig ad coductio loss of the bottom switches of the module. 94

16 i o (a) 0 D 0 α α 0 Plae Q β D (b) α β Plae Figure 4.9 Correlatio betwee time domai waveforms ad dq coordiates (a) The zero-sequece curret i time frame, (b) Three-dimesioal view o the rotatig frame 95

17 Sa1 Sa2 Sb1 Sb2 Sc1 Sc2 (a) ia1 ib1 ic1 ia2 ib2 ic2 Figure 4.10 Hysteresis zero axis cotrol oeratio waveform, (a) The gate sigals of the to switches of (b) the aralleled module, (b) The three-hase iut curret of the aralleled module 96

18 The simulatio waveforms are show i Figure As ca be see from Figure 4.10 (a), which lots the gate sigals of the to switches of the aralleled module, the bottom switches are used more frequetly tha the to switches. The three-hase iut curret also is affected by the biased use of the switches. The ositive curret has more curret riles tha the egative arts, as show i Figure 4.10 (b). Therefore, this cotrol strategy is ot satisfactory The SVM without Usig Zero Vectors As we have oted earlier, the zero-sequece curret roduced at the discotiuous oits does ot hold at the same value i the followig 60-degree trasitio but teds to retur to zero, which is seemigly i cotradictio with the statemet that the dq chael caot reject the zero axis curret. Actually, it is the curret loos that are doig their jobs. Assume both referece vectors are i sector I, where the,, ad vectors are used. Withi a switchig cycle, there will be some time itervals whe the two modules use differet vectors, which meas that there exists at least oe hase to circulate the curret. This actually breaks u the existig ure zero-sequece curret ad traslates a ortio of them ito d ad q axes, where the d ad q axes cotrollers ca see them. O the other had, the curret circulatio will ot sto as log as the modules are ot i the same vector. Therefore, it is imossible to make the sum of the threehase curret be zero at the switchig frequecy. The goal is to cotrol its average value, so that it does ot accumulate. Theoretically, the ad vectors ca be slit aart ad arraged aroriately i oe switchig cycle so that the overla would be miimized or elimiated. However, ucertaities still exist i system trasiets ad sector trasitio, where the trasitio chatterig is likely to occur because of the curret rile. Oce the overla is created, the zero-sequece will exist at least oe switchig cycle before it ca be corrected. Because the zero-axis curret loo caot be so fast as to elimiate the switchig frequecy curret. Based o these observatios, SVMs that do ot use zero-vectors are roosed for iterleaved PWM rectifiers. Figure 4.11 (a) shows oe of these schemes. The basic idea is to divide the zero-vectors duty cycle ito four equal time eriods ad rearrage the duty cycles as follows: d0 =do/2 97

19 d1 =d1+d0/4 (4-13) d2 =d2+d0/4 I the d0 eriod, the oosite vectors are used to sythesize the referece vector, as show i Figure 4.11 (a). By usig this scheme, the zero-sequece curret is cut off by two factors: (1) there is o mechaism of roducig the ure zero-sequece curret by ad vectors, ad (2) from each module s viewoit, the udesired curret resultig from the other modules ca be treated as the disturbace to its ow cotroller. If the circulatig curret is observable i the dq chael, the strog curret loo will ick it u as a disturbace ad reject it by modifyig the outut duty cycles i the followig switchig cycles. This is a dyamic rocess i which the curret loos cotrol the dq comoets to rotate as a circle. The high badwidth curret loo exists aturally for PFC oeratios, where the cotrolled variables have to track the commad as quickly as ossible. Figure 4.12 (b) shows the simulated waveform of the iut curret of the two modules. The use of this SVM ivolves more switchig actios ad a little higher curret rile. Because the chage of modulatio deth for PFC oeratio is very arrow, the rile cotet is accetable Comarisos of SVMs The followig calculatios take sector I o the hexago as the examle. Other sectors ca be obtaied similarly because of symmetry. The magitude of the sace vectors is give by: Vdc Vector = cos(π / 6) The modulatio idex is defied as (4-14) Vsvm dm =, (4-15) Vector 98

20 B Sa d0/4 A Sb C Sc d0/4 d1 d2 d0/4 (a) (b) Figure 4.11 Parallel oeratio waveform usig the SVM without usig zero-vectors, (a) SVM scheme, (b) three-hase iut curret 99

21 where Vsvm is the desired lie-to-lie voltage: the referece vector legth. Because the imedace of the iductor at lie frequecy is very low, a very small amout of voltage will roduce a sigificat curret caable of sustaiig the dc bus voltage at certai load. Therefore, Vsvm is almost equal to the iut lie-to-lie voltage. At 20 kva ower ratig, by: dm= I each switchig cycle the rojectios of the referece vector oto ad are give d1( θ ) = dm[cos( θ ) si( θ ) d 2( θ ) = dm π cos( ) 6 π si( θ ) ta( )] 6 The zero-vector duratio is obtaied by: (4-16) (4-17) d0( θ ) = 1 d1 d2, (4-18) where θ is the agular ositio of the referece vector with regard to the vector. Figure 4.12 shows the variatio of the d1, d2, ad d0 withi the sector. Divide oe switchig cycle ito four segmets with duty ratio duratio as (d0/2), d1, d2, (d0/2), let k be the idex umber of the segmets, i the vector, the followig equatios ca be obtaied: 20b) t = + k+1 tk Ts DTk (4-19) ia ib Vh L 2 Vdca 1.5L tk = k ia cos( ω t + δ ) dt+ ( t k + 1 k k+ 1 tk k+ 1 t ) k tk + 1 Vh 2 Vdcbk = ibk + cos( ω t 2π /3+ δ) dt+ ( tk+ 1 tk ) (4- L 1.5L t k (4-20a) ic k+ 1 tk + 1 Vh 2 Vdcck = ick + cos( ω t + 2π /3+ δ) dt+ ( tk+ L 1.5L t k 1 t ) k (4-20c) I these exressios; t k : time istat of the segmets; DT k :the duty cycle i each segmet; Vh: the RMS value of the iut hase voltage; 100

22 δ: the hase delay betwee lie voltage ad the modulated voltage, which is very small. d1 d2 d0 Figure 4.12 Duty cycle variatios withi oe sector Degree 101

23 I these equatios, the hase curret has three terms. The first term is the revious istat curret value. The secod term is the cotributio from the iut voltage, ad the third term is the cotributio from the dc bus voltage. I differet segmets withi o switchig cycle, the cotributios from the dc bus voltage to the iductor curret are differet. Therefore, omiators of the last term i equatio (4-20) have differet values i each segmet. For the 60-degree clamig SVM, Vdca, Vdcb, Vdcc are defied i Table 4.1. The hysical meaig of the first row of this table is as follows: For hase A, i the d0/2 eriod, the zero-vector is used, the dc bus voltage does ot cotribute to the iductor curret. I the d1 eriod, the vector is used. P hase A is coected the ositive dc rail, ad hases B ad C are coected to the egative dc rail. Therefore, the hase A iductor curret cotributed by the dc bus voltage is: Vdc ia = ( t k 1 tk ) (4-21) + 1.5L which is the last term i the equatio (4-20a). Similarly, i the d2 time eriod, the vector is used. The hase A iductor curret cotributed by the dc bus voltage is: Vdc / 2 ia = ( t k + 2 tk +1) (4-22) 1.5L I the followig d0/2 eriod, the dc bus voltage does ot cotribute the iductor curret. Similarly, we ca iterret the terms for hase B ad hase C. Tabel 4.1 Defiitio Vdc for the 60 degree-clamig SVM d0/2 D1 d2 d0/2 Vdca 0 -Vdc -Vdc/2 0 Vdcb 0 Vdc/2 -Vdc/2 0 Vdcc 0 Vdc/2 Vdc/2 0 For the roosed SVM, the duty cycles are re-calculated as: d 0( θ ) d1' ( θ ) = d1( θ ) +, 4 d 0( θ ) d 2' ( θ ) = d 2( θ ) +, 4 d 0( θ ) d 0' ( θ ) =. 2 Vdca, Vdcb, Vdcc are defied as Table 4.2 i each segmet: (4-23) 102

24 Da Db Dc Switchig Sigal Number of Commutatios O Off Phase A 0 0 Phase B 1 1 Phase C 1 1 Da Db Dc Switchig Sigal Number of Commutatios O Off Phase A 1 1 Phase B 1 1 Phase C 1 1 A d0/2 d1 d2 d0 d1 d2 d0/2 A d0/4 d1 d2 d0/2 d1 d2 d0/4 ia ia ib ib Rile=8% ic Rile=11% ic (a) Degree (b) Degree Da Db Dc Switchig Sigal Number of Commutatios O Off Phase A 0 0 Phase B 1 1 Phase C 1 1 Da Db Dc Switchig Sigal Number of Commutatios O Off Phase A 1 1 Phase B 1 1 Phase C 1 1 A d0/2 d1 d2 d0 d2 d1 d0/2 ia d0/4 d1 d2 d0/2 d2 d1 d0/4 A ia ib ib Rile=14% ic Rile=19% ic (c) Degree (d) Degree Figure 4.13 The comarisos betwee SVMs i commutatio times ad curret riles: (a) ad (b) asymmetrical 60-degree clamig SVM ad the SVM without usig zero vectors, (c) ad (d) Symmetrical oeratio 103

25 Tabel 4.2 Defiitios Vdc for the roosed SVM d0 /2 d1 d2 d0/2 Vdca Vdc/2 -Vdc -Vdc/2 Vdc Vdcb Vdc/2 Vdc/2 -Vdc/2 -Vdc/2 Vdcc -Vdc/2 Vdc/2 Vdc/2 -Vdc/2 The curret waveforms are calculated accordig the above formula. The comarisos betwee the 60-degree clamig SVM ad the roosed SVM are show i the Figure 4.13, where both the asymmetrical ad symmetrical oeratios are studied Exerimets Figure 4.14 shows the iut curret ad voltage waveform at 12 kw load for sigle module oeratio. The iut curret is i hase with the iut voltage. Figure 4.15 shows the iut curret of the aralleled modules with the roosed SVM. It ca be see that the currets o the same hase do ot overla each other exactly. They have circulatio curret at switchig frequecy, but there is o oticeable low frequecy curret oscillatio. The combied iut curret is tested over 60 A. Figure 4.16 shows the effect of the iterleaved switchig sigal ad the iut curret of the aralleled module. 104

26 100 V/div 50A/div Figure 4.14 Exerimetal waveform of the iut voltage ad curret i sigle module oeratio 105

27 Combied curret Module 2 Module 1 20 A/div Figure 4.15 Exerimetal waveforms of the iut curret i the arallel modules ad the total curret 106

28 Switchig clock 1 Switchig clock 2 Module 1 Module 2 Figure 4.16 Iterleaved switchig clock ad the curret waveforms. 107

29 4.3 The iteractio betwee frot-ed PFC coverter ad load iverter Characterizatio of the Iverter Load o the DPS Multi-Phase Iverter A three-hase voltage source iverter draws dc ower from the voltage source ad rovides ac voltage to the load. It ca rovide ac voltage to a motor load, or serve as secodary utility ower suly. The voltage source iverter is a buck tye iverter. While the iut voltage is choed ito ieces i order to cotrol the outut voltage, the outut curret is reflected to the iut side with switchig frequecy rile. I order to smooth the curret rile, a EMI filter geerally is eeded at the iut of the iverter. The iut filter is essetially a average elemet that averages the ulsatig curret ito a low frequecy cotiuous curret. For motor drive alicatios, there are fewer oortuities for load ubalace. However, for the secodary utility ower suly with higher ower requiremets, the ed user may lug the load ito the differet hases at ay momet; the ubalaced load coditio is ievitable. The four-leg iverter was roosed for the secodary utility ower system i [F8]. Figure 4.17 shows the system cofiguratios for the secodary ower system coected with various loads, such as comuters, air-coditioers, vetilatio fus, ad so o. The eutral leg has a iductor coected to the eutral oit i order to reduce eutral rile curret. Figure 4.17 (b) shows the average models of the four-leg iverter. The iut curret for the system is: Ii = D I + D IL + D I + D I a a b b c c (4.24) At a balaced load coditio, the eutral curret equals zero. The system is the same as that i a three-wire system. Equatio (4.24) ca be writte as: Ii = D I + D I + D a a b b c I c (4-25) where D a, D b, D c, ad D are the duty cycles of the to switches of the hase-legs, ad I a, I b, I c, ad I are outut currets. Similar to the PWM rectifier, with a balaced load coditio, the averaged iut curret of the iverter is a DC curret. 108

30 Ii + Vi _ Sa a b c Ia Ib Ic La Lb Lc Ca Cb Cc comuter Aircoditioer Ii + Vi _ D I D Vi + _ D a I a a D a Vi + _ D b I b b D b Vi + _ (a) D c I c c D c Vi + _ Ia Ib Ic I La Lb Lc Ca Cb Cc Vetilatio fa Four-wire AC utility bus comuter Aircoditioer Vetilatio fa L (b) I Four-wire AC utility bus Figure 4.17 Four-leg VSI as a secodary utility bus, (a) Circuit diagram, (b) Averaged model 109

31 Ii 20 A/div Va 500 V/div Vb 500 V/div Vc 500V/div Figure 4.18 Exerimetal waveforms of the four-leg iverter with balaced load coditio 110

32 Va 500 V/div Ii 20 A/div Vb 500 V/div Vc 500V/div Figure 4.19 Exerimetal waveforms of a four-leg iverter with ubalaced load coditio 111

33 At balaced load oeratio, eve though the duty cycle, Da, Db, ad Dc has a zerosequece comoet, it does ot cotribute to the iut curret of the iverter [F7]. The iut curret of the iverter has oly a dc comoet, as show i the exerimetal waveform. At ubalaced load coditio, however, the iut curret has ot oly the dc but the low frequecy 2ω rile comoet as well, as show i the exerimetal waveform of Figure Sigle Phase Voltage Source Iverter A sigle-hase voltage source iverter ca be used for auxiliary ower sulies or uiterrutible ower suly (UPS) for low ower alicatios. Basic circuit toologies iclude a full bridge or half bridge iverter with or without a isolatio trasformer. Takig the full bridge iverter as a examle, the iut ower is equal to the outut ower i oe lie cycle, assumig the iductor of the outut filter does ot cosume ay active ower. Therefore, equatio (4-26) ca be obtaied with a resistive load R. 2 Vo Pi = VdcIi = = Pout (4-26) R where, Vdc is the dc bus voltage, Ii is the iut curret, ad Vo is the outut voltage. Because the outut voltage is modulated as a siusoidal waveform, the outut voltage ca be writte as: Vo = DVdc (4-27) where D is the modulatio duty cycle which is a fuctio of time. Combiig equatio (4-26) ad (4-27) together, the iut curret ca be derived: DVdc Ii = D( ) (4-28) R I equatio (4-28), the term i aretheses is the load curret that is siusoidal, ad the duty cycle D is also a siusoidal fuctio; therefore, the iut curret ca be writte as: 2 2 Dm Vdc 2 Dm Vdc Ii( t) = si ( ωt) = (1 cos(2ωt)) (4-29) R 2R I equatio (4-29), Dm is the modulatio idex ad ω is the modulatio frequecy, From equatio (4-29), it is show that the iut curret of the sigle hase iverter has a 2ω rile. This heomeo is illustrated i Figure Figure 4.20 (a) shows a full bridge voltage source iverter with a LC iut filter. The iut voltage is 800 V. A SPWM modulatio scheme 112

34 with 20 khz carrier frequecy ad 60 Hz modulatio frequecy is used. The outut is coected to a resistive load. As show i Figure 4.20 (b), the outut voltage Vo is 120 V, the iductor curret i L is aroud 50 A, ad the iut curret has a 2ω rile of about 14 A. This curret is draw from the dc bus. A half-bridge voltage source iverter has similar iut ad outut characteristics as that of the full-bridge iverter. Figure 4.21 shows a half-bridge iverter with the simulatio waveforms with Figure 4.21 (a) showig the cofiguratio of the half bridge iverter ad Figure 5.21 (b) the outut voltage, outut filter iductor curret, ad the iut curret. The iut curret has a 2ω rile also Large Sigal Iteractios betwee Source ad Load Coverters Effect of Rile Curret o the dc Bus Caacitor Selectio It is evidet that if the dc bus has to suort the harmoic ower, it either comes from the source coverter or from the dc bus caacitors. The eergy associated with a simle siusoidal rile curret i k o a dc bus voltage Vdc is give by: E ( f ) = V Tk 2 i dc k 0 dt (4-30) where f is the rile curret frequecy, ad T k is the eriod of the harmoic frequecy. Equatio (4-30) also ca be writte as: E( f ) = V I E ( f ) E ( f ) = T k dc / 2 ac dt = f k (4-31) (4-32) E (f) is the ormalized eergy sectrum agaist rile frequecy i equatio (4-31). The eergy sectrum is i a reverse roortio to the rile frequecy. The lower frequecy rile cotet will have much higher eergy cotet. If the rile curret eergy is assumed come comletely from bus caacitors, the relatios betwee the rile voltage ad the bus caacitace is: C( f, V ) = Tk 2 ik dt ik E( f ) ik = = V V 2 Vf 2 (4-33) 113

35 + DC Bus Ii Iut Filter IL + Vo - _ R (a) Ii IL Vo (b) Figure 4.20 A full-bridge voltage source iverter (a) Circuit with a resistive load, (b) Oeratioal waveforms 114

36 + Ii DC Bus _ C1 C2 IL + Vo - R (a) Ii IL Vo Figure 4.21 A half-bridge voltage source iverter, (a) Circuit diagram, (b) Oeratioal waveforms (b) 115

37 mf V Figure 4.22 The dc caacitace as a fuctio of dc bus voltage ad rile frequecy 116

38 It ca be see from (4-33), that, to suort a dc bus with less rile, large caacitors have to be used. For examle, assumig a 50 A 120 Hz harmoic is suerimosed o a 800 V bus with some dc currets, the relatioshi betwee bus caacitace ad the rile voltage is illustrated i Figure It ca be see that i order to kee the bus withi a 10 V variatio rage, the dc bus caacitace has to be as large as 20 mf. The selectio of the caacitor is a system issue. But geerally seakig, a large caacitor usually is related to a large size ad high cost. It also affects the cotrol loo desig of the frot-ed coverters The Effect of Large Sigal Rile Curret to the Source Coverter There are two reasos that the low frequecy rile o the dc bus is likely to be roagated ito the frot-ed coverters. Firstly because the dc bus caacitor ormally is desiged at the idividual system level, it may ot be large eough to sustai the high-eergy cotet of the low frequecy rile comoet. Secodly, the badwidth of the voltage loo of the frot-ed coverter ca be higher tha the 2ω rile frequecy. The voltage rile o the dc bus caot be atteuated eough ot to affect the curret loo. The voltage loo of the frot-ed coverter rovides the referece sigal for the curret loo. At the ormal mode oeratio, the referece sigal of the curret loo is a dc comoet. Whe a 2ω comoet is mixed ito the curret loo referece, the curret will track the referece very closely because the curret loo has a higher badwidth. The duty cycles will be distorted as show i Figure Because of the distorted duty cycle, the iut curret of the frot-ed coverter is affected. Figure 4.34 (a) shows the three-hase PFC rectifier feedig various loads, these loads ca be divided ito differet frequecy sectra. Figure 4.34(b) shows the harmoic effect o a threehase ower factor correctio (PFC) frot-ed coverter as comared to the same coverter feedig a resistive load. As idicated by the simulatio waveform, the iut curret of the PFC is modulated by the rile curret. I order to maitai a stiff dc bus, the ulsatig ower is ushed back ito the ac source. This is the oosite actio as that of VSI. 117

39 Vo Da SVM Id Com. Idref Voref Db Dc Iq Com. Iqref=0 abc/dq ia,ib,ic Figure 4.23 Distortios i duty cycles, (a) The cotrol loo diagram, (b) The distorted duty cycle of the SVM by 2ω rile 118

40 Va Vc Vb Ia Ib Ic Vdc DC Pulsatig curret... 2ω rile curret DC bus voltage Vdc Ia, Ib, Ic Figure 4.24 The effect of the rile curret o dc bus to the rectifier, (a) Circuit diagram, (b) Oeratioal waveforms 119

41 The distortio of each of the three-hase iut currets is determied by both the ac curret magitude o the dc bus ad the hase shift agle betwee the harmoic curret ad the lie voltage. Because the ivert ad the frot-ed PFC are ot sychroized, there will be a hase shift betwee the 2ω rile curret ad the three-hase iut curret. If the hase shift agle betwee hase A ad the rile curret is defied as θ, the modulatio effect of the rile curret to the iut curret will be differet, as illustrated through Figures 4.25 to Because the three hases are symmetrical, these Figures oly show a chage of θ i 2π/3 rage. I Figure 4.25, the toe waveform illustrates the time domai hase A curret waveform, the bottom bar chart shows the frequecy sectra of the curret. There are three axes i this Figure; the vertical axis is the magitude of the curret, ad the horizotal axes are the frequecies ad the haseshift agles. As show i the frequecy sectra, the fudametal comoet chages with the hase-shift. The third harmoic curret exists i the waveform; however, it does ot chage with regard to the hase shift. There are other harmoic cotets i the curret with a relatively small magitude. A similar statemet ca be made to hase B ad hase C currets as show i Figures 4.26 ad The three Figures also idicate that the fudametal curret of each hase are ot the same at a same hase-shift agle θ, which meas there is a egative sequece curret. The third order harmoics, however, are the same, which is the zero-sequece curret. The above aalysis cocludes that the low frequecy harmoic curret o the dc bus ca roagate to the iut side of the source coverter. The distorted three-hase curret has a egative sequece comoet as well as a zero sequece comoet. The distortio of the iut curret will degrade the system erformace, icrease the extra loss, ad decrease system efficiecy. The harmoic curret roagated to the geerator ca also iteract with the sychroous rotatig field to excite symathetic shaft torsioal vibratios as reorted i [F4-5]. 120

42 Phase shift betwee Ia ad Iac =0~110 degree Magitude Frequecy S1 S2 S3 S4 S5 S6 S Phase shift 0 Figure 4.25 Phase A curret waveform ad its frequecy sectrum with differet hase shift agles 121

43 Phase shift betwee Ib ad Iac =0~110 degree Magitude Frequecy S1 S3 S5 S Phase shift Figure 4.26 Phase B curret waveform ad its frequecy sectrum with differet hase shift agles 122

44 Phase shift betwee Ic ad Iac =0~110 degree Magitude Frequecy 480 S1 S3 S5 S Phase shift Figure 4.27 Phase C curret waveform ad its frequecy sectrum with differet hase shift agles 123

45 4.3.3 Small Sigal Imedace Iteractio Itroductio to the Cocet of Mior Loo Gai For systems built at the box level, iteractios are most likely to occur whe they are used to lug ad lay. The most familiar sceario for such a iteractio is betwee a iut filter ad a regulator coverter. The outut imedace of the iut filter lookig from the regulated coverter behaves like a LC etwork. The iductor braches domiat at low frequecy, ad the caacitor braches domiat at high frequecy. The imedace eaks at the resoat frequecy of the iductor ad the caacitor. The eak value is determied by the damig of the filter. O the other had, the regulated coverter behaves like a egative resistor at low frequecy, ad the hase starts from egative 180 degrees to ositive 90 degrees at high frequecy. If the eakig of the outut imedace of the iut filter overlas with the iut imedace of the regulator, a oscillatio is likely to occur. The iteractios betwee the cascade system are characterized by usig the two-ort theory, as show i Figure At a give iut ad outut oeratig coditio, by alyig a small sigal erturbatio to the system, the iut ad outut voltage relatioshi of the boxes ca be defied as: g s = Vx Vi utermiated load (4.34) Vout g L = Vx utermiated load (4.35) The voltage trasfer fuctio from the iut to outut ca be obtaied by: Vout g s g L g = = Vi Z s 1+ Z L (4.36) where Z s is the outut imedace of the source box, ad Z L is the iut imedace of the load box. The ratio of the source to load imedace, Z s /Z L, is referred to as the mior loo gai ad is give as Tm. The ew eigevalues of a cascaded system ca be obtaied by solvig the equatio: 1+Tm=0 (4-37) Z Tm = Z s L (4-38) 124

46 The Nyquist criteria ca be alied to (4-37). If the Nyquist lot of the mior loo gai does ot ecircle the (-1,0) oit, the cascaded system will ot cotai ay right-half-lae eigevalues ad the system will be stable i the small sigal sese. A tyical source ad load system imedace ad mior loo gai is show i Figure If the Tm is out of the uity circle, it meas that the outut imedace of the source overlas with the iut imedace of the load box The Imedace Iteractios o the dc Bus Because of the EMI filters betwee the dc bus ad the load coverters, the iut imedace lookig ito the load is comosed of both the iut filter ad the regulated coverter. There are two commoly used iut filter cofiguratios: oe is the sigle stage filter, ad the other is the two-stage filter. The tyical iut imedace of such filters is show i Figure As a regulator is coected to the outut side of the filter, the iut imedace of the regulator will domiate the total imedace at low frequecy rage. Ad the imedace of the regulated coverter is exosed directly to the dc bus, because caacitor braches ca be viewed as oe circuited ad iductor braches are short-circuited. At the middle frequecy rage, the imedace characteristic becomes comlicated; it is a fuctio of the filter damig ad the desig of the regulated coverter. The high frequecy imedace is determied by the filter iductace ad the coverter iductace reflected to the filter side. Figure 4.30 shows the system block diagram cosistig of a PWM rectifier as dc bus regulator ad a sigle stage filter with the four-leg iverter as the secodary 60-Hz three-hase four-wire ac bus system. Figure 4.30 also shows the outut imedace of the bus regulator ad the iut imedace of the iut filter followed by the four-leg iverter. The outut imedace of the source coverter was aalyzed i the last chater, which resembles a LC etwork. The hase of the iut imedace still starts from the egative 180 degrees as that of a regulated coverter ad eds at ositive 90 degrees. Eve though there is a searatio of the outut imedace ad iut imedace, they are so close to each other that the dyamic resose of the distributed system is affected. Figure 4.31 shows the dc bus voltage uo a ste load chage at the iverter side. The bus voltage overshoots ad takes a log time to settle dow the oscillatio as show i the trasiet eveloe. 125

47 Vi Source Vx Load Vout Zs ZL Gai (db) ZL Zs Phase (deg) Zs ZL Im Tm Re Figure 4.28 The cascaded system i a distributed ower system ad the mior loo gai 126

48 Zi Gai(db) Zi Zi Gai(db) Zi Figure 4.29 The commoly used filter cofiguratios ad the their iut imedace 127

49 Ge. Filter AC/DC 100 kw Rectifier 800 V DC Bus + Vo _ Iload Zo Zi Filter DC/AC Four-Leg Iverter 3-h 4-wire Utility Bus Gai (db) Zi(s) Zo(s) Phase (Deg) Zo(s) Zi(s) Figure 4.30 The distributed ower system with a bus regulator ad a regulated four-leg iverter ad their iut ad outut imedace 128

50 Load ste chage curret DC bus voltage Trasiet eveloe Figure 4.31 Imedace iteractio o the dc bus 129

51 4.4 Commo Mode Noise Aalysis Based o Discrete Model Neutral Voltage Shift i Voltage Source Iverter I a ordiary three-hase system, if the three-hase voltage is a balaced siusoidal fuctio, the otetial of the load eutral oit will be equal to the otetial of the source eutral oit. I the switchig mode three-hase VSI, however, the outut voltage is geerally ulse width modulated by SVM. I this case, the otetial of the eutral oit is ot a fixed value, but istead, it fluctuates with resect to the other ode otetials. Table 4.3 shows the voltage betwee the eutral oit to the egative dc rail corresodig to the eight vectors of the SVM ad the related circuit toological states, where the Vdc is the voltage of DC bus. Figure 4.32 shows the simulated waveform ad exerimetal waveform of the eutral voltage shift roblem. I the followig aalysis, the otetial of the egative dc rail is take as the referece oit. Because the eutral voltage is a fuctio of sace vectors, it is evidet that differet SVM schemes result i differet shaes of the eutral voltage shift. Eve with the same SVM, the sequece of the d1, d2 ad d0 also has a effect o it. The 60-degree clamig SVM is used as the examle i Figure If the two duty cycles i two cosecutive switchig cycles are arraged symmetrically, which meas that oly oe switch is activated for each duty cycle chage, the eutral voltage will jum oly oe-third of the dc bus voltage. If the duty cycles are arraged i the same sequece i cosecutive switchig cycles, the eutral voltage ca jum two-thirds of the dc bus. Therefore, the magitude of dv/dt is a fuctio of the sequeces of the sace vectors. The eutral voltage ot oly has a high frequecy dv/dt, but alow frequecy comoet as well, which is referred to as the zero sequece voltage. The magitude of the zero sequece chages with the modulatio idex. Figure 4.34 comares the eutral voltage variatio agaist a chage of the modulatio idex. It ca be see from the waveforms that the smaller the modulatio idex is, the lower the lie-to-lie voltage, but the higher the zero sequece voltage. Figure 3.35 shows the frequecy sectrum of the lie-to-lie ad zero-sequece voltage as a 130

52 fuctio of the modulatio idex. As show i this Figure, there are the 3 rd, 9 th, ad 15 th harmoics i the zero-sequece voltage. Table 4.3 Neutral-to-egative dc rail otetial Vectors ad Toological States Neutral-DC Negative Potetial Vdc 2/3 Vdc 1/3 Vdc 0 131

53 Va Vb Vc Vab Vtl- (a) Va Vb Vc Vab V tl- (b) Figure 4.32 Neutral voltage shift i SVM iverter: (a) Simulatio, (b) Exerimet 132

54 Ts Ts d1 d2 d0 d0 d2 d1 Ts Ts d1 d2 d0 d1 d2 d0 Vdc 2/3 Vdc 1/3 Vdc 0 Vdc 2/3 Vdc 1/3 Vdc 0 (a) Figure 4.33 Neutral voltage: (a) Symmetrical SVM ad (b) Usymmetrical SVM (b) (a) (b) (c) (d) Figure 4.34 Neutral voltage as a fuctio of modulatio idex: (a) ad (b) Lie-to-lie voltage, (c) ad (d) Neutral voltage 133

55 Lie-Lie Voltage Md=1 Md=0.1 (a) Zero Sequece DC Md=0.1 Md=1 (b) Figure 4.35 Frequecy sectrum as a fuctio of the modulatio idex: (a) The lie-to-lie, (b) The eutral voltage 134

56 4.4.2 Proagatio of the DC Bus Noise Caused by Frot-ed Coverters Diode Rectifier as Frot-Ed Coverter Frequetly, the dc bus is fed by a three-hase diode rectifier. I such a system, the eutral oit of the three-hase source geerally is tied to the safety groud (GND). Because of the diodes, the egative dc rail always will ick u the lowest otetial of the three hase iuts. The ositive dc rail otetial is Vdc higher tha that. As a result, the two dc rails are two floatig otetials. The commo-mode voltage is formed. Sice the egative of the dc bus is the base oit for all secodary coverters, ay floatig voltage at this oit will roagate dowstream. With the voltage shift betwee its eutral oit ad the egative dc rail, the VSI s eutral voltage results from the combiatios of these two. Figure 4.36 (a) shows a diode rectifier fed VSI system, where three iut iductors are used. The simulatio ad exerimet waveforms of this system are show i Figures 4.36(b) ad (c). If oly a filter choke is used after the diode rectifier rather tha at the source iut, the egative dc rail will ick u exactly the lower eveloe of the three-hase voltage, as show i Figure Three-Phase Boost PFC Rectifier as Frot-ed Coverter For high ower factor ad high-voltage dc distributio, the three-hase boost rectifier is oe of the best choices. If the system GND is agai set at the source eutral oit, ad the SVM is chose for PFC cotrol, the egative dc rail voltage V agai highly fluctuates similar to the VSI. For examle, whe the vector is alied, the ositive dc rail will be at the same otetial as the eutral oit. Whe the vector is alied, the egative dc rail will be at the same otetial as the eutral oit. Table 4.4 shows the chage of the egative dc rail voltage corresodig to the eight vectors. I cotrast to the VSI, the voltage of the egative dc rail swigs betwee the mius Vdc to zero. Because the VSI s eutral voltage itself fluctuates betwee zero ad the ositive Vdc, their combiatios roduce a eutral voltage shift that is twice the dc bus voltage. For the PFC-VSI system, there ca be 64 combiatios of vectors, which corresod to 64 toological states. Figure 4.38 shows a examle of some of the combiatios of vectors i oe PFC switchig 135

57 cycle. Figure 4.39 shows a set of exerimetal waveforms, where the PFC switches at 16 khz with lie frequecy of 60 Hz, ad the VSI switches as 20 khz with outut at 500 Hz. The to waveform is the three-hase iut curret of the boost rectifier. The secod is the voltage betwee the VSI eutral ad the egative dc rails. The third oe is the voltage betwee the egative dc rail ad the source eutral oit. The bottom waveform is the combied eutral voltage with referece to groud. It is show that the combied eutral voltage has higher magitude of ulsatio. The commo-mode voltage o the dc bus resultig from the frot-ed PFC also takes a differet shae at low frequecy deedig o the SVM used. Figure 4.40 shows a simulatio waveform of V, V, ad Vtl, i which both the PFC ad VSI switch at 20kHz with the switchig clock sychroized. Figure 4.41 is the frequecy sectrum of the voltage V, V, ad Vtl. The zero sequece voltage of V i the 60 Hz lie frequecy rectifier has a eak at 180 Hz. The zero sequece of V i VSI has a eak at 15 khz with 500 Hz modulatio frequecy. The combied eutral voltage Vtl has both eaks i its zero-sequece comoets. Secodly, for either the PFC or VSI, the maximum dv/dt haes whe there is direct trasitio betwee two zero vectors. For the combied eutral voltage, the maximum dv/dt would occur if the PFC ad VSI erformed zero vector trasitios at the same time. The worst case would roduce a dv/dt that is twice as high as a idividual system. Figure 4.40 shows a combied dv/dt that is 167% higher tha that from the PFC or VSI idividually. Thirdly, because of the iut lie ad the iverter modulatio frequecies are ot costat, ad they are ot sychroized i most alicatios, the combied eutral voltage is modulated by these frequecies. The commo mode voltage also affects other loads o the dc bus because they ride o the same otetial as the egative dc rail. 136

58 V Va + Vx - Vc Vb Vdc V Vx Vy Vz Vzero Neutral + Vtl - (a) Va Vb Vc V V V zero Vtl (b) Va Vb Vc V Vzero Vtl Figure 4.36 Commo mode voltage i a diode frot-ed rectifier with three-hase iut choke, (a) System diagram, (b) Simulatio waveforms, ad (c) Exerimetal waveforms (c) 137

59 V Va + Vx - Vc Vb Vdc V Vx Vy Vz Vzero Neutral + Vtl - (a) Va Vb Vc V V Veutral Figure 4.37 Commo mode voltage i a diode frot-ed rectifier with DC iut choke, (a) System diagram (b) ad (b) Simulatio waveforms 138

60 Table 4.4. Negative dc rail voltage variatio corresodig to differet vectors. Vectors ad Toological States Voltage Shift o Negative DC Rail -Vdc -2/3 Vdc -1/3 Vdc 0 139

61 PFC VSI Vdc 2/3 Vdc 1/3 Vdc 0-1/3 Vdc -2/3 Vdc -Vdc t0 t1 t2 t3 t4 t5 t6 Figure 4.38 A examle of eutral voltage shift i PFC-VSI mode oeratio 140

62 Ia, Ib, Ic V Vdc Neutral - V + V - V + + Vtl - Ia Ib Ic V V Vtl Figure 4.39 Exerimetal results of eutral voltage shift at PFC-VSI mode oeratio 141

63 Ia Ib Ic V V Vtl Figure 4.40 Simulatio results of eutral voltage shift at PFC-VSI mode oeratio 142

64 Frequecy Sectrum of V Frequecy Sectrum of V (a) Frequecy Sectrum of Vtl (b) (c) Figure 4.41 Frequecy sectrums of the zero-sequece voltage, (a) Negative dc rail voltage, (b) Iverter eutral-to-egative dc rail voltage, ad (c) Combied voltage 143

65 DC Distributio System with Multile Geerators I order to achieve redudacy, multi-geerators ca be used for the ower distributio. The diagram of a system with two sets of geerators ad PFCs feedig a commo dc bus is show i Figure The system groud is assumed to be the eutral oit of the first geerator; the eutral of the secod geerator is floatig. This system is very similar to the PFC- VSI system discussed earlier. Because the dc lik carries a commo-mode voltage caused by the first PFC, the voltage aearig at the eutral of the secod geerator is elevated agaist the groud. Eve though the two sets of geerators are iteded to be the same for a redudat dc distributio, ractically, the magitude, frequecy, ad hase of the two geerators are differet. This meas that eve for the same cotrol, the timig of the SVM schemes i the two PFCs will be out of hase. Therefore, the combied atter of the dv/dt of the eutral voltage is agai modulated. Figure 4.42 shows a simulatio of two idetical geerators feedig PFCs searately with a timig shift of 25 µ s i the SVM at a switchig frequecy of 20 khz. The to waveform is the commo-mode voltage o the dc lik, the secod is the eutral voltage of the secod geerator, the bottom waveform is the voltage at the termial of the secod geerator. Because of the eutral voltage shift betwee the two geerators, huge groudig curret will flow if the two geerator eutral oits share the same GND i the above cofigured system as illustrated i Figure The magitude of the groudig curret is determied by the imedace alog the commo-mode voltage A tyical voltage fall time, t f, of the IGBT tur-off is less tha 500 s, the dv/dt rate i such a situatio ca be as high as 2Vdc/µs. The leakage curret is give by: Vdc I leakage = C arasitic = 2C t f arasitic Vdc With a 400 dc bus, ad 5 F caacitor, such a curret ca be as high as 4 A. (4-39) 144

66 Vc Va Vb Za Zb Zc Vai Vbi Vci Vdc V V Vx Vy Vz Za Zb Zc Vb1 Va1 Vc1 Potetial o Negative DC Rail Neutral Potetial o PFC2 Termial Voltage o PFC2 Figure 4.42 The commo-mode oise i aralleled rectifier system Vc Va Vb Za Zb Zc Vai Vbi Vci Vdc V V Vx Vy Vz Za Zb Zc Differet Source ( f=5hz) SVM Timig (25 usec) Vb1 Va1 Vc1 Iut Voltage ad Curret of PFC1 Iut Voltage ad Curret of PFC2 Figure 4.43 The groudig curret betwee aralleled rectifiers with a commo groud 145

67 4.4.3 The Effect of System Groudig The roblems brought about by the voltage shift iclude system groudig, isolatio, leakage curret, bearig curret for motor loads, ad iterferece to cotrol [E1-E8]. It is aaret that the voltage shift deeds o where the system referece oit is set: the groud. There are several situatios regardig system groudig as show i Figure The first is a ower system with o isolatio trasformers. I this case, the commo mode curret ca flow directly from the voltage floatig oit to the groud oit through arasitic caacitors. The secod is a ower system with a isolatio trasformer. This is the case with utility ac ower, where the groudig oit geerally is set i a mai trasformer. Because the chassis of the equimet are always tied to the groud for safety, the leakage curret ca flow from the voltage floatig oit through the arasitic caacitace existig i trasformer widigs ad equimet chassis. The third is a floatig stad-aloe dc distributio system. I this case, the commo mode curret aths are similar to the secod situatio. It is kow that a floatig system ca kee oeratio i case of oe oit groud fault. However, if the system has grouded at oe oit, the voltage otetials at other oits are lifted, the overall system oise atters are chaged accordigly; this might threate the cotrol circuitry ad affect the system oeratio. I ay cases, the groud is the commo oit for the leakage curret to flow. For a stadaloe distributed system, if the groudig oit ca be arbitrarily selected, the best oit of groudig is at the middle oit of the dc lik. Because all of the system otetials will be refereced to this oit, this will localize the voltage shift to each subsystem istead of elevatig oe or the other. This is illustrated i the exerimetal results of a VSI i Figure I Figure 45 (a), the bottom waveform shows the eutral voltage measured agaist the egative dc rail. The voltage shifts uward by the dc lik voltage. Whe the voltage was measured betwee the eutral ad the midoit of the dc lik, as show i Figure 45 (b), it oly shifts half of the dc lik voltage. The to waveform i each case is the three-hase outut curret of the VSI. 146

68 Vc Va Vb Vc Va Vb Va Vc Vb Figure 4.44 Three groudig methods: (a) Solid groud system (b) Groud system with isolatio trasformer (c) Floatig system 147

69 Ia, Ib, Ic 10A/div V tl-eg 200V/div (a) Ia, Ib, Ic 10A/div Vtl-mid 200V/div Figure 4.45 Neutral voltage shift measured agaist differet referece oits: (a) Negative dc rail, (b) (b) Mid-oit of dc lik 148

70 4.4.4 Sace Vector Modulatio Effects The dv/dt eetrates the stray caacitace ad forms EMI curret. The commo-modecurret ca be reduced by isertig commo mode choke ito the curret loos. Meawhile, because the zero-voltage-soft-switchig (ZVS) cotrols the slew rate of the dv/dt, it also reduces the commo mode curret. This sectio discusses the mitigatio methods related to SVM. Because there are umerous ways to sythesize the referece vector i a SVM, oe atural idea is to use the vectors that are 120 degrees aart o the hexago. The zero vectors are sythesized usig the three vectors. Suose the calculated duty cycles are d1, d2, ad d0 as usual; i order to use three vectors (120 aart) to make a zero vector, the zero vector time is evely distributed amog them. Therefore, d0 =1/3 d0 (4-40a) d1 =d1+d0 (4-40b) d2 =d2+d0 (4-40c) Usig this modulatio, the eutral voltage is ket at oe voltage level i a sixty-degree eriod. At the sector trasitio, it goes u/dow to aother voltage level, which has a V equal to oe third of the dc bus voltage. But there are ealties agaist the use of this modulatio. The first oe is the higher curret rile. The secod oe is the limited modulatio idex. This is obvious because the adjacet vectors ca roduce a vector twice as log as that roduced by vector that are 120 degrees aart. The maximum modulatio deth is half of the modulatio idex usig the ormal method. The other methods are to use oly six active vectors, but ot the zero vectors. Oe of them is described i Chater 3. I this modulatio scheme, oe still uses the adjacet vectors to sythesize the referece vector. The zero vectors are made by oosite vectors. I this case, the eutral voltage fluctuatio is betwee oe ad two-thirds of the dc bus voltage. Figure 4.46 shows the comariso betwee the covetioal method ad the oe without zero vectors i the boost PFC rectifier. I Figures 4.46 (a) ad (c), the covetioal sace vector modulatio scheme is used. The leakage curret betwee the heat sik ad the groud has higher magitude. Figures 4.46 (b) ad (d) show the case of usig oly six vectors. It is show that the voltage 149

71 betwee the middle oit of the hase leg ad the groud varies betwee 1/3-2/3 dc bus voltage. Therefore, the leakage curret is reduced. The middle traces are the rectifier iut curret System Cofiguratios with Less Voltage Shift Four-wire PWM Rectifier System There are other system cofiguratios which ca be used for a distributed ower system with reduced commo-mode voltage. A four-wire frot-ed PFC rectifier ca be used for ac/dc coversio, as show i Figure The hase wires are coected to the middle oit of the hase legs as usual, ad the eutral wire is coected to the middle oit of the dc bus. The fourth leg is used i order to kee the voltage balace betwee the caacitors. The overall system structure is modularized with hase legs. The hase legs ca be cotrolled ideedetly. The siusoidal PWM (SPWM) ca be used for each hase. I sigle-hase oeratio, the eutral wire curret equals the hase curret. I three-hase oeratio, because the sum of the threehase curret i a balaced system is equal to zero, the eutral wire curret has rile curret oly. By allowig the rile curret to flow, the eutral oit has the same otetial as the middle oit of the dc lik. There will be o fluctuatig commo mode voltage o the dc bus. Assumig i steady state the hase curret has a siusoidal curret ad a rile curret: i ( t) = I si( ωt) + i a b a a i ( t) = I si( ωt 2π /3) + i b i ( t) = I si( ωt + 2π /3) + i a The eutral curret is: a b c (4-41) i = i a + i b + i c (4-42) Because the rile curret is small comared to the average curret, the eutral wire curret will be small also. As the load chages, the duty cycle chages accordigly. But for the SPWM modulatio, the eutral curret does ot icrease because there is o commo mode voltage i the hase modulatio voltage as that of SVM. The comariso of the eutral curret uder 100%-20% load is give i Figure

72 (a) (b) Voltage shift Leakage curret (c) (d) Figure 4.46 Neutral voltage ad leakage curret with differet SVM: (a) Covetioal SVM, (b) The SVM without usig zero vectors 151

73 As a dc distributio system, there will may coverters o the dc bus. Each coverter usually has a local caacitor, which lays as a buffer betwee the dc bus ad local system. Because there is a eutral wire coected to the middle oit of the frot-ed source dc bus caacitor, oe atural questio is whether a three-wire dc distributio bus is required to coect the middle oit of the frot-ed rectifier to all the subsystems. The aswer is o, because the eutral wire oly hadles the rile circulatio ower; the active ower is rovided by the fudametal comoet of the iut rectifier. As a comariso, the relatioshi betwee the modulatio voltage ad the dc bus for the three-wire rectifier is:: Vab = Vdc For a four-wire boost rectifier, the maximum achievable modulatio voltage is: (4-43) 1 Va = Vdc (4-44) 2 Therefore, for a give DC bus voltage, the three-wire rectifier requires lower iut voltage. The differece is 87% ( 3 / 2 ). Meawhile, the switchig loss reductio techiques associated with SVM are ot available for a four-wire PFC circuit. Because the four-wire rectifier is a modularized cofiguratio, it is very easy to arallel the systems. The aralleled system structure is show i Figure 4.48 (a). The system oeratio is the same as that of the sigle hase arallel because the dc bus caacitors decoule the three-hase systems. With iterleaved SPWM cotrol, The rile of the iut curret ca be reduced, as show i Figure 4.48 (b). The eutral wire curret ca be reduced also Four-Wire Voltage Source Iverter As a alterative to the system show i Figure 4.17, the voltage source iverter ca be cofigured ito aother form by usig the half-bridge toology as show i Figure I this system, the eutral oit is tied directly to the middle oit of the caacitor. Each hase leg is the same as a stad-aloe sigle hase iverter. The three hases ca be sychroized by iterleavig the modulatio frequecy 120 degrees to roduce three-hase voltage. I a balaced load oeratio, there is o et curret goig ito the eutral leg. I a ubalaced load oeratio, the eutral wire will carry the extra curret. The eutral leg iductor curret is 152

74 cotrolled such that it equals the curret i the eutral wire; Therefore there is o et curret goig ito or out of the ode of the dc bus middle oit. Therefore, the voltage of the caacitor ca be balaced. Meawhile, the system is modularized with the hase-leg structure. There is o commo mode voltage shift as comared to the full-bridge couterart. It also offers a good fault tolerace i case oe or more hases were broke. The disadvatage is that the dc bus voltage utilizatio is low. The outut voltage of the hase voltage is half of the dc bus voltage. However, for utility 120 V AC ower suly, 800 V dc bus is eough. 153

75 V Va Vc Vb Vai Vbi Vci I V (a) Neutral wire curret Voltage of the dc rails Iut voltage ad curret (b) Neutral wire curret Voltage of the dc rails Iut voltage ad curret (c) Figure 4.47 The four-wire rectifier system, (a) System diagram, (b) 100% load, ad (c) 20% load 154

76 DC Bus Total curret (a) Iut curret of module 1 Iut curret of module 2 (b) Figure 4.48 Paralleled four-wire PWM rectifiers, (a) System diagram, (b) Total ad idividual iut curret 155

77 I Va Vb Itl Vc Three-hase Four-wire Utility Bus (a) Neutral wire ad eutral leg curret Three-hase voltage Three-hase iductor curret DC bus voltage (c) Figure 4.49 A four-wire iverter for utility ower suly, (a) System diagram, (b) Oeratioal waveforms with ubalaced load 156