Delta- Sigma Modulator with Signal Dependant Feedback Gain

Transcription

1 Delta- Sigma Modulator with Sigal Depedat Feedback Gai K.Diwakar #1 ad V.Vioth Kumar *2 # Departmet of Electroics ad Commuicatio Egieerig * Departmet of Electroics ad Istrumetatio Egieerig Vel Tech Uiversity,Cheai, Idia. 1 drdiwakar@veltechuiv.edu.i 2 viothkumarv@veltechuiv.edu.i Abstract Higher order Delta-Sigma Modulator (DSM) is basically a ustable system. The approximate coditios for stability caot be used for the desig of a DSM for idustrial applicatios where risk is ivolved. The covetioal secod order, sigle stage, sigle bit, uity feedback gai, discrete DSM caot be used for the ormalized full rage (-1 to +1) of iput sigal sice the DSM becomes ustable whe the modulus of the iput sigal is above The stability is also ot guarateed for amplitude of iput sigal less tha I this proposal, the covetioal secod order DSM is modified with iput sigal depedat feedback path gai. The proposed DSM is suitable for idustrial applicatios where oe eeds the digital represetatio of the aalog iput sigal, durig each samplig period. This first cofiguratio of proposed DSM ca operate for the full rage of iput sigal without causig istability. I order to improve the SR of first cofiguratio, it is combied with covetioal secod order DSM ad proposed the secod cofiguratio of DSM. I. IRDUCTI I the covetioal discrete secod order DSM [1],[2] ad [3] the samplig of iput sigal ad DSM operatio is performed by sigle clock sigal with period T C ad is show i Fig.1. The block D is the delay uit of oe clock period (T C ) ad the block Q is biary quatizer. I Fig.1, x(i), x 1 (i), x 2 (i) ad y(i) represet the i th sample of iput sigal, first itegrator output, secod itegrator output ad quatizer output respectively. The quatizatio error sigal durig i th samplig period is deoted as e(i). Fig.1 - Covetioal Secod-rder DSM The differece equatio goverig the secod-order DSM, is give by, Y(i) = x(i) + e(i) -2e(i-1) +e(i-2) (1) The average value of the digital output durig update period T U (T U >>T C ), is equal to the average value of the discrete iput sigal durig the same period. The DSM becomes ustable whe the modulus of the iput sigal is above I [4] is proposed a method for achievig adaptive reductio i the order of the loop filter of usual high-order, sigle-stage, sigle-bit DSM i order to improve the stability rage ad SR. The resultig DSM recovers from istability, with exteded iput rage whe compared to the correspodig covetioal DSM but the SR starts fallig dow whe the iput sigal amplitude exceeds Accordig to [1] ad [5] loop stability is obtaied by feed forward coefficiets ad feedback coefficiets ad are added to optimize quatizatio oise respose i base bad. By usig multiple feed forward ad feedback features ito secod order structure, more flexibility is obtaied for improvig stability ad improvig dyamic rage. I the research papers [6] ad [7] is proposed a sigle-loop DSM with exteded dyamic rage. It employs a auxiliary quatizer to process the quatizatio error of the mai quatizer. This simple additio guaratees improved stability over a wider sigal iput rage ad also reduces the sesitivity to the frot-ed DAC oliearity. ISS : Vol 7 o 1 Feb-Mar

2 I [8] is proposed Sturdy MASH (multi-stage oise shapig) DSM which provides reduced sesitivity to circuit o-idealities but ot stable for the full rage of iput sigal. The Sturdy MASH becomes ustable whe the iput sigal is aroud -2dB. I [9] is proposed Mixed order sturdy MASH DSM which also provides better reduced sesitivity to circuit o-idealities but becomes ustable whe the iput sigal is aroud -3dB. Pui-Kei Leog et. al. i [10] describes the desig ad implemetatio of low power Delta-Sigma digital pulse width modulatio cotroller for switchig coverters which ca operate at high frequecy. Smaller quatizer with a limiter is used i the digital Delta-Sigma modulator to miimize the area cosumptio. The resultig SR after implemetatio is decreased whe the iput amplitude is higher tha 0.9FS. Jiaxi Ju et. al. i [11] preseted a low voltage switchig capacitor DSM ad focused o the implemetatio of uity gai ad covetioal DSM which could reduce the requiremet of operatioal amplifier DC gai ad was able to reduce the circuit complexity, power cosumptio ad area. However, the SR falls whe the ormalized iput sigal exceeds -3dB. I the research paper [12] is proposed sigle-loop DSM with exteded dyamic rage which provides spurious free dyamic rage of 87.5dB. I [13] is preseted, describig fuctio approach to study the overload of multibit quatizer. For dc sigal, whe the magitude of iput is greater tha 0.8, the DSM becomes ustable. I the preset proposal, the proposed DSM ca fuctio for the full rage of iput sigal. The iput sigal ca be dc or sie sigal. I [14] is proposed a approach to fid the modulator which maitais its performace like stability, SR etc. agaist the parasitic effects. The SR falls whe the iput is aroud -3dB. I the preset proposal, the SR ever falls after certai rage of iput sigal. The SR icreases steadily for the full rage of iput sigal. Two cofiguratios of DSMs are proposed (DSM1 ad DSM2). I the proposed DSM1, the demodulated sigal closely follows the sampled aalog iput sigal for the etire ormalized rage -1 to +1. The maximum value of the error sigal is 0.8mV (0.08%). The SR ever falls after certai rage of iput sigal. The SR steadily icreases ad reaches the maximum value at Full scale. I the power spectral desity (PSD) the oise level is much below the sigal level ad so the oise ca be easily filtered out from the sigal. The secod cofiguratio DSM2 is the combiatio of DSM1 ad covetioal DSM. I DSM2, the SR is maximized for the etire rage. II. BLCK DIAGRAM F PRPSED DSM F CFIGURATI 1 (DSM1) The block diagram of the proposed secod order DSM1 is show i Fig.2. The sample ad hold circuit S/H1 samples the iput sigal at a samplig period T C ad is deoted as (x) TC. (x) TC is fed to the iput of DSM. The S/H2 circuit samples the iput sigal at a samplig period T U ad is deoted as (x) TU. The feedback gai is (x) TU (>1). I [14] the iput sigal fed to the DSM is dc beig it is sampled at T U. I this proposal, the iput sigal is sampled at T C as i the case of covetioal DSM, the operatig period of DSM2 is proportioal to (x) TU ad the DSM circuit is operatig at T C. Fig. 2 - Proposed DSM1 with sigal depedat feedback gai ISS : Vol 7 o 1 Feb-Mar

3 Durig each update period, the bit stream at the output of quatizer gives the digital represetatio of iput sigal. The average value of bit stream at the output durig each update period is equal to the average value of sampled iput sigal. The ormalized value of y (y) is equal to the ormalized iput sigal (x/). I the proposed DSM, the output of first summig uit is equal to (x) TC - (x) TU ( if y(k)=1) ad this quatity is much less tha the output of first summig uit i the covetioal DSM ((x) TC -). This fact makes the outputs of the itegrators much less. The proposed modulator icreases the iput sigal rage to full scale. The upper boud of the state variable x 2 ever overloads the quatizer ad hece the proposed DSM is stable for the complete rage of the iput sigal. The dyamic rage, SR i the higher rage ad PSD are better tha the covetioal DSM ad DSMs proposed i the referred papers. A. Relatio betwee Iput ad utput i the Proposed DSM1 The operatig time, T of the DSM circuit durig each update period is varied proportioal to ( x) TU = x.therefore, T = k x (2) where k is the costat of proportioality. Substitutig i equatio (2) that whe x = xmax =, T = T U results i T TU k x TU =. Substitutig the value of k i equatio (2), gives the value of T as; = (3) The average value of the DSM output durig T (y ) is equal to the average value of iput samples divided by x durig T. Therefore, ( x ) / 1 m y' = x where is the umber of samples durig T. By defiitio, the average value of the output sigal durig T is give by, y = p T T C ' (5) where P is the et umber of pulses at the output. Therefore, p TC ( x ) / 1 m = T x Substitutig, T x T U = i equatio (6), P ca be give as T ( x ) / U 1 m p = 2 (7) TC The average value of output (y) durig a update period is give by, ptc y = (8) TU Substitutig the value of p from equatio (7) i equatio (8), y is give by, 1 ( xm ) / y = (9) 2 Therefore, the average value of the output is proportioal to the average value of iput. The ormalized ( xm value of y (y) is equal to the ormalized value of iput which is give by 1 ) /.. (4) (6) ISS : Vol 7 o 1 Feb-Mar

4 B. Simulatio Results of Proposed DSM 1 The simulatio results of third order DSM1 for dc sigal are show i Fig.3.The itegrator outputs ever icrease abruptly ad hece the DSM is stable for the full rage of iput sigal. The quatizer output is a sequece of pulses of amplitude +1 ad -1 ad ever remais costatly at +1 or -1which proves that the proposed DSM is stable. The error sigal for dc iput is 0.7µV. The simulatio results of third order proposed DSM1for siusoidal sigal is show i Fig.4. Fig. 4(b) to Fig. 4(e) show the differet outputs of proposed for sie sigal of ormalized peak amplitude 1 ad frequecy 45Hz which is show i Fig. 3(a). From Fig.4(b), Fig.4(c) ad Fig. 4(d) it is evidet that the itegrators output ever icrease abruptly. The upper bouds of the itegrator outputs are well withi the safe limits. Fig.4(e) shows the output of the quatizer of proposed DSM. The output is a sequece of pulses of amplitude +1ad -1, cofirmig the stable operatio of the circuit. Fig. 4(f) shows the ormalized average value of the quatizer output durig each samplig period. It ca be see that the demodulated sigal closely follows the sampled aalog iput sigal for the etire ormalized rage -1 to +1. I Fig. 4(g) is show the error sigal (x/-y) ad the maximum absolute value of the error sigal is 0.8mV (0.08%). Fig.3 - utputs of Proposed DSM1 for Sie Sigal [Horizotal axis- Time i sec, Vertical axis- Voltage i Volts, T U =0.2442msec, T C =0.1μsec, x or =1 ad =1.5]. Fig.4 - utputs of Proposed DSM1 for Sie Sigal [Horizotal axis- Time i sec, Vertical axis- Voltage i Volts, T U =0.2442msec, T C =0.1μsec, x orp =1 ad =1.5]. ISS : Vol 7 o 1 Feb-Mar

5 Fig. 5 compares the SR of covetioal secod order DSM ad the proposed DSM1. I the proposed DSM, the SR ever falls after certai rage of iput sigal. The SR icreases with differet slopes ad reaches 75.9dB whe x orp is equal to 0dB.The dyamic iput rage of positive SR of proposed DSM is 75dB. The maximum SR of covetioal DSM is 71.5 db whe x orp is equal to -7dB ad whe x orp >-7dB, the SR falls. For x orp -7dB, the SR of proposed DSM is little less tha the SR of covetioal DSM. For x orp > - 7dB, the SR of covetioal DSM falls rapidly but the SR of proposed DSM cotiues to icrease. Fig.5 - Compariso of SR of Proposed DSM1 with Covetioal DSM (SR=64, T U = msec, T C = 0.1μsec, f sig =45Hz) The output of proposed DSM is passed through the ruig average filter. The average is take for the update period T U. The PSD is plotted for the output sigal from the filter ad is show i Fig.6. The PSD gives the power spectrum of the voltage applied to the load. The PSD is draw usig FFT legth of 4096 ad with samplig frequecy f U is equal to khz. I the plot of PSD, the sigal level is at 25 db ad the oise level is at -60dB. The sigal is well separated from the oise. Fig.6 - PSD of proposed DSM1 (x orp = 1). I the proposed DSM1, the outputs of the subtractor uits are kept uder cotrol by the feedback of (x) TU. This reaso makes the DSM stable for the full rage of iput sigal with better SR ad PSD. III. PRPSED DSM F CFIGURATI 2 (DSM2) DSM2 is the combiatio of DSM1 ad covetioal DSM. Whe x or 0.55 (-5dB) it fuctios as covetioal DSM ad whe x or > 0.55 it fuctios as proposed DSM1. The idea is to maximize the SR ad keep the DSM stable for the complete rage. The block diagram of proposed DSM2 is show i Fig.7. Whe x or 0.55, RS1 flip-flop is set ad output Q is i phase Ф 1. Durig Ф 1, x aalog is sampled at T U ad is fed to DSM. Durig Ф 1, the switch SW1 coects 0V to the iput of cotrol circuit, SW2 disables RS2 ad SW3 coects the feedback gai 2 i the feedback circuit. I short, if x or 0.55, the circuit is operatig as DSM1. Whe x or > 0.55, RS1 flip-flop is ISS : Vol 7 o 1 Feb-Mar

6 reset ad output Q is i phase Ф 2. Durig Ф 2, x aalog is sampled at T U ad is fed to DSM. Durig Ф 2, the switch SW1 coects x aalog to S/H2 of cotrol circuit, SW2 eables RS2 ad SW3 coects the feedback gai x i the feedback circuit. If x or > 0.55, the circuit is operatig as DSM2. DSM3 is stable for the full rage (x or varies from -1 to +1). I the lower rage ( x or 0.55 ) the SR of DSM3 is better tha the SR of DSM2. Fig.7 - Proposed DSM combied with covetioal DSM. I DSM2, y is proportioal to x i each samplig period. Whe operatig as covetioal DSM, the x x x ormalized value of y is equal to y = = = ormalized iput. Whe operatig as DSM1, y = 2 as give by equatio (9). Therefore, i DSM2 the ormalized output is equal to ormalized iput for the etire rage of ormalized iput sigal (-1 to +1). DSM2 is stable for the full rage of iput sigal. Sice it is a combiatio of covetioal DSM i the stable rage ad DSM1, the overall SR of DSM2 is better tha DSM1 ad covetioal DSM. The SR plot of proposed DSM2 is show i Fig.8. For x or 0.55, the SR plot is same as that of covetioal DSM ad for x or > 0.55, the SR plot is same as that of proposed DSM1.For the full rage, the proposed DSM2 has better SR compared to proposed DSM1 ad covetioal DSM. \ Fig.8 - SR plot of proposed DSM2 IV. CCLUSI The proposed two cofiguratios of DSMs ca fuctio for the full rage of iput sigal ad remai i stable coditio. I the proposed secod cofiguratio, the SR is maximized for the full rage of iput sigal. I the PSD of both the cofiguratios the oise level is well below the sigal level. ISS : Vol 7 o 1 Feb-Mar

7 REFERECES [1] Schreier R., Temes G.C., Uderstadig Delta-Sigma Data Coverters, IEEE Press [2] orsworthy S. R., Schreier R. ad Temes G. C., Delta-Sigma Data Coverters, Theory, Desig ad Simulatio, ew York, IEEE Press, [3] Bourdopoulos G.I., Delta-Sigma Modulators Modelig, Desig ad Applicatios, Imperial College Press., [4] Bourdopoulos G.I., Adaptive order reductio scheme for high-order sigle-bit ΔΣ Modulators. IEEE Trasactios o Circuits ad Systems., Vol. 51, o. 5, pp ,2004. [5] Bourdopoulos G.I., Delta-Sigma Modulators Modelig, Desig ad Applicatios, Imperial College Press [6] Temes G.C. ad Shao-Feg Shu, Dual Quatizatio versamplig Digital-to- Aalog Coverter U.S. patet # 5,369,403., [7] Maghari., Temes G.C. ad Moo U., Sigle loop ΔΣ modulator with exteded dyamic rage Electroics letters, Vol.44, o.25, pp , [8] Maghari., Kwo S., Temes G.C. ad Moo U., Sturdy MASH Δ-Σ Modulator, Electroics Letters, Vol.42, o.22, pp , [9] Maghari., Kwo S., Temes G.C. ad Moo U., Mixed rder Sturdy MASH Δ-Σ Modulator, IEEE Iteratioal symposium o Circuits ad Systems, pp , [10] Pui-Kei Leog, Chu-Hug Yag, Chi-Wai Leg ad Chie-Hug Tsai, Desig ad implemetatio of Sigma-Delta DPWM cotroller for switchig coverter,ieee Iteratioal Symposium o Circuits ad Systems, pp , [11] Jiaxi, Warog Zhag, Haoli Du, Yafeg Jiag ad Yami Zhag, ew architecture of low voltage Sigma-Delta ADC IEEE 8th Iteratioal Coferece o ASIC, pp , [12] Maghari., Temes G.C. ad Moo U., Sigle loop ΔΣ modulator with exteded dyamic rage Electroics letters, Vol.44, o.25, pp , [13] Pieter Rombouts, Maarte De Bock, Jeroe De Maeyer ad Ludo Weyte, A describig fuctio study of saturated quatizatio ad its applicatio to the stability aalysis of multi-bit sigma delta modulators IEEE trasactios o circuits ad systems-i, Vol.60, o.7, July2013. [14] Bart De Vuyst, Pieter Rombouts ad Georges Giele, A rigorous approach to the robust desig of cotiuous time delta-sigma modulators IEEE trasactios o circuits ad systems-i, Vol.58, o.12, December [15] K.Diwakar, C.Sethilpari ad Ajay Kumar Sigh, Highly stable Delta-Sigma Modulator for idustrial applicatios IEICE Electroics Express, Japa, Vol.5, o.15, , ISS : Vol 7 o 1 Feb-Mar