Sampling. Introduction to Digital Data Acquisition: Physical world is analog CSE/EE Digital systems need to

Transcription

1 Itroductio to Digital Data Acuisitio: Samplig Physical world is aalog Digital systems eed to Measure aalog uatities Switch iputs, speech waveforms, etc Cotrol aalog systems Computer moitors, automotive egie cotrol, etc Aalog-to-digital: A/D coverter (ADC) Example: CD recordig Digital-to-aalog: D/A coverter (DAC) Example: CD playback CSE/EE 474 1

2 A little backgroud For periodic waveforms, the duratio of the waveform before it repeats is called the period of the waveform 3 Freuecy the rate at which a regular vibratio patter repeats itself (freuecy = 1/period) 4 CSE/EE 474

3 Freuecy of a Waveform The uit for freuecy is cycles/secod, also called Hertz (Hz). The freuecy of a waveform is eual to the reciprocal of the period. 5 Freuecy of a Waveform Examples: freuecy = 10 Hz period =.1 (1/10) secods freuecy = 100 Hz period =.01 (1/100) secods freuecy = 61.6 Hz (middle C) period = (1/ 61.6) secods 6 CSE/EE 474 3

4 Waveform Samplig To represet waveforms i digital systems, we eed to digitize or sample the waveform. side effects of digitizatio: itroduces some oise limits the maximum upper freuecy rage 7 Samplig Rate The samplig rate (SR) is the rate at which amplitude values are digitized from the origial waveform. CD samplig rate (high-uality): SR = 44,100 samples/secod medium-uality samplig rate: SR =,050 samples/secod phoe samplig rate (low-uality): SR = 8,19 samples/secod 8 CSE/EE 474 4

5 Samplig Rate Higher samplig rates allow the waveform to be more accurately represeted 9 Digital Data Acuisitio Data Represetatio - Digital vs. Aalog Aalog-to-Digital Coversio Number Systems Biary Numbers Biary Arithmetic Samplig & Aliasig 10 CSE/EE 474 5

6 Aalog-to-Digital Coversio Coverts aalog voltages to biary itegers. Aalog Voltage Samplig ADC Biary Itegers (0s & 1s) Voltage Time 11 Aalog-to-Digital Coversio ADC calibratio Calibratio Curve ( 3 bit ADC) Iteger Code Aalog Voltage 1 CSE/EE 474 6

7 Aalog-to-Digital Coversio Iput Rage Uipolar: ( 0, V ADCMAX ) Bipolar: ( -V ADCMAX, +V ADCMAX ) (Nomial Rage) Clippig: If V IN > V ADCMAX, the V OUT = V ADCMAX V ADCMAX time -V ADCMAX 13 Aalog-to-Digital Coversio Quatizatio Iterval (Q) bit ADC, the iput rage is divided ito -1 itervals. Iteger Code bit ADC: Q V V ADCMAX = 1 Iteger Code ADC mi Aalog Voltage Aalog Voltage 14 CSE/EE 474 7

8 Aalog-to-Digital Coversio Voltage to Iteger Code bit ADC Voltage: V ADCmi Q V IN V ADCMAX Code: 0-1 Positive Codig: V Code = Roud IN V Q ADC mi Positive ad Negative Codig: Code = Roud VIN Q 15 Why A/D-coversio? Aalog iput Aalog sigal processig ADC DAC Aalog sigal Processig Aalog output Sigle chip Digital sigal processig Sigals are aalog by ature ADC ecessary for DSP Digital sigal processig provides: Close to ifiite SNR Low system cost Repetitive system ADC bottle ecks: Dyamic rage Coversio speed Power cosumptio 16 CSE/EE 474 8

9 A/D-coverter basics t t t T S v f IN IN, A ( t) f Ati-alias filter f IN v IN ( t) f Sample & hold Quatizer fin D OUT [ ] F S / FS f Time cotiuos Amplitude cotiuos F S Time discrete Amplitude cotiuos Time discrete Amplitude discrete D D ideal OUT real OUT Samplig clock [ ] = Gideal vin ( Ts) + ( ) [ ] = G ( 1+ ε ) v ( Ts) + ( ) + e ( ) + e ( ) + e ( ) + e ( ) ideal IN offset oise jitter distortio 17 The Theory Samplig theory is a subset of commuicatios theory Same basic math Wat to record sigal, ot oise Quatizatio: Coversio from aalog to discrete values Codig: Assigig a digital word to each discrete value Thermometer code, Gray code... Quatizatio adds oise Aalog sigal is cotiuous Digital represetatio is approximate Differece (error) is oiselike 18 CSE/EE 474 9

10 Some termiology Resolutio (): Number of states i bits Example: A 3-bit A/D Full-scale rage (FSR): The iput or output voltage rage Example: ADC iputs outside the FSR are always 111 or 000 Step size (Q): FSR Q RMS uatizatio error: 1 RMS value of triagle wave 19 Quatizatio oise N-bit coverter: δ = V FSR N 0 CSE/EE

11 Quatizatio oise V Noise eergy: Q( RMS ) = Sigal eergy: V i ( RMS ) 1 δ δ / VQ δ / dv N Q = δ 1 SNR for ideal ADC: V SNR = 0 log( V i( RMS ) Q( RMS ) N SNR = 0log( = δ SNR = 6. 0 N [ db] ) 3 ) 1 Quatizatio oise V Noise eergy: Q( RMS ) = Sigal eergy: V i ( RMS ) 1 δ δ / VQ δ / dv N Q = δ 1 SNR for ideal ADC: V SNR = 0 log( V i( RMS ) Q( RMS ) N SNR = 0log( = δ SNR = 6. 0 N [ db] ) 3 ) CSE/EE

12 D/A coverters Easier to desig ad use tha A/ Ds Types Weighted curret source DAC R R DAC Multiplyig DAC Need to smooth the output 3 You will use DACs DAC specs are tricky! Check the errors Check the settlig Vedors use deceptive advertisig 16-bit DAC!!! But errors may give oly 1- bit accuracy You have to figure this out from the specs Datel Data Acuisitio ad Coversio Hadbook 4 CSE/EE 474 1

13 A/D coverters Hard to desig Cotai digital parts Ecoders FSMs May types Successive approximatio Flash Pipelied-flash Itegratig Sigma-delta Charge balaced Foldig Others 5 Example: Flash A/D Advatages Ultra-fast Disadvatages High power Low resolutio Metastability Sample/hold improves performace 6 CSE/EE

14 Example: Successive approximatio ADC Advatages Low power High resolutio Disadvatages Slow Problem: DAC must settle to LSB accuracy at every step Datel Data Acuisitio ad Coversio Hadbook 7 Samplig Quatizig a sigal 1) We sample it ) We ecode the samples Questios: How fast do we sample? How do we so this i hardware? What resolutio do we eed? Datel Data Acuisitio ad Coversio Hadbook 8 CSE/EE

15 Shao's samplig theorem If a cotiuous, bad-limited sigal cotais o freuecy compoets higher tha f c, the we ca recover the origial sigal without distortio if we sample at a rate of at least f c samples/ secod f c is called the Nyuist rate Real life Sample at.5f c or faster Sample clock should ot be coheret with the iput sigal 9 Freuecy domai aalysis Take the Fourier Trasform of the sigal Shows a sigal s freuecy compoets Udersampled freuecy compoets fold back! Datel Data Acuisitio ad Coversio Hadbook 30 CSE/EE

16 Samplig speed versus bit resolutio Hardware issues Samplig speed depeds o bit resolutio Thik time costats Examples: 8-bit resolutio takes 5.5τ 1-bit resolutio takes 8.3τ Settlig error t = e τ 16-bit resolutio takes 11τ Datel Data Acuisitio ad Coversio Hadbook 31 Nyuist Shao samplig theorem A theorem, developed by Harry Nyuist, ad prove by Claude Shao, which states that a aalog sigal waveform may be uiuely recostructed, without error, from samples take at eual time itervals. 3 CSE/EE

17 Nyuist Shao samplig theorem The samplig rate must be eual to, or greater tha, twice the highest freuecy compoet i the aalog sigal. Stated differetly: The highest freuecy which ca be accurately represeted is oe-half of the samplig rate. 33 Nyuist Theorem ad Aliasig Nyuist Theorem: We ca digitally represet oly freuecies up to half the samplig rate. Example: CD: SR=44,100 Hz Nyuist Freuecy = SR/ =,050 Hz Example: SR=,050 Hz Nyuist Freuecy = SR/ = 11,05 Hz 34 CSE/EE

18 Nyuist Theorem ad Aliasig Freuecies above Nyuist freuecy "fold over" to soud like lower freuecies. This foldover is called aliasig. Aliased freuecy f i rage [SR/, SR] becomes f': f' = f SR/ 35 Nyuist Theorem ad Aliasig f' = f - SR/ Example: SR = 0,000 Hz Nyuist Freuecy = 10,000 Hz f = 1,000 Hz --> f' = 8,000 Hz f = 18,000 Hz --> f' =,000 Hz f = 0,000 Hz --> f' = 0 Hz 36 CSE/EE

19 Nyuist Theorem ad Aliasig Graphical Example 1a: SR = 0,000 Hz Nyuist Freuecy = 10,000 Hz f =,500 Hz (o aliasig) 37 Nyuist Theorem ad Aliasig Graphical Example 1b: SR = 0,000 Hz Nyuist Freuecy = 10,000 Hz f = 5,000 Hz (o aliasig) (left ad right figures have same freuecy, but have differet samplig poits) 38 CSE/EE

20 Nyuist Theorem ad Aliasig Graphical Example : SR = 0,000 Hz Nyuist Freuecy = 10,000 Hz f = 10,000 Hz (o aliasig) 39 Nyuist Theorem ad Aliasig Graphical Example : BUT, if sample poits fall o zero-crossigs the soud is completely cacelled out 40 CSE/EE 474 0

21 Nyuist Theorem ad Aliasig Graphical Example 3: SR = 0,000 Hz Nyuist Freuecy = 10,000 Hz f = 1,500 Hz, f' = 7, Nyuist Theorem ad Aliasig Graphical Example 3: Fittig the simplest sie wave to the sampled poits gives a aliased waveform (dotted lie below): 4 CSE/EE 474 1

22 Method to reduce aliasig oise Iput voltage = V Use low pass filter to remove high freuecy before samplig e.g. Max fre =0KHz Gai(dB) 0-3dB cut off Low Pass Filter: f corer =0KHz ADC Samplig at 40KHz Fre. output code = : : : 43 CSE/EE 474