CP 405/EC 422 MODEL TEST PAPER - 1 PULSE & DIGITAL CIRCUITS. Time: Three Hours Maximum Marks: 100

Transcription

1 PULSE & DIGITAL CIRCUITS Time: Three Hours Maximum Marks: 0 Aswer five questios, takig ANY TWO from Group A, ay two from Group B ad all from Group C. All parts of a questio (a, b, etc. ) should be aswered at oe place. Aswer should be brief ad to-the-poit ad be supplemeted with eat sketches. Uecessary log aswer may result i loss of marks. Ay missig or wrog data may be assumed suitably givig proper justificatio. Figures o the right-had side margi idicate full marks. Group A 1. (a) Trasform the followig: 8 (i) (715) 8 = (-) (ii) (A0 1 = (-) (iii) (238) = (-) 1 (b) If X = 0 ad Y = 00011, fid (X Y) ad (Y X) usig (i) 1s complimet method (ii) 2s complimet method. Also give a desig to have X.Y where. shows a biary multiplicatio. (c) Covert the followig (i) X C AD ito SOP format (ii) Y ( A B ( A D) ito POS format. Also miimise the fuctio X + Y for Boolea X ad Y. 2. (a) What do you mea by uiversal gates? Name uiversal gates. Justify your aswer. Desig the logic A BC AC usig oly NAND gates. (b) Defie the followig: (i) Karaugh map (ii) Quie McClusky table (iii) Negative OR logic gate 8 1/5

2 (iv) Limitatios of Karaugh maps (c) Miimise the followig switchig fuctios usig Karaugh map. List all prime implicats ad essetial prime implicats (o redudat group). (i) F = (1, 3, 5,, 7) (ii) F = (0, 1, 3,, 14, 15) 3. (a) Defie the terms prime implemet, o prime implemet, essetial prime implicat ad o essetial prime implicat. (b) Implemet the fuctio f CD CD CD CD CD CD CD CD usig a 8 to 1 multiplexer with A, B ad D as select iputs. 4. (a) Desig a 4 to 1 multiplexer usig 2 x 1 multiplexers ad explai its fuctios. (b) What is ROM? How does it differ from RAM? Draw block diagram of ROM. Group B 5. (a) Write short ote o moostable multivibrator. (b) Covert the followig: (i) SR to J-K flip flop (ii) D to S-R flip flop (iii) J-K flip flop to T flip flop.. (a) State the basic differece betwee a Mealy ad a Moore model for represetig a state diagram. Use the example of a D flip flop to illustrate this. Also draw the related excitatio table. (b) Explai the followig terms: (i) Sychroous sequetial circuit (ii) Fiite state machie (ii) Icompletely specified machie (iii) Compatible states 2/5

3 7. (a) What are asychroous sequetial circuits ad their advatages? Draw the block diagram of such a circuit usig the basic model for the fudametal mode circuit ad explai its operatio with referece to stable ad ustable states. (b) Write otes o followig: (i) Determiistic recogisers (ii) Graphs (iii) Regular expressios 8. (a) What is the differece betwee sychroous ad asychroous couters. What are advatages of sychroous couter over asychroous couter? (b) Desig a asychroous mod 9 couter usig JK flip-flop. Group C 9. Aswer the followig i brief: 20 (i) A is (a) A (b) B (c) A + B (d) A B (ii) I x (iii) the value of x is 2 (a) 0.01 (b) 0. (c) 0.01 (d) 0.00 The caoical sum of product form of the fuctio F = A + B is (a) (b) + BA (c) (d) (iv) The caoical product of sum form of F ( A B)( B is 3/5

4 (a) ( A B ( A B (b) ( A B ( A B ( A B ( A B (c) ( A B ( A B ( A B (d) ( A B ( A B (v) (vi) The JK flip flop acts as a T flip flop whe (a) J =1, K = 0 (b) J = 0, K = 0 (c) J = 1, K = 1 (d) J = 0, K = 1 The state diagram of a asychroous sequetial circuit is show below. (vii) The umber of outputs of the circuit is (a) 2 (b) 4 (c) (d) 1 Multiplexer ca be expressed as (a) oe-to-may (b) may to oe (c) may to may (d) oe to oe (viii) Tabular method of simplificatio is coveiet as log as the umber the umber of variables does ot exceed (a) (b) 8 (c) (d) 12 (ix) The characteristic equatio of a T flip flop is 4/5

5 (x) (a) T Q (b) T Q (c) TQ (d) oe of these Hazards i switchig circuits are caused by (a) varyig iput sigal (b) costat output (c) zero propagatio time (d) delays of switchig compoets (Refer our course material for aswers) 5/5