Single Bit DACs in a Nutshell. Part I DAC Basics

Transcription

1 Sigle Bit DACs i a Nutshell Part I DAC Basics By Dave Va Ess, Pricipal Applicatio Egieer, Cypress Semicoductor May embedded applicatios require geeratig aalog outputs uder digital cotrol. It may be a DC referece voltage or a AC sigal to stimulate trasducers. It may be a recostructed voice sigal for some wireless applicatio. The applicatios are edless. This fuctio requires a Digital to Aalog Coverter or DAC. DACs are cool! They allow aalog sigals to be geerated uder CPU cotrol. The ame eve souds cool. DAC, the ame brigs up images of a Clive Clusser adveture. DAC Bit, ma of fiite resolutio! The umber of DACs o sigle chip systems is always limited, makig them a dear resource. Oe solutio is to use oboard digital resources ad firmware, alog with simple filters to build sigal bit DACs. This article will explai the cocept of sigle bit DACs, differet techiques to costruct them, ad the beefits ad cosequeces of each type. A DAC, i its simplest form, is circuitry to geerate a output that is percetage of a referece. A simple four bit implemetatio is show below. d 0 2 d 1 4 d 2 8 d 3 8 The followig equatio defies the output voltage d0vref d1vref d 2Vref d3vref V out (1) Figure 1. Four Bit DAC If it is acceptable to use the supply voltage as the referece, the the iput multiplexers ca be replaced with digital outputs from the MCU. This simplifies the desig to four digital output pis ad five resistors as show below. d 0 d 1 d 2 d Figure 2. atiometric Four Bit DAC

2 Whe the supply voltage is used as the referece it is kow as ratiometric. This may soud cool but it is just really just clever marketig! It makes ot havig a real referece soud like a feature. Who would wat buy a 10 Bit Serial Iput, No eal eferece DAC? Withi reaso, each extra bit of resolutio requires oly oe extra resistor ad a port pi to drive it. esistor tolerace is goig to become a problem. If implemeted with 1% resistors, resolutio is limited to about 6bits. Each added resistor is doubles the value of the previous resistor. The teth bit is At some poit the ratio of the resistors becomes impracticality large. This ca be solved usig the topology show below. d 0 2 d 1 d 2 d Figure Ladder Four Bit DAC This is called a 2 ladder. It has the advatage that the resistor ratio ever gets larger tha two. If the value is costructed with two parallel 2 resistors, the oly a sigle value of resistor is eeded. Geerally 1% resistors from the same reel hold a relative tolerace better tha ½%. This icreases the resolutio limit to 7bits but requires three resistors per bit. To be accurate this topology really should be called a ½ ladder DAC. However this was rejected, as some digital egieers could ot fathom the idea of a umber betwee zero ad oe. So far the DACs discussed geerate a particular ratio of the referece, 100% of the time. For example whe a 8bit DAC with a 5erece is set to 37 the output is 0.72V (5V * 37/256). Suppose istead of supplyig 14.5% of the referece 100% of the time, oe could supply 100% of the referece 14.5% of the time. Just such a topology is show below. DutyCycle C DutyCycle C Figure 4. Sigle bit ad atiometric Sigle bit DAC The output voltage is *DutyCycle. Agai, if it is acceptable to use the supply voltage as the referece, the the iput multiplexer ca be replaced by a sigle digital output from the MCU. This simplifies the desig to a sigle digital output pi ad a filter. These examples represet the filter as sigle pole C but the filterig could be the flywheel effect of a motor or the eye viewig a pulsed LED. Ay system compoet that has a slower respose tha the geerated output frequecy acts as the filter. What waveform is ideal for geeratig a duty cycle? Well this is the stuff thesis s are made of. There are may ways to geerate a duty cycle. Each has particular advatages. We ll close off this first sectio with the simplest method ad leave the more advaced techiques for the ext time. Pulse Width Modulator (PWM) Oe of the simplest ways to geerate a duty cycle is to use a PWM. May microcotrollers already are equipped with as least oe ad may i cases, several of them. A block diagram of a PWM is show below.

3 Dow Couter f Pulse Width egister A B Comparator A<B PWM out Figure 5. Pulse Width Modulator (PWM) Block Diagram The hardware cosisted of a dow couter with some Period ad a register to store a PulseWidth value. The comparator will go high wheever the couter s value is less the pulse width value. For a period of 256, the couter will cout from 255 dow to zero. If the pulse width value is 128 the the comparator output will be high whe the couter output is from 127 dow to zero, or 128 couts. The equatios for the duty cycle ad output frequecy are show below. dc PulseWidth Period f out f Period For PWMs, the output frequecy is idepedet of the pulse width. The plots below are for two PWMs. Figure 6. PWM Waveforms; 50% ad 14.5% Duty Cycle Both have a period of 256 ad iput of 1MHz, results i both havig a output frequecy of 3.9kHz. The top trace shows a PWM with its pulse width set to 128. This trace verifies that this is a 50% duty cycle. The bottom trace is for a PWM with a pulse width of 37. It has the same output frequecy but has a duty cycle of 14.5% (37/256). Agai the trace shows a sigal that is high about 1/7 th of the time. A spectral plot of the two sigals is show below. Figure 7. PWM Spectral Plots; 50% ad 14.5% Duty Cycle It is apparet that there are sigificat harmoics i these outputs. It will require filterig to remove them. Although relatively easy to build, PWMs suffer from sigificat harmoic geeratio that is at a relatively low frequecy. Give a costat frequecy, a PWM with fier resolutio (larger period) has a lower output

4 frequecy. The geeral solutio is to icreases the frequecy. The maximum operatig frequecy for the couter ad comparator limits the practical resolutio. We ll discuss several other techiques which get aroud these limitatios i the cocludig istallmet of this article. END PAT I Sigle Bit DACs i a Nutshell Part II Advaced Sigle-Bit DAC Techiques By Dave Va Ess, Pricipal Applicatio Egieer, Cypress Semicoductor I our first istallmet, DAC Basics (INSET LINK TO PAT I HEE), we explored how traditioal resistor ladder etworks ca be replaced with simpler sigle-bit ad ratiometric sigle bit DAC elemets ad how to drive them with a pulse width modulated (PWM) waveform. I this cocludig chapter, we ll look at three other ways to drive these etworks. Each will have example oscilloscope waveforms ad spectral plots for duty cycles of 50% ad 14.5%. Delta Sigma Modulatio (DSM) PWMs reduce the umber of trasitios to the smallest possible value. (Oe high ad oe low per couter cycle.) DSM is a techique that icreases the umber of trasitios to the largest possible value. For the same frequecy, the harmoics are pushed farther out makig it easier to filter them. A block diagram of a DSM is show below Accumulator DutyCycle egister A B Adder f Carry DSM out Figure 8. Delta Sigma Modulator (DSM) Block Diagram The duty cycle value is added to a accumulated value whe the adder overflows the output is high. For example, costatly addig 128 to a 8bit adder causes a carry every other time. Costatly addig 64 results i a carry oe i four times. Addig 63 results i a carry oe i four times, most of the time, but occasioally a carry oe i five times. The equatios for the duty cycle ad output frequecy are show below. dc DutyCycleValue AccumWidth f out dc f : dc 0.5 ( 1 dc) f : dc > 0. 5 The output frequecy is o loger set by the couter period. Idepedet of the adder width, f the duty cycle is limited to a rage of 10% to 90%, the output frequecy is guarateed to be o smaller tha 1/10 th the frequecy. The plots below are for two DSMs

5 Figure 9. DSM Waveforms; 50% ad 14.5% Duty Cycle Both have a adder width of 256 ad iput of 1MHz. The top trace shows a DSM with its DutyCycleValue set to 128. This results i a output with a 50% duty cycle ad a output frequecy of 500kHz. The bottom trace is for a DSM with its DutyCycleValue set to 37. This results i a output high oe part i seve most of the time, ad occasioally oe part i six, for a average output frequecy is 145kHz (1MHz*37/256). The geerated harmoics are pushed well past the 3.9kHz of the PWM example. A spectral plot of the two sigals show below cofirms this. Figure 10. DSM Spectral Plots; 50% ad 14.5% Duty Cycle Note that the frequecy compoets of the 37/256 duty cycle DMS is a mixture of 1MHz/6 ad 1MHz/7. (256/ ) Oe chief problem with this solutio is that o micro-cotroller comes with this type of hardware. It could be built with programmable logic or implemeted with software. The Cypress Semicoductor CY8C27443 programmable system o a chip has eight PWMs, each capable of ruig with a frequecy as high as 48MHz while usig zero CPU overhead. Implemetig a software DSM i the same device requires 100% of the CPU for a frequecy of 1MHz. Pseudo adom Modulatio (PM) PWMS is a variatio of pulse width modulatio where the dow couter is replaced with a pseudo radom couter. A block diagram of a PM is show below.

6 f Psuedo adom Couter A B Comparator A<B PM out DutyCycle egister Figure 11. Pseudo adom Modulator (PM) Block Diagram The comparator is still high wheever the couter is below the duty cycle value It just that the couter o loger couts liearly. The output is still high the same umber of couts it just that they are ow (pseudo) radomly dispersed withi the couter period. As with the delta sigma modulator the output frequecy is ot depedet o the couter period. The output frequecy is higher but ot as high as the DSM. The radom ature of the output keeps it frequecy to approximately half of what it would be for DSM. The equatios for the duty cycle ad output frequecy are show below. dc The plots below are for two PMs DutyCycleValue Period f out dc f : dc 0.5 ( 1 dc) f : dc > 0. 5 Figure 12. PM Waveforms; 50% ad 14.5% Duty Cycle Both have a couter width of 256 ad iput of 1MHz. The top trace shows a PM with its DutyCycleValue set to 128. This results i a very radom lookig output with a 50% average duty cycle ad a output frequecy of approximately 250kHz. The bottom trace is for a DSM with its DutyCycleValue set to 37. This results i a sigal that is high 14.5% of the time. Its output frequecy is aroud 172kHz. Beig early radom there is ot much harmoic cotet at ay particular frequecy. A spectral plot of the two sigals show below cofirms this.

7 Figure 13. PM Spectral Plots; 50% ad 14.5% Duty Cycle Although ot pushig the harmoic frequecies as high as DSM there are advatages to the radom ature of the output. Like the PWMs Cypress offers these types of modulators o their lie of Programmable Systems o a Chip. The PSoC CY8C27443 is capable of implemetig up to eight of these modulators. Dithered Pulse Width Modulators. (DPWM) So far three differet modulatio techiques have bee show. The secod ad third reduce the effects of harmoics by pushig tem up i frequecy makig them easier to remove. They do this by icreasig the output frequecy. This ca be a problem where there is cost to high frequecy switchig. It may be that the compoets caot switch above a certai frequecy or there is a eergy loss associated with switchig. (Battery Chargers are a good example. There is loss every time the power FET is switched.). A fourth optio is radomize the feedig a PWM. A block diagram of a DPWM is show below. f PM (dc PM ) Gate PWM (dc PWM ) DPWM out Figure 14. Dither Pulse Width Modulator (DPWM) Block Diagram Normally the output frequecy of a PWM is the divided by the period. 1MHz ig a 8 bit PWM has a output frequecy of 3.9kHz. Buildig a dither PWM requires usig the gate iput of the PWM. Whe the gate is high the PWM is eabled ad it geerates a output frequecy of 3.9kHz. Whe the gate is low the is disables ad the output frequecy is zero. If the gate iput has some duty cycle the the output is proportioal to it. The equatios for the duty cycle ad output frequecy are show below. DutyCycleValue PulseWidth PM PWM dc PM dcpwm fout PeriodPM PeriodPM dc PM f Period For a 2MHz ad a pseudo radom duty cycle of 50%, the eight-bit PWM has a average output frequecy of 3.9kHz (2MHz* ½*/256). It is average because the radom ature of the PM output causes a fluctuatio frequecy. For these particular parameter the chage i output frequecy is +/- 10%. This is show i the waveforms below. PWM Figure 15. DPWM Waveforms; 50% ad 14.5% Duty Cycle With this much frequecy shift the spectrum will o loger be harmoics at fixed frequecy. This dither effect smears them out over a wider area. This is show i the spectral plots below.

8 Figure 16. DPWM Spectral Plots; 50% ad 14.5% Duty Cycle Comparig these plots with those for a regular PWM (figure x) the peak harmoic oise is dow maybe 3dB. Ad the other harmoics are sigificatly reduced but it comes at the expese of a overall oise florr. Aother feature is that oly chagig the PM duty cycle allows for fie tuig of the average output frequecy. For example, the average output frequecy is 3.9kHz. Chagig the PM duty cycle to 64% shifts the average output frequecy to 5kHz DACs are precious resources that are frequetly completely used. It may become ecessary to fabricate your ow with o chip digital resources or firmware. Four examples of sigle bit DAC have bee show. The decisio o which to use is depedet o your uique system requiremets ad available resources.