Analysis and Optimization Design of Snubber Cricuit for Isolated DC-DC Converters in DC Power Grid

Transcription

1 Aalysis ad Optimizatio Desig of Subber Cricuit for Isolated DC-DC Coverters i DC Power Grid Koji Orikawa Nagaoka Uiversity of Techology Nagaoka, Japa orikawa@st.agaokaut.ac.jp Ju-ichi Itoh Nagaoka Uiversity of Techology Nagaoka, Japa itoh@vos.agaokaut.ac.jp Abstract This paper clarifies the priciple of the surge voltage i the diode rectifier that is coected to the trasformer i the isolated DC-DC coverter. I additio, the desig method of the RC ubber circuit is discussed by usig the equivalet circuit that is cosistig of the trasformer, the ubber circuit ad the diode. Fially, the experimetal results are provided to validate the desig method. Keywords-compoet; Smart grid; DC power grid; Isolated DC- DC coverters; Rectifier diode; Surge voltage; Subber circuit I. INTRODUCTION Recetly, the DC iterface coverters for the smart grid have attracted large attetios i commuity. The size ad efficiecy of high power DC-DC coverters become particularly importat especially for the photovoltaic geeratio ad battery storage system. O the other had, the developig of wide-gap semicoductor such as silico carbide (SiC) ad gallium itride (GaN), which is the high switchig frequecy semicoductor devices, have bee actively progressig. Therefore, packagig techologies for power coverters that feature small size ad high-desity are highly researchig [1]-[]. However, the occurrece of surge voltage durig high frequecy switchig i the semicoductor switchig devices is oe of the kow problems. The surge voltage iduces problems such as overvoltage ad high frequecy oises i the semicoductor switchig devices. As the result, breakdow ad malfuctio i the semicoductor switchig devices could be happe i the power coverters such as the high power DC-DC coverters for the smart grid. Therefore, the suppressio o the surge voltage is a importat aspect to study i order to offer high reliability i a power supply system. Isolated DC-DC coverters usig trasformers have bee studyig actively [3]. Because the trasformer ca isulate trasform voltage ito a AC voltage easily. The surge voltage geerally occurs i the output rectifier diodes that is coected to the output of trasformer. It is kow that the surge voltage i the output rectifier diode is caused by the leakage iductace of the trasformer, ad a parasitic capacitace of the diode. However, there have bee few quatitative discussios oly o the desig of the ubber circuit based o the priciple of the surge voltage i the diode [4]-[6]. As the result, the desig of the ubber circuit is basically depedig o the experieces of desigers. This paper clarifies the priciple of the surge voltage i the output diode rectifier that is coected to the isolated DC-DC coverters with cosideratio of the desig method i the RC uber circuit, which is coected to the secodary side of the trasformer. A theoretical equatio of the surge voltage is derived from the equivalet circuit. Subber circuit parameters are desiged based o a parasitic capacitace ad the power cosumptio of the ubber circuit. At the ed, the validity of the desig method is cofirmed from the experimetal results. II. PRINCIPLE OF SURGE VOLTAGE ON DIODE Fig. 1 shows a circuit diagram of the isolated DC-DC coverter which is ivestigated i this paper. This circuit cosists of a sigle phase iverter, a high frequecy trasformer, a diode rectifier ad a R load. I this experimet, the iverter is operated with the square waveform drive. A. Equivalet Circuit Fig. (a) shows the equivalet circuit whe the surge voltage occurs i the diode D 1 after the overlappig period durig commutatio from D 3 to D 1. The curret path is illustrated with a dot lie. R is a wirig resistace of the trasformer. L is a leakage iductace of the trasformer. Fig. (b) ad (c) show simulatio waveforms of Fig. (a). The value of wirig resistace ad leakage iductace of the primary side of the trasformer is coverted to the secodary side of the trasformer. I additio, the characteristic of the actual diode is demostrated with the ideal diode, o resistace R o, off resistace R, the forward voltage V F ad the parasitic capacitace C. The output curret caot chage rapidly because of a smooth iductace L out. As the result, the rush curret flows through the parasitic capacitace. I additio, the vibratioal curret flows through the leakage iductace which Figure 1. Full bridge isolated DC-DC coverter.

2 results the reverse electromotive voltage occurs i the leakage iductace. That is, the reverse electromotive voltage of the leakage iductace becomes the surge voltage. Therefore, the surge voltage does ot occur whe the ideal trasformer which has o leakage iductace is used. From the priciple which is metioed above, i order to reduce the surge voltage, it is eeded to suppress the rush curret i the parasitic capacitace. A eergy buffer is a effective method to suppress the rush curret i the parasitic capacitace. B. Theoretical Aalysis of Surge Voltage Theoretical equatio of the surge voltage is derived from the equivalet circuit as show i Fig. (a). Table 1 shows the coditios of the simulatio circuit. The theoretical equatio of the surge voltage is give by (1). τ /( fvib ) vd 1max = I str { 1+ e } VF. (1) where I st is the steady curret of the diode whe diode is tured off, τ is the dampig time costat ad f vib is the vibratioal frequecy of the surge voltage. I st, τ ad f vib are give by (), (3), (4). st { V I ( R + R )} ( R + R R ) I = / +. () se out Do Do { CRR + ( CR R )/ + L} /( LCR ) τ =. (3) Do ( R + R + R )/( LCR ) τ /( π ) f. (4) vib = Do where V se is the secodary side voltage of the trasformer ad I out is the output curret. From (1), it is cofirmed that the surge voltage depeds o (), (3) ad (4) which are chaged by the parameters; the wirig resistace, the leakage iductace ad the parasitic capacitace. I order to cofirm the validity of the equatios which are show i (1) ad (4) respectively, the calculatio results of (1) ad (4) are show i Fig. (3) ad Fig. (4) i the case that the leakage iductace L ad the parasitic capacitace C are chaged respectively. Fig. 3 shows the theoretical waveforms of the diode voltage ad the surge voltage i the case that the leakage iductace L is chaged. From Fig. 3, it is cofirmed that the vibratioal frequecy decreases ad the surge voltage is reduced accordig to icremet of the leakage iductace L. The reaso that the surge voltage reduced are follows; by icreasig the leakage iductace, the impedace of the series circuit which cosists of the leakage iductace ad the parasitic capacitace are icreased. As a result, the rush curret of the parasitic capacitace is reduced which also reduce the surge voltage. This meas the dampig time costat ad vibratioal frequecy that is show i (3) ad (4) are chaged, the the (a) Whe surge voltage occur i D 1. 5 V p.1 i D1 Fig. (a) -5 1 i D v D1 i D3 3 v D1-9.8 i L 15 i L v L 4 v L Fig. (c) Time ( s) Time ( s) (b) Voltage ad curret waveforms. (c) Elarged waveforms. Figure. Equivalet circuit of secodary part i Fig.1. TABLE I. CONDITIONS OF SIMULATION CIRCUIT Iput voltage V i 48 (V) Output curret source I out 1 (A) Output iductace L out.5 (mh) Output capacitace (μf) Switchig frequecy f sw (khz) Widig resistace R 53 (mω) Leakage iductace L 8.6 (μh) Tur ratio =N 1/N =15/6=.5 Parasitic capasitace C (pf) O resistace R Do.86 (Ω) Off resistace R 1 (kω) Forward voltage V F.86 (V) power of a expoetial i (1) will icrease by icreasig of the leakage iductace. As a result, the di L /dt of the leakage iductace curret decreases, ad the reverse electromotive voltage occurs i the leakage iductace is reduced. Therefore, the surge voltage is reduced. Fig. 4 shows theoretical waveforms of the diode voltage ad the surge voltage i the case that the parasitic capacitace C is chaged. From Fig. 4, it is cofirmed that the vibratioal frequecy decreases ad the surge voltage is reduced accordig to icremet of the parasitic capacitace C. This reaso is that the impedace of the series circuit which cosists of the

3 leakage iductace ad the parasitic capacitace are icrease. As a result, the rush curret of the parasitic capacitace becomes larger. That is the di L /dt of the leakage iductace curret icreases which result the reverse electromotive voltage occurs i the leakage iductace icreases. Therefore, the surge voltage icreases. III. SURGE VOLTAGE IN THE EXPERIMENT I order to cofirm the validity of the theoretical aalysis, the surge voltage i the diode of the prototype circuit is measured ad compared with the theoretical aalysis. (a) Voltage waveform of the diode. A. Chages of LeakageIiductace I this experimet, the air-core reactor which has same resistace but differet iductace, are coected to the secodary side of the trasformer i series. By usig this method, the dampig effect by the widig resistace R ca be eglected. The effect of the leakage iductace o the surge voltage oly ca be measured. Fig. 5(a) shows the experimetal waveforms cosists of the followig, the primary side voltage of the trasformer, the diode curret ad the diode voltage without the ubber circuit. After the primary side voltage of the trasformer chages from a positive value to a egative value, the overlappig period occurs i the commutatio. Also, it is cofirmed that the surge voltage occurs i the diode. Fig. 5(b) shows the waveforms of the diode curret ad diode voltage i the case that the leakage iductace L is chaged. From Fig. 5(b), it is see that the vibratioal frequecy ad the surge voltage decreases accordig to the icremet of the leakage iductace L. Fig. 6 shows the compariso betwee the theoretical ad experimetal values, which are subjected to the ratio betwee the surge voltage ad steady voltage. I the case of the experimet, the characteristic of the vibratioal frequecy ad the surge voltage are similar to the theoretical value. Therefore, the experimetal results ca cofirm that the ivestigatio i the equivalet circuit is valid. B. Chages of Parastic Capasitace I this experimet, the parasitic capacitace is chaged by coectig the capacitace to the diode i parallel. Fig. 5(c) shows the waveforms, the diode curret ad diode voltage i the case that the parasitic capacitace C is chaged. From Fig. 5(c), it ca be see that the vibratioal frequecy ad the surge voltage decreases accordig to icremet of the parasitic capacitace C. Fig. 7 shows the compariso betwee the theoretical ad experimetal values which are subjected to the ratio betwee the surge voltage ad steady voltage. I the case of the experimet, the characteristic of the vibratioal frequecy is similar to the theoretical value. O the other had, the characteristic of the surge voltage which is based o the theoretical is differet from the experimetal results as see i Fig. 7 (b). This reaso is that the capacitace which is coected to the diode i parallel ad its wirig resistace works as the ubber circuit. As a result, i cotrast to the Voltage (V) (b) Surge voltage of the diode. Figure. 3. Voltage waveforms ad surge voltage(l is variable). (a) Voltage waveform of the diode. (b) Surge voltage of the diode. Figure. 4. Voltage waveforms ad surge voltage (C is variable). theoretical aalysis, the surge voltage ca be suppressed i the experimet. I accordig to the cosideratios which are metioed above, the required coditios for suppressig the surge voltage by reducig the rush curret of the parasitic capacitace are show below. 1) Widig resistace of the trasformer : Large ) Leakage iductace of the trasformer : Large 3) Parasitic capacitace of the diode : Small However, i geeral the widig resistace of the trasformer is low i order to reduce the copper loss. The leakage iductace is also low except the applicatio which the leakage iductace is used i a positive way. Therefore, a trade-off relatioship that is subjected to reduce the surge voltage is established betwee i) to achieve a low wirig resistace ad ii) to achieve a low leakage iductace. O the other had, the parasitic capacitace depeds o the ratig of the voltage ad curret. Therefore, it is difficult to always select the diode which has a small parasitic capacitace.

4 Frequecy fvib (MHz) (a) Voltage ad curret waveform (L:8.6μH, C:pF). (a) Vibratioal frequecy as a fuctio of the leakage iductace. (b) Elarged waveform of Fig. 5 (a) (L:8.6μH, C:pF). (b) Ratio betwee surge voltage ad steady voltage. Figure. 6. Theoretical value ad experimetal value of the surge voltage ad the vibratioal frequecy (L is variable). (I D1 ) (V D1 ) (c) Elarged voltage ad curret waveform (L:15.9μH, C:pF). I D1 (ma) R: 53(m ) L: 8.6( H) I out : 1(A) V D1 5(V) (s) (d) Elarged voltage ad curret waveform (L:8.6μH, C:pF). Figure. 5.Experimetal waveforms. IV. DESIGN METHOD OF SNUBBER CIRCUIT As metioed above, there are limitatios to suppress the surge voltage by reducig the rush curret of the parasitic capacitor from the desig of trasformer ad selectio of diode. Therefore, the ubber circuit is coected to the diode i parallel. It cosists of the ubber resistace ad the ubber capacitace which has a larger value tha that of the parasitic capacitace. By usig the ubber circuit, the surge voltage ca be reduced by reducig the rush curret of the parasitic capacitace. This paper describes the desig of a RC ubber circuit which is coected to the secodary side of the trasformer. Fig. 8 shows the equivalet circuit of Fig. (a) i case that the commo ubber circuit is coected to the secodary side of the trasformer. The ubber circuit is desiged based o Fig. 8. I particular, Fig. 8 is divided ito two parts: the dotted lie regio which cosists of the trasformer ad the ubber circuit ad the equivalet circuit of the diode. Firstly, the peak Frequecy fvib (MHz) VD1max/Vst (a) Vibratioal frequecy as a fuctio of the parasitic capacitace Experimetal value ( ) Theoretical value( ) No surge voltage lie R: 53(m ) L: 8.6( H) Parasitic capacitace C (pf) (b) Ratio betwee surge voltage ad steady voltage. Figure. 7. Theoretical value ad experimetal value of the surge voltage ad the vibratioal frequecy(c is variable). value of the step respose i the dotted lie circuit is calculated. After that, subtractig the voltage drop of the diode from it, these calculatio results become the desiged value of the surge voltage V D1max. The coefficiet that the desiged value of the surge voltage divided by the steady voltage V st is give by (5). k [ 1+ e ]/ Vst ( I out RDo VF ) Vst V /. (5) D1 max / Vst = Vse + where V st is the steady voltage, k is a costat value. k is give by (6).

5 ( ) ζ 1 4ζ ( ) 1 ζ 1 ta + π 3 4ζ ζ ζ 1 1 k = ta (6) 1 ζ ζ From (5), the surge voltage will be determied i case that the output curret ad the parameters of the diode are kow. I additio, the relatioship amog the ubber resistace R, the ubber capacitace C ad the dampig coefficiet ξ are give by (7). R = ζ L /. (7) C From (7), the ubber resistace R ca be desiged after the ubber capacitace C is determied. However, the umber of the combiatio of two parameters is ifiity. I this sectio, C is desiged based o the relatioship amog the ubber capacitace, the parasitic capacitace ad the ubber loss. I the ed, R is desiged usig by (7). I the case of the smaller ubber capacitace, the impedace of the ubber circuit icreases, which results the ubber circuit does ot work. Therefore, the ubber circuit caot suppress the surge voltage. O the other had, i case of the larger ubber capacitace, the impedace of the ubber circuit decreases. As a result, the ubber circuit ca suppress the surge voltage. However, the ubber curret ad the power cosumptio of the ubber circuit icreases. Therefore, the optimum value of the ubber capacitace eeds to be idetified accordig to the parasitic capacitace. The power cosumptio of the ubber circuit P is give by (1) i the case that the dotted lie regio oly is cosidered i Fig. 8. Figure. 8. Equivalet circuit of the trasformer with the RC ubber circuit. Iput Start Eq. (5),(6) V D1max I out R Do V F C L P a C R P Eq. (7) Eq. (8) P < P a Yes Ed No Figure. 9. Flowchart for desig of ubber circuit. C :Decreased P R = R ( 1 ω / ω ) + ( ω / ω )( R / R ) ω / ω V ( ω ) (8) se where ω is a -order atural agular frequecy of the secodry side voltage i the trasormer. ω ad R are give by (9), (1). (a) C/C =1-3. ω = 1/ LC (9) R L / C = (1) Fig. 9 shows a flowchart of the ubber circuit desig. Required parameters for the desig of the ubber circuit are desiged surge voltage V D1max, the output curret I out, o resistace R Do, the forward voltage V F, the parasitic capacitace C, the leakage iductace L ad a allowace ubber loss P a. First, the dampig coefficiet ζ is decided by parameters which are metioed above. The, the ubber resistace R is calculated by (7). I the ed, if a calculated ubber loss P is less tha the allowace ubber loss, the the desig of the ubber circuit is completed. V. EXPERIMENTAL RESULTS WITH SNUBER CIRCUIT Fig. 1 shows waveforms, the diode voltage ad the curret of the ubber circuit i the case that the ratio betwee the (b) C/C =3 1 - Figure. 1. Waveforms of the diode ad the curret of the ubber. parasitic capacitace ad the ubber capacitace is chaged uder a costat dampig coefficiet. It ca be see that the surge voltage is almost same ad the curret of the ubber circuit icrease accordig to the icremet of the parasitic capacitace. Therefore, it is cofirmed that the experimetal results is well agreed with the theoretical aalysis which are metioed i the chapter IV. Fig. 11(a) shows the desiged value, the simulatio results, ad the experimetal results i terms of the ratio betwee the surge voltage ad steady voltage of the diode. Fig. 11(b) shows

6 VD1max/Vst (a) With RC ubber (ζ:.1). (a) Ratio betwee surge voltage ad steady voltage. (b) With RC ubber (ζ:.8). Figure. 1. Voltage waveforms of the diode without ubber ad with ubber usig desiged parameter. (b) Subber loss. Figure. 11. Ratio betwee surge voltage ad steady voltage ad ubber loss as a fuctio of ratio betwee parasitic capacitace ad ubber capacitace. the calculatio result which is obtaied by (8), the simulatio result is obtaied by addig the RC ubber circuit to Fig. (a), ad the experimetal result is obtaied from Fig. 1 i terms of the power cosumptio of the ubber circuit. From Fig. 11(a), it is cofirmed that the ubber capacitace should be desiged from 1 to 3 times larger tha the parasitic capacitace. I additio, it is see that the calculatio result is larger tha the simulatio result. I other words, the worst case of the power cosumptio of the ubber circuit ca be calculated by usig (8) Fig. 1 shows the experimetal waveform with ubber circuit i the case that C/C =.3. From Fig. 1, it is cofirmed that surge voltage is suppressed below tha the desiged value. Fig. 13 shows the compariso betwee the desiged ad experimetal values that are subjected to the ratio betwee the surge voltage ad steady voltage. From Fig. 13, it is cofirmed the tedecy of the desiged ad experimetal values is closed. VI. CONCLUSION This paper clarifies the priciple of the surge voltage o the diode i the isolated DC-DC coverter ad also the desig method of the ubber circuit that is coected to the secodary side of the trasformer. It is cofirmed that the surge voltage depeds o the wirig resistace, the leakage iductace ad the parasitic capacitace, based o the experimetal results obtaied from the equivalet circuit. I additio, it is cofirmed that the surge voltage is suppressed VD1max/Vst Figure. 13. Ratio betwee the surge voltage ad the steady voltage. below the desiged value with the ubber circuit which has a low ubber loss. I the ed, the validity of the aalysis results, which is based o the equivalet circuit, has bee cofirmed by experimetal results. REFERENCES [1] J. Kodoh, T. Yatsuo, I. Ishii, K. Arai : Estimatio of Coverters with SiC Devices for Distributio Networks, IEEJ Trasactio o Idustry Applicatios, Vol.16, No.4, pp (6) [] Biela, J.; Aggeler, D.; Ioue, S.; Akagi, H.; Kolar, J.W. : Bi-Directioal Isolated DC-DC Coverter for Nexr-Geeratio Power Distributio- Compariso of Coverters Usig Si ad SiC Devices, IEEJ Trasactio o Idustry Applicatios, Vol.18, No.7, pp (8) [3] Simajorag, R.; Yamaguchi, H.; Ohashi, H.; Takeda, T.; Yamazaki, M.; Murai, H. : Low Cost Trasformer Isolated Boost Half-bridge Micro-iverter for Sigle-phase Grid-coected Photovoltaic System, Applied Power Electroics Coferece ad Expositio (APEC) 1, pp (1) [4] M. Hirokawa, T. Niomiya: No-Dissipative Subber for Rectifyig Diodes i a High-Power DC-DC Coverter, T.IEEJapa, Vol. 15-D, No. 4, pp (5) (i Japaese) [5] D. Yoshitomi, J. Itoh, K. Hirachi: Relatioship betwee Leakage Iductace ad Surge Voltage o Isolated DC-DC Coverter, Japa Istitute of Power Electroics, JIPE-37-3 (11) (i Japaese) [6] Cacciato, M.; Cosoli, A. : New Regeerative Active Subber Circuit for ZVS Phase Shift Full Bridge Coverter, Applied Power Electroics Coferece ad Expositio (APEC) 11, pp (11)