Reducing Power Dissipation in Complex Digital Filters by using the Quadratic Residue Number System Λ

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1 Reducig Power Dissipatio i Complex Digital Filters by usig the Quadratic Residue Number System Λ Agelo D Amora, Alberto Naarelli, Marco Re ad Gia Carlo Cardarilli Departmet of Electrical Egieerig Uiversity of Rome Tor Vergata - Italy Abstract The aim of this work is to compare i terms of performace, area ad power dissipatio, a complex FIR filter realized i the traditioal two s complemet system with a Quadratic Residue Number System (QRNS) based oe. The resultig implemetatios, desiged to work at the same clock rate, show that the QRNS filter is almost half the size of the traditioal oe, ad dissipates about oe third of the eergy. 1 Itroductio The ew geeratio of telecommuicatio equipmet ofte require the use of high order FIR filters for the implemetatio of the ew modulatio schemes. Moreover, low power cosumptio for ew portable multimedia termials is eeded. I this cotext, computatioal itesive sigal processig blocks ca be effectively implemeted by usig Residue Number System (RNS) arithmetic. The use of the RNS allows the decompositio of a give dyamic rage i slices of smaller rage o which the computatio ca be efficietly implemeted i parallel [1], [2], [3]. The QRNS (Quadratic RNS) is particularly coveiet whe dealig with complex umbers [4] [5]. I QRNS the imagiary term of a complex umber is trasformed ito a iteger, therefore a complex multiplicatio which requires four itegers multiplicatios ad two sums i the covetioal two s complemet system, is implemeted with two iteger multiplicatios i QRNS. The drawback preseted by the RNS (ad QRNS) is the overhead due to both iput ad output coversios biary- Λ 34th Asilomar Coferece o Sigals, Systems, ad Computers, Asilomar Hotel ad Coferece Grouds, Pacific Grove, CA, USA. Oct Nov. 1, RNS-biary. This problem ca be solved by usig efficiet coversio techiques [6] [7], or by covertig directly the aalog sigal i the residue represetatio [8]. Recetly, a umber of works o low power ad RNS have bee preseted. I [9] ad [10] the power dissipatio is reduced by takig advatage of the speed-up due to the parallelism of the RNS structure. The supply voltage is reduced, resultig i a quadratic reductio of power, util the speed-up =1[9], or util the desired value of delay [10]. I [11] some ecodig optimizatio techiques for small moduli are preseted. I our work, we compare the performace, area ad power of a complex FIR filter realized with the traditioal biary arithmetic, with a QRNS based oe. Both filters have bee desiged accordig to the specificatios of a actual filter used i a telecommuicatio satellite ad are clocked at the same rate of 166 MHz. Although the QRNS filter has a loger latecy, it ca sustai the same throughput of the traditioal oe, while its area ad power dissipatio are about 57% of the total area ad 34% of the total power of the traditioal filter. 2 Backgroud A Residue Number System is defied by a set of relatively prime itegers fm1;m2;:::;m P g : The dyamic rage of the system is give by the product of all the moduli m i : M = m1 m2 ::: m P : Ay iteger X 2f0; 1; 2;:::m 1g has a uique RNS represetatio give by: X RNS! ( hxi m1 ; hxi m2 ;:::;hxi mp )

2 where hxi mi deotes the operatio X mod m i. Operatios o sigle moduli are doe i parallel Z = XopY RNS! 8>< >: Z m1 = hx m1 op Y m1 i m1 Z m2 = hx m2 op Y m2 i m2 ::: ::: ::: Z mp = hx mp op Y mp i mp The coversio of the RNS represetatio of Z ca be accomplished by the Chiese Remaider Theorem (CRT): Z =* P X i=0 m i hm 1 i imi Z mi M with m i = M m i ad m 1 i obtaied by hmi m 1 i imi =1. I the complex case, we ca trasform the imagiary term ito a iteger if the equatio q 2 1=0 has two distict roots q1 ad q2 i the rig of itegers modulo m i (Z mi ). A complex umber x R jx I =(x R ;x I ) 2 Z mi, with q root of q 2 1=0 i Z mi has a uique Quadratic Residue Number System represetatio give by (x R ;x I ) QRNS! (X i ; ^X i ) i =0; 1;:::;P X i = hx R g x I i mi ^X i = hx R g x I i mi The iverse QRNS trasformatio is give by x R = h2 1 (X i ^X i )i mi x I = h2 1 q 1 (X i ^X i )i mi where 2 1 ad q 1 are the multiplicative iverses of 2 ad q, respectively, modulo m i : h2 2 1 i mi =1 ad hq q 1 i mi =1: Moreover, it ca be proved that for all the prime itegers which satisfy p =4k 1 k 2 N the equatio q 2 1=0has two distict roots q1 ad q2. As a cosequece, the product of two complex umbers x R jx I ad y R jy I is i QRNS (x R jx I )(y R jy I ) QRNS! (hx i Y i i mi ; h ^X i ^Y i i mi ) ad it is realized by usig two itegers multiplicatios istead of four. Table 1 shows a example of QRNS multiplicatio i the rig modulo 13. A complex N taps FIR filter (Figure 1) is expressed by NX y() = a k x( k) k=0 where x;y;a k deotes complex quatities. From the QRNS theory described above, it is easy to derive for the complex filter the structure show i Figure 2, i which both portios of the filter are realized with P RNS filters workig i parallel. example for m =13: q = q1 =5$h5 5i13 = 1 (x R jx I )(y R jy I )=(3j)(2 j2) = 4 j8 coversio to QRNS X = h3 5 1i13 =8 Y = h2 5 2i13 =12 ^X = h3 5 1i13 =11 ^Y = h2 5 2i13 =5 multiplicatios X Y = h8 12i13 =5 ^X ^Y = h11 5i13 =3 coversio from QRNS Z R = h7(5 3)i13 =4 beig 2 1 =7 Z I = h7 8(5 3)i13 =8 beig q 1 =8 Table 1. Example of QRNS multiplicatio mod 13. x(t) a 0 a 1 a 1 a Figure 1. FIR filter i direct form. 3 Traditioal FIR Filter The startig poit of our desig is a programmable 64- tap FIR filter realized i direct form (Figure 1) with complex iput ad coefficiets size of 10 bits for the real part ad 10 bits for the imagiary part. These data are derived from the specificatio of a actual digital filter, used aboard a satellite for direct TV broadcastig. We desiged a prototype filter i traditioal two s complemet system i order to compare its performace, area ad power dissipatio with a QRNS filter. The filter ca be decomposed i a real ad imagiary part. A sigle tap is realized as sketched i Figure 3. The real ad imagiary products are realized with two Booth multipliers [12] ad the resultig partial products are accumulated i a Wallace s tree structure which produces a carry-save (CS) represetatio of the product i each side x(t) _ bi to QRNS X X^ RNS FIR filter RNS FIR filter Y Y^ QRNS to bi Figure 2. Structure of QRNS filter. y(t) y(t) _

3 of the filter. The CS represetatio of the products, is the accumulated i two 128-added Wallace s tree realized with 4:2 compressors [13], ot depicted i Figure 3. To have a error-free filter we must keep a umber of bits sufficiet to hold the carry-save represetatio of the sum, ad we eed a 20 log2 64 wide tree. The carry-save represetatio is fially coverted ito two s complemet represetatio by a carry-propagate adder (realized with a carry-look-ahead scheme) i the last stage of the filter (both real ad imagiary sides). The filter has bee implemeted i the AMS 0:35μm stadard cells library, ad it was sythesized from VHDL descriptio usig Syopsys ad a costrait of 6 s as a critical path, for this reaso it resulted i a pipelied filter of 6 stages. x RE a IM Imagiary tree a RE x IM 4 QRNS FIR Filter a RE a IM From Figure 2 we ca see that the QRNS filter ca be realized by two RNS filters i parallel. Each RNS filter is the decomposed ito P filters workig i parallel, where P is the umber of moduli used i the RNS represetatio. I additio, the RNS filter requires both biary to QRNS ad QRNS to biary coverters. I order to have a dyamic rage of 20 bits, as i the case of the traditioal implemetatio, we chose the followig set of moduli: m i = f5; 13; 17; 29; 41g Real tree Figure 3. Structure of tap i traditioal complex FIR filter. such that log2( ) = 20:3 : where 4.1 Implemetatio of modular multiplicatio I each tap, a modular multiplier is eeded to compute the term ha k x( k)i mi. Because of the complexity of modular multiplicatio, we used the isomorphism techique [14] to implemet the product of residues. By usig isomorphism, the product of the two residues is trasformed ito the sum of their idices which are obtaied by a isomorphic trasformatio. Accordig to [14], if m is prime there exists a primitive radix r such that its powers modulo m cover the set [1;m 1]: i = hr wi i m with i 2 [1;m 1] w i 2 [0;m 2]: Both trasformatios! w ad w! ca be implemeted with m 1 etries tables. Therefore, the product of a1 ad a2 modulo m ca be obtaied as: ha1 a2i m = hr w i m w = hw1 w2i m 1 with a1 = hr w1 i m a2 = hr w2 i m I order to implemet the modular multiplicatio the followig operatios are performed: i) Two isomorphic trasformatios to obtai w1 ad w2; ii) Oe modulo m 1 additio hw1 w2i m 1; iii) Oe iverse isomorphic trasformatios to obtai the product. For example, for the modular multiplicatio we have (r =2): h3 4i5 =2 i) 3=h2 3 i5! w1 =3 4=h2 2 i5! w2 =2 ii) h2 3i4 =1 iii) h2 1 i5 =2

4 w 1 w 2 m a 1 a 2 detect 0 adder mod (m 1) i detect 0 carry save adder iv. isomorphism bit adder bit adder a x a 1 2 Figure 4. Multiplicatio implemeted by isomorphism. MSB m u x Figure 5. Adder modulo m. The iput x, although delayed, is the multiplicad of all the multiplicatios (see Figure 1). For this reaso oly oe isomorphic trasformatio, icorporated i the biary to QRNS coversio, is ecessary for all the taps. O the other had, because the coefficiets of the filter (multiplicators) are costat terms loaded oce at start-up, it is coveiet to load directly the isomorphic represetatio modulo m i 1. As a result, i each tap, we reduce the modular multiplicatio to a modular additio followed by a access to table (iverse isomorphism) as depicted i Figure 4. The table is implemeted as sythesized logic ad special attetio has to be paid whe oe of the two operads is zero. I this case, there exists o isomorphic correspodece ad the modular adder has to be bypassed. 4.2 Implemetatio of modular additio The modular additio ha1 a2i m, cosists of two biary additios. If the result of a1 a2 exceeds the modulo (it is larger tha m 1), we have to subtract the modulo m. I order to speed-up the operatio we ca execute i parallel the two operatios: (a1 a2) ad (a1 a2 m): If the sig of the three-term additio is egative it meas tha the sum (a1 a2) <m ad the modular sum is a1 a2, otherwise the modular additio is the result of the three-term additio. The above algorithm ca be implemeted with two dlog2 me-bit adders as show i Figure 5. At the output of the tree, it is ecessary to reduce the sum S of all the taps to hsi mi. This is doe with the moduloreductio techique described i [6]. 4.3 Implemetatio of iput/output coversios As already metioed, the iput coversio block icludes the isomorphic trasformatio. If x is zero, there is o expoet w such that hr w i mi =0. As a cosequece, zero is ecoded with a special patter that is the detected i the block which computes the product usig the isomorphism (Figure 4). The output coversio is implemeted by usig the Chiese Remaider Theorem (CRT), as described i [6]. 5 Results ad Comparisos Both the traditioal ad the QRNS filters were implemeted i the AMS 0:35μm stadard cells library. Delay, area ad power dissipatio have bee determied with Syopsys tools. Table 2 summarizes the results. I the table, area is reported as umber of NAND2 equivalet gates ad power is computed at 166 MHz. However, both area ad power dissipatio do ot take ito accout the cotributio of itercoectios. Table 2 shows that the QRNS filter has a higher latecy, due to the coversios, but it ca be clocked at the same rate of the traditioal filter, ad cosequetly, it ca sustai the same throughput. However, the QRNS filter is almost half the area o the traditioal complex filter, ad cosumes oe third of the eergy. 6 Coclusios We have implemeted a QRNS 64-taps FIR filter ad compared its delay, area ad power dissipatio with those of

5 Filter Cycle Latecy Area Power [s] (cycles) (gate equiv.) [W ] QRNS ; 400 2:5 Trad ; 700 7:4 ratio Table 2. Summary of results. a correspodig complex FIR filter realized with the traditioal two s complemet system. The results obtaied show that the QRNS filter ca sustai the same clock rate, although it has a slightly loger latecy. However, i terms of area ad power the QRNS versio is more coveiet. A better improvemet is expected for filters with a larger umber of taps. Ackowledgemets This work was partially supported by MURST Natioal Project: Codesig Methods for Low Power Itegrated Circuits. Refereces [1] N.S. Szabo ad R.I. Taaka. Residue Arithmetic ad its Applicatios i Computer Techology. New York: McGraw-Hill, [2] M.A. Sodestrad, W.K. Jekis, G. A. Jullie, ad F. J. Taylor. Residue Number System Arithmetic: Moder Applicatios i Digital Sigal Processig. New York: IEEE Press, [7] G. Cardarilli, M. Re, R. Lojacoo, ad G. Ferri. A ew efficiet architecture for biary to rs coversio. Proc. of Europea Coferece o Circuit Theory ad Desig (ECCTD 99), Vol. 2: , [8] A.P. Preethy ad D. Radhakrisha. A vlsi architecture for aalog-to-residue coversio. Third Iteratioal Coferece o Advaced A/D ad D/A Coversio Techiques ad Their Applicatios, pages 83 85, [9] M. Bhardwaj ad A. Balaram. Low power sigal processig architectures usig residue arithmetic. Proceedigs of IEEE Iteratioal Coferece o Acoustics, Speech ad Sigal Processig (ASSP 98), Vol. 5: , [10] W.L. Frekig ad K.K. Parhi. Low-power digital filters usig residue arithmetic. Thirty-First Asilomar Coferece o Sigals, Systems ad Computers, Vol. 1: , [11] M.N. Mahesh ad M. Mehdale. Low power realizatio of residue umber system based fir filters. Thirteeth Iteratioal Coferece o VLSI Desig, pages 30 33, [12] Israel Kore. Computer Arithmetic Algorithms. Pretice-Hall, Ic., [13] M.D. Ercegovac ad T. Lag. Divisio ad Square Root: Digit-Recurrece Algorithms ad Implemetatios. Kluwer Academic Publisher, [14] I.M. Viogradov. A Itroductio to the Theory of Numbers. New York: Pergamo Press, [3] M.A. Soderstrad ad K.Al Marayati. Vlsi implemetatio of very high-order fir filters. IEEE Iteratioal Symposium o Circuits ad Systems (ISCAS 95), Vol. 2: , [4] F. J. Taylor, G. Papadourakis, A. Skavatzos, ad A. Stouraitis. A radix-4 FFT usig complex RNS arithmetic. IEEE Trasactios o Computers, Vol. C- 34: , Jue [5] M. Abdallah ad A. Skavatzos. O the biary quadratic residue system with ocoprime moduli. IEEE Trasactios o Sigal Processig, Vol. 45: , Aug [6] G. Cardarilli, M. Re, ad R. Lojacoo. A residue to biary coversio algorithm for siged umbers. Europea Coferece o Circuit Theory ad Desig (EC- CTD 97), Vol. 3: , 1997.