-RESEARCH ARTICLE- The impact transconductance parameter and threshold voltage of MOSFET s in static characteristics of CMOS inverter

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1 NEScieces, 2017, 2 (3): RESEARCH ARTICLE- The imact trascoductace arameter ad threshold voltage of MOSFET s i static characteristics of CMOS iverter Milaim Zabeli 1, Nebi Caa 1, Myzafere Limai 1, Qamil Kabashi 1* 1 Faculty of Electrical ad Comuter Egieerig, Uiversity of Prishtia, Prishtia, Kosovo Abstract The objective of this aer is to research the imact of electrical ad hysical arameters that characterize the comlemetary MOSFET trasistors (NMOS ad PMOS trasistors) i the CMOS iverter for static mode of oeratio. I additio to this, the aer also aims at exlorig the directives that are to be followed durig the desig hase of the CMOS iverters that eable desigers to desig the CMOS iverters with the best ossible erformace, deedig o oeratio coditios. The CMOS iverter desiged with the best ossible features also eables the desigig of the CMOS logic circuits with the best ossible erformace, accordig to the oeratio coditios ad desigers requiremets. Keywords: CMOS iverter, threshold voltage, voltage critical value, oise margis, trascoductace arameter. Article history: Received 25 Setember 2017, Acceted 13 November 2017, Available olie 14 November 2017 Itroductio CMOS logic circuits rereset the family of logic circuits which are the most oular techology for the imlemetatio of digital circuits, or digital systems. The small dimesios, low ower of dissiatio ad ease of fabricatio eable extremely high levels of itegratio (or circuits acig desities) i digital systems (Ludager, Zeiali, Tohidi, Madse, & Moradi, 2016; Pal, 2015; Plummer, Deal, & Griffi, 2009; Zat, 2014; Salma & Friedma, 2012). By oise margis, CMOS techology is the domiat of all the IC techologies available for digital circuits desig. The fudametal circuit of CMOS logic circuit is the CMOS iverter. Electrical ad hysical arameters that characterize the comlemetary MOS trasistors (or * Corresodig Author: Qamil Kabashi, qamil.abashi@ui-r.edu

2 Natural ad Egieerig Scieces 136 comlemetary MOSFET trasistors) determie the behavior of CMOS iverter, as for static coditios of oeratio, as well as dyamic coditios of oeratio (Kag & Leblebici, 2016; Sedra & Smith, 2015; Caa, Zabeli, Limai, & Kabashi, 2010; Karl, et al., 2013). The CMOS iverter cosists of two comlemetary MOS trasistors (of a ehacemettye NMOS trasistor ad a ehacemet-tye PMOS trasistor, because the ehacemet-tye of MOSFETs have high erformace o deletio- tye of MOSFETs), itercoected as i Figure 1 (Kag & Leblebici, 2016; Taur & Nig, 2013). The NMOS trasistor is called ull-dow trasistor, while the PMOS trasistor is called ull-u trasistor (Rai & Latha, 2016). Comlemetary MOS trasistors i the CMOS iverter oerates i comlemetary mode deedig o voltage level alied to the iut termial (to the gates of MOS trasistors). I the CMOS iverter, the cotributio of both MOS trasistors is equal to the circuit oeratio characteristics, therefore both trasistors are cosidered as driver trasistors. By circuit toology for iut high voltage (high level), the NMOS trasistor drives (ulls dow) the outut ode while the PMOS trasistor acts as the load (oliear resistor), ad for iut low voltage (low level) the PMOS trasistor drives (ulls u) the outut ode while the NMOS acts as load (Kag & Leblebici, 2016; Sedra & Smith, 2015; Baer, 2010). It s very imortat that the CMOS iverter has the static ower of dissiatio early zero, whe the subthreshold coductios ad leaage currets are eglected (Sedra & Smith, 2015; Baer, 2010; Weste & Harris, 2011; Zhag, Huag, Zhag, Li, & Yoshihara, 2013; Uddi, Nordi, Reaz, & Bhuiya, 2013). Figure 1. The structure of the CMOS iverter which cotais two comlemetary ehacemet-tye MOS trasistors. The role of the comlemetary MOSFET (NMOS ad PMOS) trasistors arameters i characteristic roerties of the CMOS iverters The behavior of the CMOS iverter for static coditios of oeratio is described by the voltage trasfer characteristic (TC), ad for dyamic oeratio coditios is described by the time resose durig switchig coductios (Kag & Leblebici, 2016; Sedra & Smith, 2015). The tyical TC of the CMOS iverter is show as i Figure 2. I the CMOS iverter, the NMOS trasistor ad PMOS trasistor ca be treated as a switch which oerates i comlemetary mode (Baer, 2010). For costructio of the TC of the CMOS iverter, five differet combiatios of oeratio modes of the NMOS ad PMOS trasistors should be examied, which are the results of the various

3 Natural ad Egieerig Scieces 137 ratios of the iut voltage levels ad the outut voltage levels. Oeratio modes of comlemetary MOS trasistors withi articular regios of the TC are reseted i Table 1. The characteristic roerties that characterize the TC are some voltage critical values at the iut ad outut termial of the CMOS iverter, as: OH, OL, IL, IH, th (Kag & Leblebici, 2016; Sedra & Smith, 2015). Figure 2. The tyical TC of the CMOS iverter. Table 1. Oeratio modes of comlemetary MOS trasistors (NMOS ad PMOS trasistors) Regio i o NMOS PMOS A B C D E < to, IL th IH > (DD+to,) OH OH th OL OL cut-off saturatio saturatio liear liear Liear liear saturatio saturatio cut-off OH outut high voltage whe outut level is a logic 1 (high logic level), OL outut low voltage whe outut level is a logic 0 (low logic level), IL maximum iut voltage which ca be iterreted as logic 0, IH miimum iut voltage which ca be iterreted as logic 1. The voltage critical values at iut ad outut of the CMOS iverter are determied by usig combiatios of oeratio regios (oeratio modes) of the NMOS trasistor ad the PMOS trasistor, deedig o the level of the outut voltage values relative to the voltage values at the iut of the CMOS iverter.

4 Natural ad Egieerig Scieces 138 The critical value of outut voltage OH ca be calculated by usig the A regio of TC s, whe the NMOS trasistor oerates i the cut-off mode, while the PMOS trasistor oerates i the liear mode, ad after calculatio will have voltage level of: OH DD whe DD ower suly voltage (source voltage). (1) By usig the B regio of the TC, the defiitio for IL critical value (the smaller of the two iut voltage value at which the sloe of the TC becomes do/di= -1) ad the oeratio modes of comlemetary MOS trasistors accordig to Table 1 (the NMOS trasistor oerates i saturatio mode, while the PMOS trasistors oerates liear mode) it ca be obtaied the exressios for the critical iut voltage ad the critical outut voltage, as: whe o IL 2 o to, DD rto, 1 r (3) 2 2 ( i t 0, ) ( i DD t 0, ) r( i t 0, ) t0, the threshold voltage of the NMOS trasistor, t0, the threshold voltage of the PMOS trasistor, r the trascoductace arameters ratio of the NMOS ad the PMOS trasistors, i iut voltage. ( W / L) ' r (4) ' ( W / L) trascoductace arameter of the NMOS trasistor, tracoductace arameter of the PMOS trasistor, ' - rocess trascoductace arameter of the NMOS trasistor, - rocess trascoductace arameter of the PMOS trasistor, ' W chael width of the MOS trasistor, L chael legth of the MOS trasistor, whereas idexes ad idicate the NMOS ad PMOS trasistor. The body effect of NMOS ad PMOS trasistor is ot reset i the CMOS iverter, because SB of both trasistors is zero. This will have to be tae ito cosideratio i other tyes of MOS iverters, as i NMOS iverter, whe it will ifluece the threshold voltage of NMOS ad PMOS trasistors, as well as the TC shae of iverters. Also, by usig the defiitio for obtaiig the exressio for iut voltage critical value IH (the larger of the two iut voltage values at which the sloe of the TC becomes do/di = -1), ad by usig D regio i TC of CMOS iverter, ad oeratio modes of the NMOS, ad the PMOS trasistors accordig to Table 1, we ca obtai the exressios for the critical voltage value IH ad the outut voltage o, as: (2)

5 Natural ad Egieerig Scieces 139 IH o DD to, 1 r 2 o to, r 2 2 ( i t 0, ) ( i t 0, ) 1/ r( i DD t 0, ) (6) I the CMOS iverter, it is also imortat to cosider a electrical arameter which reresets the threshold voltage of the CMOS iverter th, which is calculated uder the coditio that o = i. For calculatio of the threshold voltage of CMOS iverter th, the C regio of TC is used, where both trasistors (NMOS ad PMOS devices) oerate i saturatio mode ad will have: 1 r to, DD to, r th (7) 1 1 The low outut critical voltage value OL is calculated usig the E regio of TC, whe the NMOS trasistor oerates i liear mode ad the PMOS trasistor oerates i cut-off mode, resultig i: (5) OL 0 (8) The critical iut ad outut voltage values are also determiative to the oise margis values which characterize CMOS iverter for two logic levels (NML ad NMH) i static coditio of oeratio (steady state). The oise margis for two logic levels are exressed as: NML = IL-OL (9) NMH = OH -IH (10) From the exressios of the iut voltage critical values (IL ad IH) ad the outut voltage critical values (OL, OH) achieved above, imact o these characteristic voltage values will have: the values of the ower suly voltage (source voltage), the values of the threshold voltage of the comlemetary MOS trasistors, as well as the values of trascoductace arameters which characterize the comlemetary MOS trasistors. Relayig o fabricatio rocesses advaces of MOS trasistors, it is ossible that electrical ad hysical arameters which characterize MOS trasistors ca be cotrolled durig fabricatio rocess (Ludager, Zeiali, Tohidi, Madse, & Moradi, 2016; Plummer, Deal, & Griffi, 2009; Kag & Leblebici, 2016). Therefore, we will examie the imact of these arameters o the articular magitudes that characterize the CMOS iverter ad based o them, ca be defied the routes which lead to the desig of the CMOS iverter with favorable erformace accordig to the oeratio coditios ad digital circuits based o CMOS logic (Ludager, Zeiali, Tohidi, Madse, & Moradi, 2016; Karl, et al., 2013; Uddi, Nordi, Reaz, & Bhuiya, 2013; Chag, Liu, Zhag, & Kog, 2016; Zeiali, Madse, Raghava, & Moradi, 2015).

6 Natural ad Egieerig Scieces 140 Results ad Discussio The deedece of the iut voltage critical value IL o the ratio of MOS trasistors tracoductace arameters for two differet values of the threshold voltage of NMOS driver trasistor, whe the value of the PMOS trasistor threshold voltage (PMOS ca be treated as a load) remais costat, is reseted i Figure 3. Figure 3. The deedece of iut voltage critical value IL o ratio of MOS trasistor trascoductace arameters (the ratio of NMOS trascoductace arameters o PMOS trascoductace arameters) r for two differet values of NMOS threshold voltage (t0,), whe threshold voltage of PMOS trasistor has a costat value of t0, = I Figure 4 is show the deedece of iut voltage critical value IL o the ratio of MOS trasistor trascoductace arameters for a case whe threshold voltage of PMOS trasistor has two differet values (arametric values), whereas the NMOS trasistor threshold voltage remais costat. Figure 4. The deedece of iut voltage critical value IL o the ratio of MOS trasistor trascoductace arameters r for two differet values of PMOS threshold voltage (t0,), whe threshold voltage of NMOS trasistor has costat value of t0, = 0.5.

7 Natural ad Egieerig Scieces 141 For low critical value of iut voltage IL, the outut voltage value is slightly smaller tha value of the voltage source, but also it deeds o dimesios of the MOS trasistors ad their threshold voltage values. The imact of MOS trascoductace arameters ratio o outut voltage value o, for some arametric values of comlemetary MOS trasistor threshold voltages, is show i Figure 5. Figure 5. Ifluece of MOS trasistor trascoductace arameters ratio (r) o outut voltage value o, whe the iut termial of CMOS iverter is biased by voltage i = IL, for several arametric values of comlemetary MOS trasistor threshold voltage. From the results reseted i Figures 3 ad 4 for the iut voltage critical value IL, we ote that as the higher the value of the trascoductace arameter ratio of comlemetary MOS trasistors is, the low critical value of iut voltage IL will decrease. For higher values of the NMOS threshold voltage, the iut voltage critical value IL, will shift to higher values. Also, for the higher value of the absolute value of PMOS trasistor threshold voltage, the iut voltage critical value IL will shift to the lower values. The results reseted i Figure 5 show that whe the MOS trascoductace arameters ratio have higher value, the outut voltage value o will have higher values, whe the iut termial is biased by i = IL (or by iut low voltage critical value). Also, the imact o outut voltage value o will have liewise the values of MOS trasistors threshold voltage, but this imact is less imortat comared to the ratio of MOS trasistors trascoductace arameters. However for lower values of the comlemetary MOS trascoductace arameters ratio, the imact of threshold voltage of comlemetary MOS trasistors will be more sigificat. The imact of the MOS trasistor trascoductace arameters ratio, the MOS trasistor threshold voltage values i iut voltage critical value IH (high critical value of iut voltage) are show i Figures 6 ad 7. Preseted results show that the higher value of MOS trasistors trascoductace arameters ratio r will decrease the high critical value of iut voltage IH. Whe the value of the threshold voltage of NMOS trasistor is decreased, the the high critical value of iut voltage IH will be decreased ad this decreasig will be more romiet for the higher value of the MOS trasistor trascoductae arameters ratio r. Also, whe the value of the threshold voltage of PMOS

8 Natural ad Egieerig Scieces 142 trasistor icreases by absolute value, the iut critical voltage values IH will decrease, esecially the imact will be more sigificat for the smaller values of MOS trasistors trascoductace arameters ratio. Figure 6. The deedece of the voltage critical value IH o MOS trasistors trascoductace arameters ratio r for two arametric values of NMOS trasistor threshold voltage, whe PMOS trasistor threshold voltage remais costat t0, = Figure 7. The deedece of voltage critical value IH o MOS trasistors trascoductace arameters ratio r for two arametric values of PMOS trasistor threshold voltage, whe NMOS trasistor threshold voltage remais costat t0, = 0.5. Preseted results show that the higher value of MOS trasistors trascoductace arameters ratio r will decrease the high critical value of iut voltage IH. Whe the value of the threshold voltage of NMOS trasistor is decreased, the the high critical value of iut voltage IH will be decreased ad this decreasig will be more romiet for the higher value of the MOS trasistor trascoductae arameters ratio r. Also, whe the value of the threshold voltage of PMOS trasistor icreases by absolute value, the iut critical voltage values IH will decrease, esecially the imact will be more sigificat for the smaller values of MOS trasistors trascoductace arameters ratio.

9 Natural ad Egieerig Scieces 143 The MOS trasistors trascoductace arameters ratio ad the values of the MOS trasistors threshold voltage will have imact o the CMOS iverter characteristic value which is called the CMOS threshold voltage value (or switchig threshold). I Figures 8 ad 9 is show the imact of the MOS trasistors trascoductace arameters ratio that costitute CMOS iverter o the CMOS iverter threshold voltage value th for several arametric values of comlemetary MOS trasistors threshold voltage (NMOS ad PMOS threshold voltage). Figure 8. The imact of the trascoductace arameters ratio (r) of MOS trasistors (NMOS ad PMOS) o value of the CMOS iverter threshold voltage (o value of CMOS iverter switchig threshold voltage) for two differet values of the NMOS threshold voltage, whe t0, = ad source voltage DD = 2.5. Based o the obtaied results, it is show that the higher value of MOS trascoductae arameters ratio is, the CMOS threshold voltage value will be decreased, resectively, it will be shifted towards the logical lower value. For higher values of the NMOS threshold voltage, the value of the CMOS threshold voltage th would icrease i value, esecially the imact will be more romiet for greater values of the trascoductace arameters ratio r ( > ). While whe the threshold voltage of the PMOS trasistor has a higher value by absolute value, the value of the CMOS threshold voltage th will be decreased, ad this decreasig will be more sigificat whe the trascoductace arameter ratio r has lower values ( < ).

10 Natural ad Egieerig Scieces 144 Figure 9. The imact of the trascoductace arameters ratio (r) of MOS trasistors (NMOS ad PMOS) o value of the CMOS iverter threshold voltage th (o value of CMOS iverter switchig threshold voltage) for two differet values of the PMOS threshold voltage, whe t0, = 0.5 ad DD = 2.5. The immuity of CMOS iverter o uwated sigals is exressed through the oise margis for both logical levels (for low level ad for high level). The arameters that characterize the comlemetary MOS trasistors i a CMOS iverter determie the oise margis level for both logical levels. The deedece of oise margis (NM) o the comlemetary MOS trasistors trascoductace arameters ratio, for several arametric values of MOS trasistors threshold voltages i both logic levels are show i Figures 10 ad 11. Figure 10. The deedece of the oise margis for low logic level NML o comlemetary MOS trasistors trascoductace arameters ratio r, for three cases of differet MOS trasistor threshold voltage (NMOS ad PMOS trasistors), whe DD = 2.5. The results i Figure 10 idicate that the higher values of the MOS trascoductace arameters ratio r, oise margi for the low level will be lower. For the lower value of the NMOS trasistor threshold voltage (t0,), the level of oise margis NML (oise margis for low level) will decrease, resultig i the sigificat reductio i the bad of higher values of the

11 Natural ad Egieerig Scieces 145 trascoductace arameter ratio r. Also, the smaller the PMOS trasistor threshold voltage value (t0, ) by absolute value, the level of oise margis NML will icrease, esecially i the rage of small values of the trascoductace arameters ratio r. Figure 11. The deedece of the oise margis for high logic level NMH o comlemetary MOS trasistors trascoductace arameters ratio r, for three cases of differet MOS trasistor threshold voltage (NMOS ad PMOS trasistors), whe DD = 2.5. The level of oise margis NMH (oise margis for high level) will icrease whe the MOS trascoductace arameter ratio is desiged to be higher, Figure 11. For smaller value of NMOS threshold voltage, the oise margi for high level NMH will icrease esecially i the rage of higher values of the trascoductace arameter r. While the lower value of PMOS threshold voltage by absolute value (t0,), the level of oise margis NMH will decrease, esecially with sigificat imact i the rage of low values of the trascoductae arameter ratio r. By matchig the values of comlemetary MOS trascoductace arameters ad values of their threshold voltage, the CMOS iverter ca be desiged with higher erformace, deedig o the requiremets of desiger that dictate oeratio coditios. For CMOS iverter with matched arameters as: = ad t0, = t0, will be achieved that the oise margi to be equal to both logic levels ad the value of the threshold voltage of the CMOS iverter will be half of voltage source th = DD/2. The CMOS iverter which ossesses these features is called symmetric iverter ad it must satisfy the coditio: symetric 1 Cox W / L W / L W W 2.5 Cox W / L W / L L L (11) ad although the MOS trasistors built by equal legth of chael defied by lithograhic rocess, it aears that: W 2. 5W ) (12)

12 Natural ad Egieerig Scieces 146 The behavior of CMOS iverter is described through the TC i DC mode of oeratios (steady state mode). The arameters that characterize the comlemetary MOS trasistors ifluece i the shae of the TC. At the desig hase of CMOS iverter, the requiremets of CMOS iverter behavior are reseted, so the tas of the desiger is to adjust the arameters of the NMOS ad PMOS trasistors as much as ossible, which eable the desig of the CMOS iverter with accetable erformace. The imact of NMOS ad PMOS trasistor arameters i shae of the TC is show i Figure 12. Figure 12. The imact of comlemetary MOS trasistors chael legth ratio (W/W) o TC shae, whe L = L, t0, = t0, = 0.5 ad DD = 2.5. From the TC shae reseted i Figure 12 we ca see the imact of the chael width (resectively the ratio of the trascoductace arameter r) i the shae of TC, resultig i dislacemet of the TC's left or right, deedig o the chaels widths ratio, ad reflectig i the characteristic values of TC's. Whe the value of NMOS trasistor threshold voltage icreases, ad the PMOS trasistor threshold voltage remais uchaged, the TC of CMOS iverter shall shift to the right from the lower value of the NMOS threshold voltage (t0.), which is reflected i the voltage critical values, Figure 13. Figure 13. The imact of the NMOS trasistor threshold voltage (t0,) o TC shae, whe PMOS trasistor threshold voltage is t0, = - 0.5, ad trasistors have idetical dimesios. I Figure 14 is show the imact of the PMOS trasistor threshold voltage value i TC shae of CMOS iverter whe the NMOS trasistor threshold voltage has a fixed value. Whe the PMOS

13 Natural ad Egieerig Scieces 147 trasistor threshold voltage has lower value by a absolute value, the the CMOS iverter TC will shift to the right from the larger value. Figure 14. The imact of PMOS trasistor threshold voltage (t0,) o CMOS iverter TC shae, whe NMOS trasistor threshold voltage value is t0, = 0.5, ad trasistors have idetical dimesios. Accordig to the shaes of TC of the CMOS iverter reseted i Figure the sloe of TC i articular regios is idicted. It s very imortat that the sloe of TC i regio amed by C is same i all cases, which differs for other tyes of MOS iverters. Coclusios If durig the desig hase of the CMOS iverter, the threshold voltage values of comlemetary MOS trasistors (with the threshold voltage of NMOS (t0,) ad PMOS trasistor (t0,)) ad the ratio of comlemetary MOS trasistors trascoductace arameters (the ratio betwee trascoductace arameters of NMOS trasistor () ad PMOS trasistor (), r = /) are cotrolled, or matched, the CMOS iverter ca be desiged with high erformace as for static coditios of oeratio, as well as for dyamic coditios of oeratios, deedig o the desiger requiremets ad oeratig coditios. As for the outut voltage critical values OL ad OH (or for high ad low logic level at outut), the trascoductace arameter ratio of the comlemetary CMOS trasistors (r) ad the comlemetary MOS trasistor threshold voltages (t0. ad t0,) do t have imact, but their values are determied by zero volt (groud voltage) ad source voltage value (DD). For the higher values of comlemetary MOS trasistors trascoductace arameters ratio (r), lower value of the NMOS trasistor threshold voltage (t0,) ad higher value by absolute value of the PMOS trasistor threshold voltage (t0.), the iut voltage critical value IL ad oise margi for low level NML will decrease. For the higher values of comlemetary MOS trasistors trascoductace arameters ratio (r), lower value of the NMOS trasistor threshold voltage (t0,) ad higher value by absolute value of the PMOS trasistor threshold voltage (t0.), the iut voltage critical value IH will decrease, whereas oise margi for high level NMH will icrease. As for the outut voltage value o whe i = IL, for the higher values of comlemetary MOS trasistors trascoductace arameters ratio (r), lower value of the NMOS trasistor threshold voltage (t0,) ad higher.

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