Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment

Transcription

1 Aalysis ad Desig of LVTSCR-based EOS/ESD Protectio Circuits for Bur-i Eviromet O. Semeov, H. Sarbishaei ad M. Sachdev Det. of Electrical ad Comuter Egieerig, Uiversity of Waterloo, Waterloo, Caada NL 3G ABSTRACT As techology feature size is reduced, ESD becomes oe of the domiat failure modes due to the lower gate oxide breakdow voltage. Also, the holdig voltage of LVTSCR devices is reduced with oeratig temerature icrease. As a result, durig stress testig (bur-i), the risk of latch-u i LVTSCR is extremely high. this aer, a ew latch-u free LVTSCR-based rotectio circuit is roosed. t ca be reliably used i sub-.8 um CMOS techologies ad buri eviromet. The roosed ESD circuit has higher holdig voltage by.5x tha the covetioal LVTSCR structure at bur-i temerature. Uder 3kV HBM ESD stress, the develoed LVTSCR-based rotectio circuit has the voltage eak less tha the covetioal LVTSCR structure ad GG-MOSFET by X ad.5x, resectively. Keywords - Electrostatic discharge (ESD), electrical overstress (EOS), LVTSCR, bur-i, latch-u.. troductio Electrostatic Overstress ad Discharge is cosidered as a major reliability threat i the semicoductor idustry for decades. t was reorted that ESD ad EOS are resosible for u to 7% of failures i C techology []. Therefore, each /O must be desiged with a rotectio circuitry that creates a discharge ath for ESD curret. As a CMOS techology scales dow, the desig of ESD rotectio circuits becomes more challegig. This is due to thier gate oxide ad shallower juctio deth i advaced techologies that makes them more vulerable to ESD damages. additio, secial accelerated test methods such as bur-i are ofte emloyed as reliability screes to weed out ifat mortalities. Weak gate oxides are oe of the major comoets of such failures. These failures are accelerated due to elevated temerature (~5ºC), elevated voltage (V DD + 3%) ad log stress time (3-68 hours). Uder stress oeratig coditios, ESD robustess of rotectio devises becomes worse. Silico Cotrolled Rectifiers (SCRs) i low voltage triggered cofiguratios (LVTSCR) are the oular rotectio elemets that are used for o-chi ESD rotectio. The excellet high curret behavior of LVTSCRs rovide a area gai factor of 4X to 5X over the silicide-blocked grouded-gate N-MOSFET (GG- NMOSFET). Geerally, ESD rotectio device should have the first breakdow voltage less tha the breakdow voltage of the gate oxide while its holdig voltage should be greater tha V DD i order to avoid the latch-u ossibilities. However, the relatively high triggerig voltage (~- V) ad low holdig voltage (~.5-.5 V) restrict the alicatio of covetioal LVTSCR ESD devices for sub-.8 micro CMOS techologies []. The risk of latch-u i SCR structures ad hece the ost bur-i yield losses are sigificatly icreased uder stress oeratig coditios durig bur-i [3]. Note, that the bur-i testig is tyically erformed at T=-5ºC ad V DD =.-.3V for.8 um CMOS techology. this aer, a ew imlemetatio of latch-u free LVTSCR-based ESD rotectio circuit for bur-i eviromet is roosed. The develoed ESD rotectio device has the followig features: () The holdig voltage (V h ) more tha 3V at stress temerature (to avoid latch-u i LVTSCR uder bur-i oeratig coditios), () The triggerig voltage (V tr ) less tha 9V (to revet the gate oxide breakdow due to ESD evet i sub-.8 um trasistors) (3) The ESD robustess is more tha 3kV of huma body model (HBM) ESD stress. Our results show that the roosed LVTSCR-based ESD rotectio circuit has sigificatly lower V tr ad higher V h tha the covetioal LVTSCR device. Also, it has less V tr ad eak temerature durig ESD evet tha the covetioal GG-MOSFET with equivalet device width. Hece, the develoed ESD circuit is more robust at ESD evet ad bur-i coditios i comariso with the commoly used ESD rotectio devices. The rest of the aer is orgaized as follows: Sectio, we review the oeratig features of ESD rotectio circuits i bur-i eviromet. The covetioal LVTSCR structure ad the roosed ESD rotectio circuits, used i our research, are described i Sectio 3. The circuit ad device simulatio results at bur-i oeratig coditios ad 3kV HBM ESD stress are reseted i Sectio 4. Sectio 5, the aalytical modelig of temerature deedecy of holdig voltage i aalyzed ESD circuits is reseted. Fially, the coclusios are summarized i Sectio 6.. ESD Protectio Devices uder Bur-i Stress Durig bur-i testig devices i the chi ca be damaged, whe icorrect test vectors, systems ad rocedures are used. Usually, bur-i systems iclude voltage rotectio circuits, byass caacitors, bur-i /5 $. (c) 5 EEE

2 oves, driver boards ad ower suliers. Over voltage or uder voltage sikes o ower suliers or device iuts ca result i ESD device ad /O buffer failures. ractice,.5v sikes were observed o iut is of Field Programmable Gate Arrays (FPGAs) due to the electrical overstress (EOS) i bur-i oves durig the stress testig. Note, that.5 V sike for a.5v chi is 67% overstress [4]. Hece, the covetioal LVTSCR structures ca ot be used for EOS/ESD rotectio due to the high risk of latch-u. Cascaded diodes are other semicoductor devices, which are widely used for ESD rotectio. The tyical forward biased tur-o voltage of diode is.6-.7v at room temerature. Hece, for reliable ESD rotectio i.8 um CMOS techology we eed four diodes coected i series. At bur-i temerature (-5ºC), the diode strig leakage curret is icreased due to the Darligto effect ad the diode tur-i voltage is reduced from.6v to.4v. As a result, a loger diode strig will be eeded to rovide the same EOS/ESD rotectio at stress temerature ad to revet the false triggerig uder voltage sikes i bur-i ove. However, the icrease i umber of diodes ad their series resistace may have effect o ESD reliability [5]. For GG-MOSFET rotectio devices, the bur-i is ot such a severe cocer because these devices are oly exeriece higher leakage curret uder stress oeratig coditios. 3. ESD Protectio Circuits uder vestigatio To develo the LVTSCR-based rotectio circuit with latch-u immuity uder bur-i oeratig coditios, low triggerig voltage ad high ESD robustess, the followig ESD structures were studied i this work: () covetioal LVTSCR, () LVTSCR with gate or/ad substrate triggerig to reduce the V tr [6,7], (3) LVTSCR with high V h otio ad (4) GG-MOS trasistor, which was used for the comariso. All these circuits were desiged usig.8 um CMOS techology (T ox =4Å). Electrothermal simulatio has bee itroduced to geeral-urose commercially available device simulatio i the early 9-ties by TMA [8]. Validity of hysical models such as mobility, imact ioizatio rates, etc. has bee cofirmed by umerous idustrial alicatios ad is geerally believed to exted to aroximately 6-7K. Sice the a umber of other TCAD comaies also develoed similar electrothermal models, icludig Silvaco, SE ad SEQUOA. our research, we used -D "SEQUOA ESD" simulatio software, which was develoed by Sequoia Desig Systems for characterizatio of a ESD evet [9]. This simulator has built-i device sythesis, mesh geeratio, device simulatio, circuit-device mixed-mode simulatio ad lattice self-heatig simulatio modules. The hysical structures of rotectio devices used for ESD simulatios ad quasi-dc -V characteristics are give i Fig.. These device structures were calibrated usig idustrial data by Sequoia Desig Systems. LVTSCR structure was imlemeted as a uch-through-iduced rotectio elemet []. The quasi-dc simulatios were erformed uder high curret coditios icludig a self-heatig effect. The iut voltage was ramed liearly u to kv durig ~s of stress time ad was alied to a large resistor (5 Ohm) i series with the ESD device to limit the curret. -V characteristics were extracted from these simulatios. Fig. shows that at room temerature, for LVTSCR ad GG-MOSFET, V tr is.5v ad 9.5V resectively, while V h is.v ad 3V resectively. (c) Log(Curret), A.... (a) (b) Voltage, V Holdig voltage (Vh) Triggerig voltage (Vtr) LVTSCR, W= um GG-MOSFET, W =4 um Fig.. (a) Cross-sectio of.8 um silicided GG- NMOSFET, (b) Cross-sectio of surface-iduced LVTSCR, (c) Quasi-DC -V characteristics of ESD devices.

3 The schematics of aalyzed ESD rotectio circuits are show i Fig.. The size of ESD rotectio devices was chose to ass a 3kV HBM ESD stress. our simulatios, the waveform of 3kV HBM ESD stress had 4 s (%-9% of eak) rise time ad s (9%-% of eak) decay time (see Fig 3). The equivalet huma body resistace was 5 Ohms. Note, that the size of GG- MOSFET ad the equivalet size of all active devices i LVTSCR-base ESD circuit are the same. Trasistors used for substrate triggerig ad high V h should be large to rovide a sigificat curret umed ito substrate of LVTSCR ad groud. O the other had, the trasistor used for gate triggerig ca be sigificatly smaller. This trasistor oly rovides the voltage biasig o the gate of LVTSCR durig ESD evet. HBM ESD voltage waveform, V E+.E-8 4.E-8 6.E-8 8.E-8.E-7 Time, sec voltage waveform curret waveform HBM ESD curret waveform, A Fig. 3. 3kV HBM ESD stress waveforms used for simulatios % (a) Holdig voltage (Vh), V % 7% 7% 5% %.5 LVTSCR LVTSCR with gate trig. LVTSCR with high Vhold GG-MOSFET LVTSCR with sub. trig. LVTSCR with gate-sub. trig. LVTSCR with high-vhold-sub. trig Temerature, K (b) Fig.. (a) ESD GG-NMOSFET, (b) LVTSCR-based rotectio circuit with differet otios. 4. Simulatio Results: V h uder Bur-i Oeratig Coditios ad HBM ESD Stress From Fig. (c), we ca coclude that the basic disadvatages of covetioal LVTSCR rotectio devices are high V tr ad low V h. Note, that the holdig voltage of SCR-based devices decreases with elevatig temerature []. Hece, it is imortat to develo the LVTSCR-based rotectio circuit with high V h to avoid latch-u durig bur-i. To estimate the imact of elevated temerature o LVTSCR rotectio device with differet otios (see Fig. (b)), the holdig voltage was extracted from the quasi-dc -V characteristics obtaied from simulatios for differet temeratures. The Fig. 4. The comariso of V h deedecy o ambiet temerature for differet techiques alied for LVTSCR (V h of GG-MOSFET is show for the comariso). simulatio results are deicted i Fig. 4. From these grahs, we ca coclude that i the first order aroximatio, the V h has a liear deedecy o temerature i the rage of 3K-4K. The same temerature tred of holdig voltage was also observed i exerimetal results i SCR (. um CMOS rocess) [] ad LVTSCR (.5 um CMOS rocess) structures []. The otatios i Fig. 4 show the reductio of holdig voltage i ercetage, whe the ambiet temerature icreases from room temerature to bur-i temerature (4K). We ca ote that the LVTSCR with gate triggerig has the holdig voltage degradatio by 4X stroger tha the LVTSCR with substrate triggerig. Hece for bur-i coditios, the substrate triggerig techique is more referable for usig i LVTSCR-based

4 EOS/ESD rotectio circuits for triggerig voltage reductio tha the gate triggerig techique. To icrease the holdig voltage at room ad stress temeratures, we develoed a secial techique (see otio #3 i Fig. (b)), which iclude trasistor T3 with RC gate coulig etwork. The combiatio of substrate triggerig techique ad high V h otio gives us the icrease of holdig voltage by.56x (from.5v to 3.35V) at room temerature ad by.5x (from V to 3V) at bur-i temerature (4K). Note, that 3V of holdig voltage at stress temerature is eough to revet the latch-u of LVTCSR-based rotectio circuit due to.5v sikes o chi iut is i bur-i ove durig the stress testig. 4. Desig of LVTSCR-based Protectio Circuit for 3kV HBM ESD Stress As it was metioed before, the mai advatage of usig LVTSCR is it s a high ESD rotectio level er uit area. After quasi-dc simulatios, we also simulated huma body 3kV ESD evets at room temerature. The urose of this aalysis was to reduce the triggerig voltage of LVTSCR from origial 5V to accetable level, which should be less tha 9V. The GG-MOSFET (see Fig. (a)) was also simulated for the comariso. From the revious aalysis, we foud that the substrate triggerig techique is otimal for bur-i coditios ad we used this techique for V tr reductio. The obtaied simulatio results are show i Fig. 5. From these grahs, we ca coclude that the develoed techique for high V h allows us to icrease the holdig voltage by.6x uder trasiet oeratig coditios. The substrate triggerig techique reduces the triggerig voltage by X from 5V to 7.5V. To reduce the secod voltage eak i LVTSCR with high V h, the bulk electrodes of T ad T3 trasistors (see Fig. (b)) Outut waveform, V Triggerig voltage (Vtr) Holdig voltage (Vh).E-.E-.E-.E-9.E-8.E-7.E-6 Log(Time), sec LVTSCR LVTSCR-high-Vhold GG-MOSFET LVTSCR-high-Vhold-sub-trig Fig. 5. Outut waveform of LVTSCR-based rotectio circuits ad GG-MOSFET uder 3kV HBM ESD stress (T=3K) Voltage, V Fig. 6. LVTSCR-based EOS/ESD rotectio circuit develoed for bur-i eviromet ad sub-.8 um CMOS techologies. 3 Substrate-otetial-LVTSCR Gate-otetial-Tr-r-T3 Bulk-otetial-Tr-rs-T-T3 -.E-.E-.E-.E-9.E-8.E-7 Log(Time), sec Fig. 7. teral otetials i LVTSCR-based rotectio circuit uder 3kV HBM ESD stress. were coected together ad were shorted with cathode termial of LVTSCR. The fial LVTSCR-based rotectio circuit, which was otimized for bur-i eviromet ad sub-.8 um CMOS techologies, is show i Fig. 6. This circuit has less voltage eak by % (8V) ad higher holdig voltage by 5% (4.5V) i comariso with the covetioal GG-MOSFET with the same device width at 3kV HBM ESD stress. The effectiveess of imlemeted techiques i LVTSCRbased rotectio circuit ca be exlaied as follows: Durig the ESD stress, substrate ad well otetials of LVTSCR ad T/T3 trasistors sigificatly exceed the built-i - juctio otetial (~.7 V) (see Fig. 7) ad the arasitic BJT trasistors are activated i these devices. As a result, the triggerig voltage of roosed circuit becomes less tha the triggerig voltage of covetioal LVTSCR ad GG-MOSFET. The gate otetial of T3

5 trasistor exceeds his threshold voltage V th (>.5 V) as show i Fig. 7. Hece, durig the ESD evet this trasistor ca ass sigificat curret from the ad to groud. At ormal ad bur-i oeratig coditios T3 trasistor rovides the high holdig voltage, which allows us to elimiate the lath-u i LVTSCR structure. 4. Evaluatio of ESD Robustess of LVTSCR-based Protectio Circuit Geerally, the destructio of a ESD device occurs at the threshold voltage, at which the maximum temerature i device structure reaches the meltig oit of silico (4 C) [3] (tyically i the gate-to-drai overla regio) or the meltig oit of metallizatio (66 C for alumium based metallizatio ad 34 C for coer based metallizatio) [4]. To estimate the ESD robustess of roosed LVTSCR-based rotectio circuit, we erformed thermal simulatios ad extracted eak temerature durig the 3kV HBM ESD stress. For comariso, the same simulatios were erformed for the GG-MOSFET. The width of this device (4 um) was equalled to the total width of T, T3 trasistors ad LVTSCR (see Fig. 6). The sizes of GG-MOSFET ad LVTSCR-based rotectio device were chose to revet the iteral heatig more tha 66 C at 3kV ESD stress. The thermal simulatio results are show i Fig. 8. From this figure, we ca coclude that the self-heatig effect i roosed LVTSCR-based rotectio circuit is less by % tha the self-heatig effect i GG-MOSFET. Hece, the ESD robustess of roosed ESC circuit is stroger tha the ESD robustess of covetioal GG-MOSFET. Note, that i the develoed LVTSCR-based ESD rotectio circuit, the strogest heatig has trasistor T. Peak temerature, K GG-MOSFET LVTSCR-high-Vhold-sub-trig 3.E-.E-.E-.E-9.E-8.E-7.E-6 Log(Time), sec Fig. 8. Self-heatig effect i ESD rotectio devices uder 3kV HBM ESD stress. 5. Aalytical Model for Temerature Deedece of Holdig Curret order to verify the validity of simulatios results, a aalytical model for holdig curret of LVTSCR is reseted i this sectio. Fig. 9 (a) shows a simle model for LVTSCR which cosists of arasitic biolar ad MOS trasistors. Fig. 9. (a) A model for LVTSCR (b) A model for gate-coulig ad substrate-triggerig effects. Usig collector curret equatios of biolar trasistors, the holdig curret of LVTSCR ca be exressed as follows. () ( + ) W + ( + ) S + h = D VGS = t has bee show that the first term i Eq. is the holdig curret of SCR [5]. Therefore, + LVTSCR ) = SCR) D VGS = order to use this model uder gate-coulig ad substrate-triggerig coditios, two bias voltages are added to the model, which rereset gate ad substrate bias of the LVTSCR. This model is show i Fig. 9 (b). Accordig to the ew model, Eq. ca be modified to cover the effect of gate-coulig ad substrate-triggerig techiques. Holdig curret for gate-triggered LVTSCR (GTLVTSCR) ad substrate-triggered LVTSCR (STLVTSCR) are give i equatios 3 ad 4 resectively. + GTLVTSCR) = SCR) (3) D V GS (4) + V + Sub STLVTSCR) = SCR) D VGS = R order to model the temerature deedecy of holdig curret, gai of biolar trasistors ( ad ), well ad substrate resistaces (R W ad R S ), ad MOSFET curret ( D ) should be determied i terms of temerature. other words, to redict variatios of holdig curret uder bur-i coditios, the temerature deedecy of mobility (, ), curret gai of BJTs (, ) ad MOSFET threshold voltage (V th ) should be derived. t has bee reorted that V th has a liear deedecy o temerature. For.8 m techology, dv th /dt is S ()

6 .6mV/ C [6]. our research we used mobility models roosed by N. Arora et al. [7]. They develoed electro ad hole mobility models as a fuctio of temerature ad doig cocetratio. For temerature deedece of, a umerical exressio (Eq. 5) has bee roosed i [8]. T = T + a T T + b T (5) ( ) ( ) ( ) ( ) ( ) T where costats a ad b ca be determied from simulatios. order to fid these values, the SCR structure has bee divided ito two arasitic biolar trasistors (Q N ad Q P ). Values of a ad b were fouded by extractig from MEDC simulatios for two differet temeratures. To solve equatios,3 ad 4, a MATLAB simulator has bee used. Fig. shows the holdig curret of LVTSCR, GTLVTSCR ad STLVTSCR for differet temeratures. t ca be see that the holdig curret of STLVTSCR has the lowest deedecy o temerature ad the holdig curret of GTLVTSCR has the highest temerature deedecy. This agrees with simulatio results of Fig. 4, sice ESD rotectio device has a resistive -V characteristic after the saback regio ad therefore holdig voltage ad holdig curret have the same temerature deedecy tred. Fig.. Temerature deedecy of holdig curret of LVTSCR with gate- ad substrate-triggerig. 6. Coclusio This aer reorts a ew desig of LVTSCR-based EOS/ESD rotectio circuit otimized for bur-i eviromet ad sub-.8 um CMOS techologies. The aalytical model of holdig voltage temerature deedecy of LVTSCR-based structure has bee develoed. The roosed ESD circuit has higher holdig voltage by.5x (3V) tha the covetioal LVTSCR structure (V) at bur-i temerature. t allows us to elimiate the latch-u i LVTSCR due to voltage sikes (.5V) o chi iut is durig bur-i. Uder 3kV HBM ESD stress, the develoed LVTSCR-based rotectio circuit has the voltage eak (7.5V) less tha the covetioal LVTSCR structure (5V) by X ad less tha the GG-MOSFET (9.5V) by.5x. Hece, it ca revet the gate oxide breakdow due to ESD evet i sub-.8 um CMOS techologies. A ew rotectio circuit has the self-heatig effect less tha the covetioal GG-MOSFET by % at 3kV HBM ESD stress. Therefore, it has higher ESD robustess tha the traditioal ESD rotectio devices. Ackowledgemet The authors would like to thak V. Axelrad ad A. Shibkov (Sequoia Desig Systems) for rovidig of TCAD tool ad discussio of obtaied results. Refereces [] J-B Huag, et al., ESD rotectio desig for advaced CMOS, Proc. of SPE, vol. 46,, [] Markus P.J. Merges, et al., High holdig curret SCRs (HH-SCR) for ESD rotectio ad latch-u immue C oeratio, Proc. of EOS/ESD Sym.,, aer A3. [3] C.Y. Chiag, Latch-u at RAM cotrol circuitry, Proc. of PFA, 997, [4] M. Sawat, et al., Post rogrammig bur i (PPB) for RT54SX-S ad A54SX-A ACTEL FPGAs, htt:// [5] S. Dabdal, et al., Desigig o chi ower suly coulig diodes for ESD rotectio ad oise immuity, J. of Electrostatic, vol.33, No.3, , 994. [6] M. D. Ker, et al., "A Gate-Couled PTLSCR/NTLSCR ESD Protectio Circuit for Dee-Submicro Low-Voltage CMOS C s," EEE J. Solid-State Circuits, vol. 3, No.,. 38-5, 997. [7] M.D. Ker, et al., Substrate-Triggered SCR Device for O-Chi ESD Protectio i Fully Silicided Sub-.5 m CMOS Process, EEE Tras.o Electro Dev., vol. 5, No., , 3. [8] V. Axelrad ad R. Klei. Electrothermal simulatio of a GBT, t. Sym. o Power Semicod. Dev. ad Cs, , 99. [9] SEQUOA Device Desiger User's Guide, Sequoia Desig Systems, htt:// [] K. Kwo, et al., "A ovel ESD rotectio techique for submicro CMOS/BiCMOS techologies," Proc. of EOS/ESD Sym., 995, [] S.-L. Jag, et al., Temerature-deedece of steady-state characteristics of SCR-tye ESD rotectio circuits, Solid-State- Electroics J., vol. 44, o., ,. [] R.B. Brow, et al., Juctio-isolated CMOS for high-temerature microelectroics, EEE Tras. O Electro Dev., vol. 36, No. 9, , 989. [3] D.L. Li, "ESD sesitivity ad VLS techology treds: thermal breakdow ad dielectric breakdow," EOS/ESD Symosium,. 73-8, 993. [4] S.H. Voldma, "The imact of techology scalig o ESD robustess of alumium ad coer itercoects i advaced semicoductor techologies," EEE Tras. o Comoet, Packagig, ad Maufacturig Tech., Part C, vol., No 4, , 998. [5] F.S. Shoucair, High-Temerature latchu characteristics i VLS CMOS circuits, EEE Tras. o Electro Dev., vol. 35, No., , 988. [6] O. Semeov, et al., Leakage curret i sub-quarter micro MOSFET: a ersective o stresses delta DDQ testig, J. Electroic Testig: Theory ad Alicatio, 3, [7] N.D. Arora, et al., "Electro ad hole mobilities i silico as a fuctio of cocetratio ad temerature," EEE Tras. o Electro Dev., vol. ED-9, No.,. 9-95, 98. [8]. E. Getreu, Modelig the Biolar Trasistor, Elsevier Sci. Pub. Comay, 978.