Your name. Scalable Regulated Three Phase Power Rectifier. Introduction. Existing System Designed in 1996 from Dr. Hess and Dr. Wall.

Transcription

1 Scalable Regulated Three Phase Power Rectifier ECE480 Seior Desig Review Tyler Budziaowski & Tao Nguye Mar 31, 2004 Istructor: Dr. Jim Frezel Techical Advisors: Dr. Hess ad Dr. Wall Sposors: Dr. Hess ad Dr. Wall Itroductio Purpose of the project Paper authored by Dr. Wall ad Dr. Hess Itel 196KD microcotroller obsolete Or lacked programmig experiece Geeral ideas of ew desig Replace the system with a ew microcotroller Upgrade hardware compoets of etire system Existig System Desiged i 1996 from Dr. Hess ad Dr. Wall Objectives Three Phase SCR Power Coverter Microcotroller applicatio Phase A Phase B Phase C HSI sigal iput Zero Crossig Detectio Phase Locked Loop Iput Delay Cotrol HSO to SCR devices H11L1QT Optoisolator High Speed Iputs High Speed Outputs Delay New Desig Aspect Maitai the all curret features of existig desig Decrease SCR Gate Drivers i80c196kd up Icrease Delay S1 S3 S5 S4 S6 S2 RUN - STOP Output Load Coverter Power ON/OFF Idicatio Replace the system with a moder ad less expesive microcotroller Implemet closed-loop cotrol for voltage/curret regulatio Prototype should less tha 25VAC Structure voltage iput commad Create a local display for system iformatio Upgrade zero-crossig detectio accordig to Wall Upgrade the SCR gate firig architecture Istall subbig ad protectio for SCRs Geerate MATLAB-based model Title goes here 1

2 Desig Compoets Microcotroller Microchip PIC16C73B Microcotroller ad protoboard Silico Cotrolled Rectifier (Thyristors) LCD System Display Uit Iput Etry Keypad Upgraded Sigal Optoisolators Upgraded SCR Gate Firig Circuitry/Architecture Subbig Capacitors ad Resistors Microchip PIC16C73B Microcotroller 4K X 14 words Program Memory 192 X 8 bytes Data Memory (RAM) 20 MHz clock with 200 s istructio cycle low power cosumptio ( > 5 5 V) 22 I/O pis Sillico Cotrolled Rectifiers (SCRs) LCD System Display Uit Teccor D4025L SCRs Six SCRs will be eeded Rated voltage 400V Rated Curret 25A Storage ad Operatig temperature rage is -40 to +125 degree C LCD (ACM1602B Series) Module 2 lies, 16 characters per lie Power supply (+5V) 4-bit or 8-bit Data bus 14 ad 16 pi, sigle row iterface 5x7 dot matrix character + cursor Overall size i mm 84(w) x44(h)x1.35(d) Operatig temperature 0-50 degree C Title goes here 2

3 LCD Data Sheet Iput Etry Keypad 4x4 matrix keypad cotact ratig: 10mA resistive 9-pi data bus KeyPad Data Sheet Optoisolators TLP2200 Optoisolators Detects zero crossig of iput AC sigal Compesate for variatios i level sesitivity Provides oise filterig Circuit Model 6 Positive O 4 2 Volts 0-2 Negative O Iput sigal Time - ms Title goes here 3

4 SCR Gate Firig Circuitry Subbig System FCOAUX-60 Three-Phase Firig Board (eerpro) Selectable 60Hz/50Hz operatio Delay circuit forms a set of phase balace (60 degree) 12 V logic sigal Purpose of Subbig Circuit to slow dow the rate of applied voltage (dv/dt)give a trasiet to prevet damage to SCRs due to high voltage trasiets or spikes to prevet SCRs from false tur o by voltage trasiets Desig cosists of 6 capacitors ad 6 resistors i a series cofiguratio, with both i parallel with the SCR diode SCR R C3 Cs ad Rs Equatios Overview of Microcotroller Setup Optoisolators SCR Gate Drivers HSI HSO PIC16C73B Microcotroller Iput Commad Iput Display Output Display Title goes here 4

5 HSI Iterrupt Service Routie Phase Locked Loop (PLL) High Speed Iput (HSI) Receives Output of the Optoisolators ad Samples The Capture Time Data is Iterated Through the Phase Locked Loop Save Evet Time Retur eg. o No Reset Ru & Lock Flags Retur HSI ISR Capture time Evet? pos. o Compute zero crossig time - Tzcm Compute filtered Tzc, Pd, ad Pd/6 from PLL algorithm Compute sum squared, of Phase Cotrol S<=Limit? S, Yes Start Flag No Set? Yes Set Tref=Tzc Start HSO Clear Start Flag Measured zero crossig time Tcm Samples the detected zero crossig time ad predicts the ext zero crossig time Utilizes a digital lowpass filter algorithm ad adds the filter to a fixed bias (feed-forward). forward). Oce lock is achieved, Pd is locked to the sigal i both frequecy ad phase Tzc Period Error Pde Lowpass Filter Period adjust Fixed period bias Pd 0 Pd Tzc Divide by 6 1/z Pd Pd/6 Tzc +1 Predicted ext zero crossig time Filtered period outputs Phase Locked Loop Cot. Volts 6 Positive O Negative O Iput sigal Time - ms Iput sigal is oisy ad ca produce erroeous zero crossigs 6 SCR Firig Timig Diagram 6 outputs for each of the 6 SCRs Each is fired by the microcotroller 4 Negative O Volts 2 0 Est. Zero Positive O Iput Sie Sigal Time - ms Iterpolatio is used through the PLL to predict the ext zero crossig time Cotrol diagram for SCR Firig Timig Title goes here 5

6 HSO Iterrupt Service Routie Output sigal has iterated through phase locked loop Sigal output from microcotroller is routed to gate firig circuitry Retur Noe set HSO ISR Flags? Determie HSO pi states from firig table Ru Flag Compute HSO pi high evet times from Tref, Pd, Pd/6, ad T d, Determie HSO pis from sequece table Schedule pi high ad pi low evets Retur Summary of Budget Labor Costs: Price per Uit Total Cost Tyler Budziaowski (165 hrr) $25/hr 4,200 Tao Nguye (165hrs) $25/hr 4,200 Total Labor Cost: 8,400 Part Costs: Update Budget 6 Thyristors $1.8 $1.8 x 6 = 9.6 PIC ProtoBoard $200 1 PIC16C73B processor $10 $10 2 TLP2200 Optoisolators $2.48 $ SCR Gate Drivers $278 $278 1 LCD $16 $16 Total Costs: $520 Proposed Budget Price per Uit Tyler Budziaowski (165 hrs) $25/hr $4,200 Tao Nguye (165hrs) $25/hr $4,200 Total Labor Cost: $8,400 6 Thyristors $1.3 $8.00 PIC ProtoBoard 1 PIC16C73B processor $10 $10 2 TLP2200 Optoisolators $5 $ SCR Gate Drivers $5 $5 1 LCD $15 $15 Total Compoet Costs: 43 Proposed Budget Schedulig ad Milestoes Detail Schedule Schedulig ad Milestoes Methods 04/04 05/04 09/04 10/04 11/04 12/04 Review ad Research xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Matlab System Model xxxxxxxxxxxxxxxxxxxxx Desig ad PIC16C73B Implemet xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Close Loop Cotrol Implemetatio xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Voltage Scalability ad User Friedly Commad Structure Upgrade SCR ad Istall Protectio xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx Testig xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Behid the schedule Immediate goals (before April 26): Fialize compoet selectio Order compoets Implemetatio of all required hardware compoets for workig model Begi programmig of the microcotroller Test ad evaluate workig model Future Goals Implemetatio of the PLL i the processor icludig voltage cotrol Implemetatio of the user iterface peripherals (LCD, Keypad) Successful coordiatio of rectifyig hardware ad cotrollig software Title goes here 6

7 QUESTIONS? Thak you for your iput ad time! Title goes here 7