Scalable Regulated Three Phase Power Rectifier

Transcription

1 Scalable Regulated Three Phase Power Rectifier ECE 481 Senior Design Final Presentation Tyler Budzianowski & Tao Nguyen Dec 7, 2004 Instructor: Dr. Jim Frenzel Technical Advisors: Dr. Herb Hess and Dr. Richard Wall Sponsors: Dr. Herb Hess and Dr. Richard Wall

2 Presentation Outline Introduction to project Project objectives and specifications Product applications Design approach Implementation details and features including testing methods and summary of results Summary of overall project results Summary of expenditures Scheduling and milestones?

3 Introduction Purpose of the project To upgrade an original design for a microcontroller based three phase rectifier as outlined in a paper authored by Dr. Richard Wall and Dr. Herb Hess Product Applications - Any electrical application where a variable DC output voltage must be obtained from a three phase AC power line - DC motor drive applications based on a three phase AC source

4 Project Objectives Upgrade zero-crossing detection method Replace the system with a modern and less expensive microcontroller Implementation of closed-loop control for voltage/current regulation Upgrade the SCR gate firing architecture Installation of snubbing and protection for SCRs Generation of a MATLAB-based PLL model

5 Design Approach: Upgrade hardware components of entire system and apply more accurate hardware implementation methods that are available Replace the original processor with a new microcontroller Use commercially available components where applicable Increase usability for the customer

6 System Schematic m o v m o v m o v Output Load 7805 Zero Crossing Detector 24 Vcd Power Supply m o v m o v m o v LM317 Inputs PIC ucontroller O u t p u t s C M O S Interface CKT Gate Firing Circuit Board FC0-AUX60 KEYPAD LCD

7 Implementation of modern, less expensive microcontroller A Microchip PIC16C74B microcontroller has the necessary functionality to accurately control the three phase rectification process At approximately $10 per unit, the system is inexpensive and widely available

8 Test: Using a function generator, a 5 V square pulse signal into the PIC16C74B PORTA should produce 6 individual firing pulses on the output PORTD (RD0-RD5) These output pulses can be analyzed with an oscilloscope to ensure that they are out of phase by the desired angle (ex: 60 ) and compared with the 60 Hz input signal. To test closed loop operation, the phase error of the initial value into the phase locked loop should be zero when compared to the feedback value of the output.

9 Results: Initially, the microcontroller did produce six individual firing outputs running in an open loop process based entirely on the 60 Hz input signal pulse The open loop process does not compensate for any zero crossing detection errors. The closed loop implementation was not successful The application and implementation of a user friendly input structure and visual display was not achieved.

10 Closed loop control for voltage/current regulation A digital phase locked loop implemented within the microcontroller software is intended to accurately predict the next possible zero crossing time to compensate for any physical errors/inaccuracies in the zero crossing detection circuit MATLAB was used to model this behavior (to be discussed later)

11 Zero-Crossing detector Converts the input AC line signal to a digital representation with minimal error A dynamic hysteresis comparator circuit was designed to provide a more accurate alternative to the original optoisolator device configuration

12 Test: Must interface a three phase AC sinusoidal line and produce a digital 5V logic level output signal that matches the detected zero crossings of the sinusoidal input Must detect the positive rising edge zero crossing and negative falling edge zero crossing points with minimal error Forward schottky diode voltage should be approximately 1 volt max for an input of 30 ma, and 0.3 volt max for an input of 1 ma

13 Results: Input (3V) & Output (5V) vs. Time Volts (V) 6.00E E E E E E E E E E E E E E E E+00 Time (s) Input Output Successfully produces a 5V logic output based on approximate input signal zero crossings Forward schottky diode voltage is approximately 1V for a 30 ma input There is a slight offset error present with the actual zero crossing of the input line signal and the output square pulse signal

14 Input & Output of Zero Crossing Detector vs. Time (R1 = 170kohm) 2.50E E E+00 Volt (V) 1.00E E-01 Vout Vin 0.00E E E E E E E E E E E E E E+00 Time (Second) Input and Output of the Zero Crossing Detector (Without input resistance [R1 =0]) Volt (V) 2.50E E E E E E E E E E E E E E-02 Time (Sec) Output Input

15 SCR gate firing architecture Amplifies a lower voltage logic level signal to a level that will consistently trigger the gate of an SCR 2 Key Components: - A commercially available Enerpro FCO-AUX60 gate firing circuit was selected as the primary gate firing driver - A MOSFET based amplifier was designed to amplify the 5 V logic PIC output to a 12V logic signal that is usable by the FCO-AUX60 board

16 Enerpro FCO-AUX60 Auxiliary Firing Board Schematic:

17 MOSFET 5V/12V interface circuit Consists of 2 N-Channel (BS170) FETs and a single P- Channel (BS250P) FET configuration, 3 resistors, and an LM317 variable supply voltage regulator (12 V) Single Stage Schematic

18 Test: A 5 V logic high input should produce an identical but 12V magnitude high output A 0V logic low input should produce a 0V logic low output Switching times should be under 20 ns (physical limitation of transistors)

19 Results: Input (5V) and Output (12V) vs. Time Volt (V) 1.40E E E E E E E E E E E E E E E E E E E+00 Time (s) Output Signal Input Signal Does successfully amplify 5 V square pulses to 12 V square pulses as well as maintaining 0 V signal when the input is 0 V There may be a possible switching conflict due to excess charge buildup across the gates of the parallel transistor configuration

20 Input & Output of Interface Ckt. vs. Time 3.50E E+01 Voltage (V) 2.50E E E E E E E E E E E E E E E+01 Time (s) Input Output Some signal noise and ringing can be noticed trailing off upon close inspection

21 SCR Gate Trigger Inputs SCR and snubbing/protection circuit Consists of six of each: Teccor D4020L silicon-controlled rectifier diodes (SCRs) Snubbing resistors and capacitors (standard values) BC Components metal oxide varistors (MOVs) u u u Phase A Phase B Phase C LOAD u u u

22 Snubbing and protection Snubber circuit is designed to reduce and eliminate any harmful voltage/current transients that occur at SCR turn-on and turnoff points Metal-Oxide varistor devices are designed to absorb any fatal high voltage/current spikes before they can destroy the SCR devices.

23 Test: The SCR should turn on only when a positive forward voltage is applied to the SCR s gate, regardless of the voltage magnitude across the SCR (from anode to cathode) The device should turn off when there is no voltage signal applied to the gate The snubber configuration should absorb any signal transients at SCR turn on and turn off times/points The MOV should absorb (destroy itself) at voltage levels above 230 VAC Single SCR Schematic: MOV + Vo u mA Variable AC V1 0.7Vdc V2

24 Results: The SCR turns on when a forward voltage is applied to the gate (and a voltage is applied across the anode and cathode) The SCR turns off when the power supply to the gate is removed It is difficult to determine whether signal transients are present within the system to verify snubber functionality Because a high enough voltage spike could not be applied to the system, the full functionality of the MOV could not be confirmed

25 MATLAB based phase locked loop model DPLL consists of three functional units: Phase Detector (PD) Digital Loop Filter (DLF) Voltage Controlled Oscillator (VCO) C1 Input-Ph C2 Product 1 z Unit Delay Constant 1 1 z Unit Delay1 OutputPhase To Workspace Product1

26 Parameters in DPLL C1 and C2 are coefficients/parameters of the digital filter C is a constant value that determines the center frequency (fc) of the DPLL Behavior of the output is dependent on these parameters Some values of C1 and C2 can cause the error to oscillate. Values of C1 and C2 can be found if sampling freq. (fs) greater than the center freq. (fc) According to final theorem, phase error is zero

27 DPLL Analysis C 2 = 2*n*w n* T Where T=1/f s C 1 =(C 2 ) 2 /(4*n 2 ) Where w n =2*pi*f n 2C 2-4 < C 2 ; C 1 >0 Eqt (1) H( z) Φo ( Z ) Φi( Z ) = C. 2 ( Z 1 ) C1 ( Z 1 ) 2 C. 2 ( Z 1 ) C 1 Eqt (2) H( s) := 2 n ω n S + ( ) 2 ω n ( ) 2 S n ω n S + ω n Figure 1. Stable region of the output digital filter

28 Test: Filter output must be stabilized Locking time duration must be small (< 0.5 Second) Frequency and phase of input signal and output signal must be locked Phase error must be small (approx. 0)

29 Results: For n=17, Fs=8000Hz and Fc= 69Hz, c2 = c1 = Oscilation, Phase_err=0.04, Locking time = 0.4 Second When n=4, Fs=8000Hz and Fc=69Hz c2 = c1 = Oscillation, Phase_err=0.08, Locking time = 0.12 Second

30 Results Filter output is stable and oscillating Locking time is very small and dependent on the value of n Frequency of input and output signal is locked Small phase error is detected If n increases, locking time increases, and error decreases, just as error increases and locking time decreases if n decreases

31 Summary of project results Designed and working: - MOSFET interface circuit - Single SCR circuit configuration - MATLAB simulation model - Zero crossing detector Designed but not working: - Microcontroller system utilizing closed loop control - Entire system as a whole (6 firing SCRs)

32 Project Budget Summary Components Price/unit Cost 1 Gate Firing Circuit Board 1 Demo Board for PIC 1 Omron 24 Vdc Supply 1 12Vdc Power Supply 1 Key Pad 1 LCD 1 PIC16C74 processor 12 BS250P P MOSFETs 10 x 4020L SCRs Resistors & Capacitors 10 MOVs 12 BS170 N MOSFETs 6 Schottky Diodes 1 Comparator circuit Voltage Regulator Total Cost $ $ $41.80 $14.95 $14.95 $14.91 $12.73 $0.96 $1.80 Approx. $0.46 $0.33 $0.44 $1.10 $0.99 $ $ $41.80 $14.95 $14.95 $14.91 $12.73 $11.52 $10.80 $10.00 $4.56 $3.96 $2.64 $1.10 $0.99 $541.74

33 Schedule and Milestones Project Status Report 9/21 Lifecycle Report 10/5 Reliability Analysis Report 10/19 Test Plan Report 11/18 Final Demonstration 12/1 Final Presentation 12/7 Final Report 12/10

34 QUESTIONS and COMMENTS

35 Scalable Regulated Three Phase Power Rectifier ECE480 Senior Design Final Presentation Tyler Budzianowski & Tao Nguyen Dec 7, 2004 Instructor: Dr. Jim Frenzel Technical Advisors: Dr. Hess and Dr. Wall Sponsors: Dr. Hess and Dr. Wall