CHAPTER 4 MULTI-LEVEL INVERTER BASED DVR SYSTEM

Transcription

1 64 CHAPTER 4 MULTI-LEVEL INVERTER BASED DVR SYSTEM 4.1 INTRODUCTION Power electronic devices contribute an important part of harmonics in all kind of applications, such as power rectifiers, thyristor converters and SVC. The updated PWM techniques used to control modern static converters such as machine derives, power factor compensators, or active power filters do not produce perfect waveforms, which strongly depend on the semiconductors switching frequency. Voltage or current converters as they generate discrete output waveforms, force the use of machines with special isolation, and in some applications large inductances connected in series with the respective load. In other words, neither the voltage nor the current waveforms are as expected. Also, it is well known that distorted voltages and current waveforms produce harmonic contamination, additional power losses, and high frequency noise that can affect not only the power load but also the associated controllers. In this section, the enhancement of three phase voltage and reactive power is carried out with DVR when a non-linear and unbalanced load conditions are connected in the simulink block-set. A nine-level inverter is used to trigger the operation of DVR for the different load disturbance assessment by PWM technique. A practical implementation of the DVR is demonstrated with hardware at the last subsection of this chapter.

2 MULTI-LEVEL INVERTER CHARACTERISTICS Multi-level inverters have drawn tremendous interest in the power industry and are now becoming an established topology in higher power and higher voltage applications, such as HVDC Transmission, FACTS and high power variable speed drives. Compared with the traditional twolevel inverters, multi-level inverters offer better harmonic contents in the output voltage in a given switching frequency. The voltage stress across each switching device is reduced as the voltage levels increase. This leads to a possibility of raising the power rating of the inverter. Multi-level inverters can be mainly categorized into three topologies. They are diode-clamped multilevel inverters, flying-capacitors, multi-level inverters and cascaded multilevel inverters. Their circuit structures and basic operating principles are reviewed and presented next. The principal function of the inverters is to generate an AC voltage from a DC source voltage. If the DC voltage sources connected in series, it becomes possible to generate an output voltage with several steps. Multi-level inverters include an arrangement of semiconductors and DC voltage sources required to generate a staircase output voltage waveform. Figure 4.1 shows the schematic diagram of voltage source-inverters with a different number of levels. It is well known that a two-level inverter, such as the one shown in Figure 4.1.a, generates an output voltage with two different values (levels) V c and zero, with respect to the negative terminal of the DC source ( 0 ), while a three-level module, Figure 4.1(b) generates three different voltages at the output (2Vc, V c and zero). The different positions of the ideal switches are implemented with a number of semiconductors that are in direct relation with the output voltage number of levels.

3 66 Figure 4.1 Basic Multi-level inverters (a) two-levels, (b) three-levels and (c) m-levels Figure 4.2 Voltage waveform from an 11-level inverter

4 67 Multi-level inverters are implemented with small DC sources to form a staircase AC waveform, which follows a given reference template. For example, having ten DC sources with magnitudes equal to 20 V each a composed 11-level waveform can be obtained (five positives, five negatives and zero with respect to the middle point between the ten sources), generating a sinusoidal waveform with 100 V amplitude as shown in Figure 4.2, and with very low THD. It can be observed that the larger the number of the inverter DC supplies, the greater the number of steps that can be generated, obtaining smaller harmonic distortion. However the number of DC sources is directly related to the number of levels through the equation: n = m 1 (4.1) where, n is the number of DC supplies connected in series and m is the number of the output voltage levels. In order to get a 51-level inverter output voltage, 50 Voltage supplies would be required, which is too much for a simple topology. Besides the problem of having to use too many power supplies to get a multi-level inverter, there is a second problem which is also important, the number of power semiconductors required to implement the commutator, as shown in Figure Diode-clamped Inverter This inverter consists of a number of semiconductors connected in series, and another identical number of voltage sources, also connected in series. These two chains are connected with diodes at the upper and lower semiconductors as shown in Figure 4.3. For an m-level converter, the requires number of transistors T is given by T = 2 (m 1) (4.2)

5 68 then, for example of a 51-level converter, 100 power transistors would be required (which is an enormous amount of switches to be controlled). One of the most utilized configurations with this topology is that of the three-level inverter, which is shown in Figure 4.4. The capacitors act like two DC sources connected in series. Thus, in the diagram, each capacitor accumulates ½ V DC, giving voltages at the output of ½ V DC, 0, or - ½ V DC with respect to the middle point between the capacitors. Figure 4.3 m-level diode clamped inverter

6 69 Figure 4.4 Three-level diode clamped inverter Figure 4.5 m-level capacitor clamped inverter

7 Capacitor-clamped Inverter This inverter has a similar structure to that of the diode-clamped, however it can generate the voltage steps with capacitors connected as shown in Figure 4.5. The problem with this converter is that it requires a large number of capacitors, which translates is that it requires a large number of capacitors, which translates to a bulky and expensive converter as compared with the diode-clamped inverter. Besides, the number of transistors used is the same with the diode-clamped inverter, and therefore, for a 51-level inverter, 100 power transistors are required. In order to overcome all these problems, a third topology, which will be called the transistor-clamped inverter will be presented and analyzed Transistor-Clamped Inverter The transistor-clamped inverter has the advantage of requiring the same number of power transistors as the levels generated, and therefore, the semiconductors are reduced by half with respect to the previous topologies. A 51-level converter requires 51 transistors (instead of 100 transistors). For an m-level transistor clamped inverter, this satisfies, T = m (4.3) In this topology, the control of the gates is very simple because only one power transistor is switched-on at a time. Then, there is a direct relation between the output voltage, V out and the transistor that has to be turned-on. However, and despite the excellent characteristics of this topology, the number of transistors is still too large to allow the implementation of a practical converter with more than 50 levels.

8 71 Figure 4.6 m-level H-bridge inverter One solution for increasing the number of steps could be the use of H converters, like the one shown in Figure 4.6, which consists of connecting two of the previously discussed topologies in series (two legs). If transistor-clamped inverters are used to build an H converter, the number of transistors required for an m-level inverter is m+1, which means only one more transistor than what is required for a simple leg configuration. However, the number of DC source is reduced to 50%, which is the most important advantage of H converters. Another characteristic is that the H topology has many redundant combinations of switch positions to produce the same voltage levels. As an example, the level zero can be generated with switches in position S(1) and S(2), or S(3) and S(4), or S(5) and S(6), and so on. Another characteristic of

9 72 H converters is that they only produce an odd number of levels, which ensures the existence of the 0-V level at the load. Table 4.1 Component comparisons of the threem-level inverters Description Diode-clamped Flying-capacitor Cascaded Switching Devices 2 (m 1) 2 (m 1) 2 (m 1) Anti-parallel diodes 2 (m 1) 2 (m 1) 2 (m 1) Clamping Diodes (m 1) (m 2) Flying Capacitors ca (m 1) (m 2) / 2 DC Bus Capacitors (m 1) (m 1) (m 1)/2 Dc Supplies 1 1 (m 1) / 2 Table 4.1 shows the comparison of the component requirements among the above three multi-level inverters. All devices are assumed to have the same voltage rating. As shown in the table, the number of device increases when the required voltage level increases. Although the performance of the inverter would be better by increasing the number of levels, the cost and the circuit complexity would also increase. This makes the system unreasonable to implement when more levels are required. Tap changing transformers can give only magnitude variation. It cannot give voltage with variable phase angle. Multi-level inverter can give variable voltage and variable phase angle. From the above table it can be found that the cascaded multi-level inverters required less number of diodes, flying capacitors and DC bus capacitors. Since, this thesis proposes capacitors as DC supply, using (m-1)/2 capacitors will not affect the economy of the overall DVR system.

10 SIMULATION RESULTS AND DISCUSSION The THD present in the output of H-bridge based DVR is high. In order to reduce the THD value further inverter configuration is improved by using a nine-level inverter. Hence this chapter discusses the usage of ninelevel inverter for the applications of the DVR. To design the pulse duration for nine level inverter system, one cycle, i.e., (20 ms) is divided in to 18 modes, therefore each mode is having 1.11 ms. The pulses are designed such that the duration of each mode is 1.11ms. The cascaded nine-level inverter has been simulated using MATLAB software. The simulation circuit is illustrated in Figure 4.7. The voltage of the cascaded nine-level inverter can be synthesized from the following switching combinations. The Table 4.2 shows the switching sequence of nine-level inverter. Driving pulse sequence is selected such that nine-level output is obtained. Equal pulse width modulation technique is used. The driving pulses for switches S1 and S2 are shown in following Figure 4.8. The driving pulses for switches S5 and S6 are shown in Figure 4.9. The Figure 4.10 shows the output voltage across inverter-1. The Figure 4.11 shows the output voltage across inverter-2. Nine-level inverter output is shown in Figure The frequency spectrum for the output of the inverter is shown in Figure The value of THD is 19.6%. In a three-phase inverter, THD is further reduced due to elimination of third harmonic voltage.

11 Figure 4.7 Simulation circuit of cascaded nine-level inverter 74

12 75 Table 4.2 Switching sequence of nine-level inverter Output Voltage (V) SWITCHING SEQUENCE S1 S2 S3 S4 S5 S6 S7 S V V V V V V V V V V V V V V

13 Figure 4.8 Driving pulses for S1 and S 2 76

14 Figure 4.9 Driving pulses for S 5 and S 6 77

15 Figure 4.10 Output voltage across inverter-1 78

16 Figure 4.11 Output voltage across inverter-2 79

17 80 Figure 4.12 Output of nine-level inverter Figure 4.13 Frequency spectrum for output voltage

18 Figure 4.14 DVR using nine-level inverter with RL load 81

19 82 Figure 4.15 Nine-level inverter Figure 4.14 shows nine-level inverter based DVR system with RL load. Here single pulse PWM method is used. Figure 4.15 shows the ninelevel inverter circuit and Figure 4.16 shows the output voltage of nine-level inverter. Figure 4.17 shows the output voltage across load-1 and load-2. Upto 0.2 sec, load-1 is connected.at t=0.2 sec additional load (load-2) is connected. As a result voltage sag occurs. At t=0.4 sec the DVR is connected and as a result voltage gets compensated. Figure 4.18 shows the FFT analysis of line voltage. It has THD of 4.41%. This THD is very less compared to H-bridge based DVR.

20 83 Figure 4.16 Nine-level inverter output Figure 4.17 Voltage across load-1 and load-2

21 84 Figure 4.18 FFT analysis for output voltage Figure 4.19 shows the nine-level inverter based DVR with non-linear load. Figure 4.20 shows the output voltage across load-1 and load-2. Here single pulse PWM method is used.upto 0.2 sec, load-1 is connected and at t=0.2 sec, load-2 is connected. As a result voltage sag occurs. At t=0.4 sec, the DVR is connected and as a result voltage gets compensated. Figure 4.21 shows the FFT analysis of line voltage. It has THD of 16.97%. This is lesser compared to H-bridge inverter based DVR.

22 Figure 4.19 DVR with non-linear load 85

23 86 Figure 4.20 Voltage across load-1 and load-2 Figure 4.21 FFT analysis for output voltage

24 87 The above simulation results show that, the nine-level inverter compensates the voltage sag satisfactorily in short period, i.e., with in the permissible limit and at very low THD, compare to that of H-bridge inverter. Hence, in this section, simulation is further extended to a three phase system without and with nine-level inverter based DVR device. The performance analysis of the DVR is discussed through the following case studies: i) unbalanced load condition ii) increase in load and non linear load conditions Case Study I: Unbalanced Load Condition Figure 4.22 shows the schematic diagram of a three phase system developed using simulink block-set. In this diagram, a three phase source is connected to a three phase load through a transmission line. The system is connected with unbalanced linear load as shown in the schematic diagram. The system is executed in the MATLAB environment, to determine the Voltage and current levels in the power components. The scopes in the diagram illustrate the three phase voltage and current waveforms during the unbalanced condition as given in figures 4.23 & 4.24 respectively. To demonstrate the unbalanced condition in the three phase system and to improve the voltage and reduce THD, a DVR is connected as shown in Figure Pulse width modulation technique is used to adjust the firing angle and the DVR through nine level inverter and the obtained balanced three phase voltage and current were form are given in Figures 4.26 & Table 4.3 summarizes the enhancement of three-phase voltage with and without connecting the DVR in the system. Hence it is inferred that the unbalanced voltage is rectified by adding the DVR in the three-phase system.

25 88 Figure phase system without DVR at unbalanced condition Figure 4.23 Three phase unbalanced voltage

26 89 Figure 4.24 Three-phase unbalanced current.

27 Figure 4.25 Three phase system with DVR 90

28 91 Figure 4.26 Three-phase unbalanced voltage Figure 4.27 Three phase unbalanced current

29 92 Table 4.3 Phase voltage variations without and with DVR PHASE VOLTAGE WITHOUT DVR (Volts) WITH DVR (Volts) V a V b V c Case Study II: Increased in Load and Non-linear Load Conditions In this subsection, the influence of DVR is analysed when the system is connected to increase in load and non-linear (rectifier) load condition. Figure 4.28 shows the Simulink diagram of the three-phase system when connected with a non-linear load condition. A rectifier is connected in parallel with a capacitor and this combination is connected in parallel with a resistive load. The effect of the rectifier charges/discharge through the capacitor and the output is taken in the resistor terminals. The impact of nonlinear load is studied with DVR connection. The switch connected below to the rectifier load is closed to connect the additional load in the system. In this case study, the additional load is connected after the time t = 0.75 seconds with the already connected non-linear load in the system. Figures 4.29 to 4.31 show the voltage, current and power tracings of the system, when the above loads are connected in the system. From Figures 4.29 & 4.30, it is inferred that the voltage and currents are distorted due to the non-linear and increase in load conditions. The spectrum analysis is also given in Figure It is inferred that the predominant harmonic components are within permissible limits. Hence the impact of DVR on non-linear load study is illustrated.

30 Figure 4.28 Three phase system without DVR with non-linear load 93

31 94 Figure 4.29 Three phase line voltage with non linear load Figure 4.30 Three phase current with non linear load

32 95 Figure 4.31 FFT analysis for voltage The DVR connected in the three phase system and the connections of the nine-level inverter are given in the Simulink blocks in Figures 4.32 & To study the voltage sag & THD performance of DVR, a 3 phase system is connected to the non-linear load. After the time interval of t = 0.75s, an additional load is connected with the non-linear load. DVR is connected in the system at t = 0.85s to improve the voltage profile and damp at the system parameters oscillation. When there is a change in load condition, the corresponding changes in the inverter voltage happened as illustrated in Figure The three phase voltage and current profiles are settled down with non-linear and increased in load conditions after connecting the DVR as illustrated in the Figures 4.35 & To illustrate the power quality of the system with non-linear load, the voltage harmonic analysis at this load condition is given in Figure From this Figure, it is observed that the predominant harmonics is considerably reduced after connecting to DVR in the three phase system with non-linear and increased in load conditions.

33 Figure 4.32 Three phase system with DVR for non-linear load 96

34 97 Figure 4.33 Nine-level inverter Figure 4.34 Inverter output voltage

35 98 Figure 4.35 Three phase balanced voltage waveform Figure 4.36 Three phase current waveform

36 99 Figure 4.37 FFT analysis for voltage SIMULATION OF 8-BUS SYSTEM WITHOUT DVR Figure 4.38 shows the 8 bus system without DVR. The system consists of three generator buses and five load buses. Additional load is connected at t = 0.2 seconds. As a result the load voltage is changed across the load in each bus. Voltage at bus 4 is shown in Figure RMS value of voltage at bus 4 is shown in Figure RMS value decreases when the additional load is applied. Voltage at bus 7 is shown in Figure RMS value of voltage at bus 7 is shown in Figure The above mentioned figures show that additional loads affect the voltage in other busses also. To tackle the voltage sag DVR is introduced to the system in the next simulation.

37 100 Figure 4.38 Eight bus system without DVR. Figure 4.39 Voltage at bus-4

38 101 Figure 4.40 RMS value of voltage at bus-4 Figure 4.41 Voltage at bus-7

39 102 Figure 4.42 RMS value of voltage at bus-7 SIMULATION OF 8-BUS SYSTEM WITH DVR Figure 4.43 shows the 8 bus system with DVR. Figure 4.44 shows nine-level inverter based DVR circuit. The system consists of three generator buses and five load buses and two nine level inverter based DVR The load is increased at t = 0.2 seconds. As a result the load voltage and power are changed across the load in each bus. The DVRs are connected between bus 1 & 7 and bus 3 & 4. After compensation the voltage is maintained at original level. Figures 4.45 and 4.46 show the instantaneous and RMS voltage in bus 4. Figures 4.47, 4.48 show the instantaneous and RMS voltage in bus 7. Figures 4.47, 4.48 show the instantaneous and RMS voltage in bus 8. Table 4.4 shows the variation in voltage with and without DVR system at different busses.

40 103 Figure 4.43 Eight bus system with DVR Figure 4.44 Nine-level inverter based DVR circuit

41 104 Figure 4.45 Voltage at bus-4 Figure 4.46 RMS value of voltage at bus-4

42 105 Figure 4.47 Voltage at bus-7 Figure 4.48 RMS value of voltage at bus-7

43 106 Figure 4.49 Voltage at bus-8 Figure 4.50 RMS value of voltage at bus-8

44 107 Table 4.4 Variation in voltages at different busses with and without DVR Bus No. without DVR Bus voltage (KV) with DVR The nine-level inverter based DVR for 8 bus system has improved the voltage sag produced by external disturbances introduced to the system. Hence it is proved that nine-level inverter based DVR system can tackle the voltage sag issue at various busses in a multi-bus system. This helps the electrical utility to supply power to the customers with better quality. 4.4 EXPERIMENTAL RESULTS A laboratory model for nine-level inverter is fabricated and tested. The hardware consists of power supply board, MOSFET board and Driver IC board. The pulses required by the MOSFETs are generated by using microcontroller PIC16F84, features and description of the same is given in appendix 3. The control circuit is shown in Figure The regulators 7812 and 7805 supply the voltage required by the IC 2110 and IC 16F84. Crystal and capacitors are connected to generate the clock. Pulses from the port A are amplified. The flow chart of the microcontroller is shown in Figure Delay subroutine is given in Figure Assembly language program is given in Appendix 7. Experimental set up is shown in Figure The pulses are amplified using the driver IC IR2110. Driving pulses for S 1 and S 5 are shown in Figures 4.55 and 4.56 respectively. Output voltage of inverter 1 is

45 108 shown in Figure Output voltage of inverter-2 is shown in Figure Nine-level output is shown in Figure D1 D V AC Supply 230V/15V C V 560 LED D4 D RA2 RA Driver IC IR k C2 S1 C5 10uF uF 33pF C8 0 C9 33pF PIC MICROCONTROLLER PIC16F84A RA1 RA C6 47uF C7 47uF Driver IC IR k 1k C3 47uF 1k S2 S3 C4 10uF S4 Figure 4.51 Control circuit

46 109 FLOW CHART START PORT INITIALIZATION CALCULATE DELAY1, DELAY 2, DELAY3, DELAY4 AND DELAY5 OUT DATA 00H D CALL DELAY 1 OUT DATA 44H CALL DELAY 2 OUT DATA 99H CALL DELAY 3 A

47 110 Figure 4.52 Flow chart of main routine A OUT DATA 11H CALL DELAY 4 OUT DATA 55H CALL DELAY 5 OUT DATA 11H CALL DELAY 4 OUT DATA 99H CALL DELAY 3 OUT DATA 44H CALL DELAY 2 B

48 111 Figure 4.52 (Continued) B OUT DATA 00H CALL DELAY 1 OUT DATA 00H CALL DELAY 1 OUT DATA 88H CALL DELAY 2 OUT DATA 66H CALL DELAY 3 OUT DATA 22H CALL DELAY 4 C

49 112 Figure 4.52 (Continued) C OUT DATA AAH CALL DELAY 5 OUT DATA 22H CALL DELAY 4 OUT DATA 66H CALL DELAY 3 OUT DATA 88H CALL DELAY 2 OUT DATA 00H CALL DELAY 1 S JUMP D

50 113 Figure 4.52 (Continued) DELAY SUBROUTINE COUNT DEC COUNT NO IS COUNT =0? YES RETURN Figure 4.53 Delay Subroutine

51 114 Figure 4.54 Experimental set-up Amplitude 1 unit=5 V Time 1 unit = 5 ms Figure 4.55 Driving pulse for S1

52 Amplitude 1 unit=10 V 115 Time 1 unit = 5 ms Amplitude 1 unit= 10V Figure 4.56 Driving pulse for S5 Time 1 unit = 5 ms Figure 4.57 Output voltage of inverter-1

53 Amplitude 1 unit= 10V 116 Time 1 unit = 5 ms Amplitude 1 unit= 10V Figure 4.58 Output voltage of inverter-2 Time 1 unit = 5 ms Figure 4.59 Nine-level output

54 CONCLUSION In this Chapter, nine-level inverter is proposed for the DVR system. Multi-level inverters with large number of steps have been used in the DVR system. Multi-level inverter which requires minimum power supplies have been used in DVR system. MATLAB Simulink model for nine-level inverter system is developed. Pulse width in the hardware is designed based on the values obtained from simulation. This chapter gives simulation results of nine-level inverter based DVR. THD is found to be lesser than that of single pulse PWM inverter. The THD in the output of nine-level inverter is 8.9%. Therefore nine-level inverter gives the better solution to the voltage sag and harmonic issues. A hardware laboratory model for nine-level inverter is fabricated and the results are also presented. The results obtained from the simulation of nine-level inverter based DVR for 3 phase non-linear load, unbalanced load and increased in load conditions show that the voltage sag is mitigated and THD is maintained within the limit. Hence the nine-level inverter based DVR presents a viable solution to different disturbance conditions.