A Fast-Processing Modulation Strategy for Three-Phase Four-Leg Neutral-Point- Clamped Inverter Based on the Circuit-Level Decoupling Concept

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1 Dowloaded from orbit.dtu.dk o: Aug 22, 2018 A Fast-Processig Modulatio Strategy for Three-Phase Four-Leg Neutral-Poit- Clamed Iverter Based o the Circuit-Level Decoulig Cocet Ghoreishy, Hoda; Zhag, Zhe; Thomse, Ole Corelius; Aderse, Michael A. E. Published i: Proceedigs of The Iteratioal Power Electroics ad Motio Cotrol Coferece (IPEMC) Lik to article, DOI: /IPEMC Publicatio date: 2012 Documet Versio Publisher's PDF, also kow as Versio of record Lik back to DTU Orbit Citatio (APA): Ghoreishy, H., Zhag, Z., Thomse, O. C., & Aderse, M. A. E. (2012). A Fast-Processig Modulatio Strategy for Three-Phase Four-Leg Neutral-Poit-Clamed Iverter Based o the Circuit-Level Decoulig Cocet. I Proceedigs of The Iteratioal Power Electroics ad Motio Cotrol Coferece (IPEMC) (Chater 280,. 274). IEEE. DOI: /IPEMC Geeral rights Coyright ad moral rights for the ublicatios made accessible i the ublic ortal are retaied by the authors ad/or other coyright owers ad it is a coditio of accessig ublicatios that users recogise ad abide by the legal requiremets associated with these rights. Users may dowload ad rit oe coy of ay ublicatio from the ublic ortal for the urose of rivate study or research. You may ot further distribute the material or use it for ay rofit-makig activity or commercial gai You may freely distribute the URL idetifyig the ublicatio i the ublic ortal If you believe that this documet breaches coyright lease cotact us rovidig details, ad we will remove access to the work immediately ad ivestigate your claim.

2 2012 IEEE 7th Iteratioal Power Electroics ad Motio Cotrol Coferece - ECCE Asia Jue 2-5, 2012, Harbi, Chia A Fast-Processig Modulatio Strategy for Three- Phase Four-Leg Neutral-Poit-Clamed Iverter Based o the Circuit-Level Decoulig Cocet Hoda Ghoreishy, Zhe Zhag, Ole C. Thomse ad Michael A. E. Aderse Deartmet of Electrical Egieerig Techical Uiversity of Demark Kgs. Lygby, Demark (zz@elektro.dtu.dk) Abstract I this aer, a modulatio strategy based o the circuit-level decoulig cocet is roosed ad ivestigated for the three-level four-leg eutral-oit-clamed (NPC) iverter, with the aim of deliverig ower to all sorts of loads, liear/oliear ad balaced/ubalaced. By alyig the roosed modulatio strategy, the four-leg NPC iverter ca be decouled ito three three-level Buck coverters i each defied oeratig sectio. This makes the cotroller desig much simler comared to the covetioal four-leg NPC iverter cotrollers. Also, this techique ca be imlemeted with a simle logic ad ca be rocessed very quickly. Moreover, the switchig loss is reduced substatially ad the dc-lik caacitors voltages balace is also achieved without ay feedback cotrol. The roosed modulatio techique is verified by the eerimet. Keywords-circuit-level decoulig; iverter; eutral-oitclamed; PWM modulatio; three-level I. INTRODUCTION The eutral-oit-clam (NPC) iverter [1], [2], is the most etesively alied coverter toology at reset. However, the covetioal three-leg NPC iverters are ot suitable for three-hase four-wire systems [3]. The four-leg NPC iverter is a romisig toology comared to the three-leg NPC iverter i three-hase four-wire systems [4]-[6]. A great variety of modulatio methods available for this iverter ca be classified as ulse width modulatio (PWM) ad 3D sace vector modulatio (SVM) [4]-[7]. However, all these reviously roosed modulatio schemes have cosiderable disadvatages such as comlicated digital logic as i 3D SVM ad ocomlete utilizatio of the iverter caacity as i SPWM. A ew modulatio strategy for the three-level four-leg NPC iverter is itroduced i this aer ad a theoretical basis for the roosed strategy is develoed based o the aalysis of circuit-level decoulig method [8], [9]. The saliet features of the roosed strategy are the followig: The four-leg NPC iverter ca be decouled ito threelevel Buck coverters i every 60 o oeratig sectio of a fudametal cycle, which leads to a simler desig of closed-loo cotrollers; It rovides iheret caability to maitai the voltages of the DC caacitors equal without ay requiremet to additioal cotrol effort; As si of its sitee switches are ot oerated at switchig frequecy at ay istat, the switchig losses are reduced; Oly oe carrier wave is eeded for PWM sigal modulatig. Figure 1. Schematic of the three-hase four-leg NPC iverter toology. Figure 2. Waveform of the three-hase outut voltage. Figure 3. Vector diagram of the three-hase ouut voltages. This aer itroduces the circuit-level decoulig of the four-leg NPC iverter ad the modulatio strategy imlemetatio i sectio II, ad rovides the detailed aalysis o imlemetatio of the roosed PWM scheme i sectio III. Sectio IV resets the eerimetal results, ad fially sectio V cocludes this aer by highlightig the advatages of the roosed modulatio strategy. II. OPERATION PRINCIPLE OF THE PROPOSED PWM MODUALTION STRATGY A. Idea of the Circuit-Level Decoulig Scheme A three-level four-leg NPC iverter is deicted i Fig. 1. Well cotrolled, the iverter is able to geerate balaced ad high-quality AC outut voltages (as show i Fig. 2) irresective of the load coditio. These eected voltages are equivalet to a equilateral triagle i the vector lae as /11/$26.00@2012 IEEE

3 show i Fig. 3, where the three outside lies rereset lie voltages V AB, V BC ad V CA ad the three iside lies corresod to hase voltages V AO, V BO, ad V CO. It is foud that there are oly three ideedet lies withi this triagle. I other words, if the ositio ad legth of three ideedet lies are determied, the rest of the lies i the triagle are automatically settled [8]. This idicates that the active cotrol of ay two lie voltages ad oe-hase voltage ca lead to the full cotrol of a three-hase four-leg NPC iverter. Therefore, the circuit-level decoulig method for three-level NPC iverters roosed i [9], ca the be eteded to four-leg oes. As illustrated i Fig. 2, a lie eriod ca be divided ito si regios. By isectig the three-hase voltage waveforms i each regio, oe commo fact is foud that two hase voltages are always ositive ad the other oe is egative i regios I, III ad V (odd regios), whereas the oosite coditio ca be foud i regios II, IV ad VI (eve regios). This fact leads to the thought of ulse width modulatig the switches i the hases with same sigs while keeig the switches i the other hase steady state for etire or art of the regio. For this reaso, i the odd regios, the followig modulatio method is used: 1) The lowest hase voltage alog with its corresodig lie voltages are selected as the active voltages uder cotrol. 2) The switches T i3 ad T i4 (ia, b, c) for the hase with lowest voltage are always tured o, ad the corresodig T i1 ad T i2 for this hase are always tured off. 3) The switches for the other two hases ad also the eutral hase are cotrolled by SPWM scheme. With this treatmet, Fig. 1 is equivalet to Fig. 4 i regio I, which ca be further simlified ad orgaized ito Fig. 4, where S TLi(i1,2,3) is the equivalet sigle ole trile throw switch for each hase half bridge. The same equivalet circuit is also alicable to regios III ad V. While i eve regios, the voltage waveforms i Fig. 2 have the same atter ad the followig modulatio method is used: 1) The highest hase voltage alog with its corresodig lie voltages are selected as the active voltages uder cotrol. 2) The switches T i1 ad T i2 (ia, b, c) for the hase with highest voltage are always tured o, ad the corresodig T i3 ad T i4 for this hase are always tured off. 3) The switches of the other two hases ad also the eutral hase are cotrolled by SPWM scheme. I regio II, the four-leg iverter i Fig. 1 is equivalet to Fig. 5, ad hereby the simlified circuit with the model of the sigle ole trile throw switch is obtaied i Fig. 5. Similarly, the same equivalet circuit is alicable to regios IV ad VI as well. B. Oeratio Pricile of the Equavilet Coverters For a further aalysis o the oeratio riciles, the followig assumtios are made firstly: L A L B L C L, C A C B C C ad the switchig frequecy is much higher tha the fudametal frequecy. I regio I, it ca be see i Fig. 4 that V V AB, V V CB ad V V OB. Hereby, whe V m(m,,) E, the corresodig switch S TLm(m,,) is switched betwee the switchig odes P ad 0 with a duty cycle defied by d m(m,,) T op,m(m,,) /T s, where T op,m(m,,) is the coectio time with the switch ode P, ad T s is the switchig eriod. Accordig to the volt-secod balace ricile o iductors i Figure 4. Equivalet circuit of four-leg NPC iverter i regio I. Figure 5. Equivalet circuit of four-leg NPC iverter i regio II. a whole switchig eriod, the followig equatios ca be derived, ( 2E V ). d + ( E V ).(1 d ) 0 (1) ( 2E V ). d + ( E V ).(1 d ) 0 (2) ( 2E V ). d + ( E V ).(1 d ) 0 (3) 275

4 The, the duty cycles are eressed d V V V ; d ; d (4) E E E O the cotrary, whe V m(m,,) <E, the corresodig switch S TLm(m,,) is switched betwee the switchig odes 0 ad N with a duty cycle defied as d m(m,,) T o0,m(m,,) /T s, where T o0,m(m,,) is the coectio time with the switch ode 0. Accordig to the iductor volt-secod balace i a whole switchig eriod, the followig equatios ca be derived, ( E V ). d + (0 V ).(1 d ) 0 (5) ( E V ). d + (0 V ).(1 d ) 0 (6) ( E V ). d + (0 V ).(1 d ) 0 (7) Corresodigly, the duty cycles are eressed V V V d ; d ; d (8) E E E Hece, (4) ad (8) costitute the relatioshi of three three-level Buck coverters ad to make this coclusio eve clearer the equivalet circuit of hase leg a ad the tyical waveforms for V AB (V ) as a eamle are lotted i Fig. 6. I regio II, as show i Fig. 5, the active lie voltages ad hase voltage are V BA ( V ), V BA ( V ) ad V AO ( V ), resectively. Accordigly, if V m(m,,) E, the equivalet switch S TLm(m,,) will be switched betwee the termials N ad 0 with the duty cycle d m(m,,) T on,m(m,,) /T s. Otherwise, if V m(m,,) > E, S TLm(m,,) will be switched betwee the termials 0 ad P with the duty cycle d m(m,,) T o0,m(m,,) /T s. I order to obtai the steady state trasfer fuctios from duty cycles to iut/outut voltages, the volt-secod balace ricile is adoted agai, the same duty cycle descritios as i regio I ca be obtaied below. d d d VBA + E V VCA + E V VOA + E V AB AC AO V E E V E E V E E (9) V V BA VAB d E E VCA VAC V d', (10) E E VOA VAO V d' E E It is clear that i regio II the four-leg NPC iverter ca also be decouled ito three three-level Buck coverters. As a eamle, the equivalet circuit of hase leg b ad the tyical waveforms for the outut voltage V BA ( V ) are lotted i Fig. 7 to reset the decoulig effect. Alyig the same aalysis to oe etire fudametal cycle, the reresetatio of the decouled three-level Buck coverters for the four-leg NPC iverter ca be derived i every 60 o regio. Also, cotroller desig ad selectio of the Figure 6. Equivalet circuit, cotrol strategy ad tyical waveforms for outut voltage V AB (V ) i regio I. Figure 7. Equivalet circuit, cotrol strategy ad tyical waveforms for outut voltage V BA (-V ) i regio II. outut filter arameters L ad C ca thereby follow the same rules as those for three-level DC-DC coverters. C. Average NP voltage self-balacig ability The mai techical challege i ay alicatio of the NPC iverter is to maitai the voltages of the two DC-side caacitors equal ad at a re-secified level. Whe the four-leg NPC iverter coects with the threehase balaced load, i L equals to zero, so it will ot affect the NP voltage. Uder this case, by isectig refereces listed i Table I, it ca be see that i the adjacet two regios the cotrol sigals are always same, for istace, i regios I ad II the lie voltage V AB is adoted as the sigal CON. A socalled aode three-level Buck coverter (A-TLBC) ad a cathode three-level Buck coverter (C-TLBC) ca be obtaied [10]. Furthermore, both of the three-level Buck coverters ca be combied ito oe coverter with commo iut dividig caacitors. Thus, by rotatig the eergy rovisio burde betwee these caacitors through the adjacet oeratig regios, the two dividig caacitors will rovide, o average, a equal amout of eergy to the load, which allows them to maitai a balace voltage over time, thereby the voltage of the dividig caacitors ca be balaced aturally, so ay additioal feedback or feed-forward cotrol is ot eeded. Moreover, as the aalyzed results i [9], the frequecy of NP voltage rile is 150 Hz. 276

5 Voltage (V) v C1 v C2 Time (s) Voltage (V) v C1 v C2 Voltage (V) v C1 v C2 Time (s) Time (s) (c) Figure 8. Simulated waveforms of DC-side voltage balacig. with threehase load, with two-hase load, ad (c) with oly hase-c load. Whe there is a load imbalace, the eutral curret i L will vary the NP voltage rile frequecy as well as the rile magitude. But the voltages of the two DC-side caacitors ca still maitai equal, because the cotrol sigal of the eutral hase CON i the first half fudametal eriod has symmetrical hase voltage sequece with that i the secod oe, i.e. V BO, V AO, V CO i the regios I, II, III, ad V BO, V AO, V CO i the regios IV, V, VI, resectively. Hece, the variatio frequecy of CON is 50 Hz ad it ca decide the NP voltage rile frequecy which is also 50 Hz. More detailed quatitive aalysis o NP voltage variatio ad DC bus curret rile will ot be reseted i this aer. To verify the aalysis above, the four-leg NPC iverter is simulated by Matlab. The adoted simulatio arameters are: Wye-coected resistive-iductive load 15Ω/23mH er hase, 250VAC/50Hz outut voltage, DC-side caacitors C 1 C µF, ad the iitial voltages across C 1 ad C 2 V C1 250VDC ad V C2 150VDC, resectively. The trasiet waveforms of the DC-side voltage balacig are show i Fig. 8 ad the differeces of those waveforms, such as shae, rile frequecy ad magitude, ad trasiet time, ca be observed clearly. III. IMPLEMENTATION OF THE PROPOSED MODULATION STRATEGY A. Imlemetatio of Modulator Fig. 9 shows the roosed modulator for the four-leg NPC iverter, which is resosible to determie the decoule logic ad distribute the corresodig drivig sigals. It cosists of a regio selector, a carrier sigal selector, a PWM geerator ad a gate sigal distributor. If the feedback cotroller is desiged, oututs of the desiged cotroller (curret ad/or voltage sigals) ca be coected ito the carrier sigal selector. The regio selector determies the active workig regio, as show i Fig. 2, by detectig the zero-crossig oit of the eected Figure 9. The block diagram of the roosed modulator. TABLE I. SYNTHESIS OF THE DRIVING SIGNALS Regio Selector Cotrol Sigal Selector Gate Sigal Distributer Regios CON CON CON or d d d or d d or d dt E + VAB-E VCB-E -VBO-E dta1, dtc1, dt1, Tb3Tb41 I Ta21 Tc21 T21 E - VAB VCB -VBO d Ta2, d Tc2, d T2, Ta10 Tc10 T10 E + VAB-E VAC-E VAO-E dtb4, dtc4, dt4, Ta1Ta21 II E - Tb31 Tc31 T31 VAB VAC VAO d Tb3, d Tc3, d T3, Tb40 Tc40 T40 E + VBC-E VAC-E -VCO-E dtb1, dta1, dt1, Tc3Tc41 III E - Tb21 Ta21 T21 VBC VAC -VCO d Tb2, d Ta2, d T2, Tb10 Ta10 T10 E + VBC-E VBA-E VBO-E dtc4, dta4, dt4, Tb1Tb11 IV E - Tc31 Ta31 T31 VBC VBA VBO d Tc3, d Ta3, d T3, Tc40 Ta40 T40 E + VCA-E VBA-E -VAO-E dtc1, dtb1, dt1, Ta3Ta41 V E - Tc21 Tb21 T21 VCA VBA -VAO d Tc2, d Tb2, d T2, Tc10 Tb10 T10 E + VCA-E VCB-E VCO-E dta4, dtb4, dt4, Tc1Tc21 VI E - Ta31 Tb31 T31 VCA VCB VCO d Ta3, d Tb3, d T3, Ta40 Tb40 T40 outut AC voltages. The carrier sigal selector selects the active cotrol sigals (modulatio referece waves), which are rereseted by CON, CON ad CON. Moreover, it also selects the switchig ositio sigal E + or E, which idicates that the half of DC bus voltage E is larger or smaller tha the corresodig outut lie voltage. The selected cotrol ad referece sigals are rocessed by the PWM geerator to geerate the duty-ratio sigals. The gate sigal distributor seds these duty-ratio sigals to the gate driver circuits i order to trigger the aroriate switches of the sitee trasistors T a1 ~T c4 ad T 1 ~T 4 accordig to the iformatio from the regio selector ad the carrier sigal selector. I Table I, the selected lie voltages that act as oututs of the equivalet decouled circuits i every regio are listed, which also deeds o the switchig-ositio sigals; the assigmet of duty cycles of the active switches i.e. d, d, d, d, d, d, is listed i Table I as well; d t, which equals 1, is allocated to the switch that is always o i the iactive hase. Comarig to the 3D-SVM-based modulator, the modulator roosed i this aer ca be eve imlemeted by a simle logic ad a aalogue circuit. The algorithm of modulator is simle ad thereby it ca be rocessed very quickly. As for the closed-loo cotroller desig, the desig methods for threelevel DC-DC coverters ca be utilized easily to imlemet outut voltage cotrol of the four-leg NPC iverter due to the circuit decoulig cocet, ad thereby a high-seed DSP accomaied with a high samlig-rate A/D coverter to achieve coordiate trasformatio is o more eeded. 277

6 B. Aalysis of Modulatio Sigals From (4), (8), (9) ad (10), ad the cotrol sigals listed i Table I, it ca be foud that the modulatio refereces are always lie voltages for the switches i the legs a, b ad c, ad hase voltages for the switches i the fourth leg. At the limit, d 1 or d 1, the maimal outut lie voltage is to be 2E, which meas the maimal amlitude-modulatio ratio is: m vl l 3 E 2 E 3 E ma (11) (c) Therefore, (11) shows the maimum modulatio ide that is achievable for the liear-modulatio mode by the roosed strategy. This maimal value is also obtaied by 3D-SVMs or by other carrier-based PWM strategies with a roer zerosequece sigal ijectio. The aftermetioed modulatio ide m i this aer is eressed by ormalizig with resect to this maimum value m ma. Fig. 10, illustrates the modulatio sigals for switches T a1, T a2, T 1, ad T 2 i the hase legs a ad, for differet modulatio idices. It is clear that (1) lie voltages are used as the modulatio refereces for T a1 ad T a2, ad hase voltages are alied as refereces for T 1 ad T 2 ; (2) T a1 ad T a2 have o switchig actios i regios II ad V; (3) modulatio sigals are withi the rage [0, 1], so all the refereces ca share oe commo carrier wave. Hece, the modulatio sigals for the switches located i hase legs b ad c ca be obtaied by ±120 o hase-shiftig with resect to the modulatio sigals of hase leg a, resectively. While comlicated i shae, sice the equatios describig the fuctios are relatively simle sectios of siusoids, they ca be readily imlemeted i real-time digital form. C. Imlemetatio of Closed-Loo Cotrol I this aer, the modulator ad closed-loo cotroller are imlemeted digitally by a TMS320F28335 ezds. The system closed loo cotrol block diagram has bee reseted i Fig.11. Accordig to system erformace, cotrol variables are the three-hase outut voltages (V abc ). The cotrol is erformed i the sychroous rotatig frame which coverts measured AC values ito the DC oes. This allows the use of covetioal Proortioal-Itegral (PI) cotrollers achievig zero steady state error. Accordig to Fig.11, the referece voltages (V abc *) alog with the measured outut voltages (V abcf ) are coverted ito V qd * ad V qdf resectively. Comarig the referece ad actual values of the coverted voltages, the error sigals are geerated. The geerated error sigals are assed through PI cotrollers ad the required V qd values are obtaied. Covertig these values to V abc voltages, roer sigals for the carrier sigal selector block (Fig.8) are roduced. (d) Figure 10. Modulatio sigals of T a1, T a2, T 1 ad T 2 with differece modulatio idices. Figure 11. Block diagram of system closed loo cotrol. 278

7 IV. EXPERIMENTAL VERIFICATION The roosed modulatio techique has bee verified by eerimet from a rototye built i the lab. The arameters for the rototye are listed i Table II. The coverter oerates over both a Wye-coected resistive load ad a oliear load. TABLE II. PARAMETERS OF THE EXPERIMENT Outut ower Outut fudametal frequecy DC bus voltage Switchig frequecy Outut low-ass LC filter Digital sigal rocessor 1.5 kw 50 Hz 250 V DC 20 khz L AL BL C120 μh, C AC BC C40 μf TMS320F28335 ezds Fig. 12 shows the eerimetal results whe the rototye is tested with balaced resistive load ad the modulatio ide is 0.8. The outut hase voltage, the outut lie voltage ad the three hase siusoidal outut voltages are deicted i Fig. 12, ad (c), resectively. It ca be see that there are o switchig actios i hase leg a durig the oeratig regios II ad IV. Fig.13 ad reset the closed-loo cotrolled rototye s resose with the roosed modulatio strategy, whe it is tested uder balaced ad ubalaced resistive load. The to oe of the waveforms is outut voltage v BO, while the bottom three waveforms are three hase load currets i A, i B ad i C. Fig.13 shows the rototye s resose whe the load is ubalaced with two-hase load (hase B discoected) ad Fig.13 shows its resose with oe hase load (hases B ad C are discoected). I both of the cases, the outut voltage waveform demostrates a highquality siusoidal shae. Figure 13. Eerimetal results of outut voltage (v BO, [50 V/div]) ad currets (i A, i B, i C, 2 A/div) with ubalaced resistive load with two-hase load ad with oly oe hase load. (Time base: 20 ms/div). (c) (c) Figure 12. Eerimetal results with balaced resistive load outut hase voltage v az ad v AO [100 V/div], ouut lie voltage v ab ad v AB [100 V/div] ad (c) outut three-hase voltages v AO, v BO ad v CO [50 V/div]. (Time base: 5 ms/div) (d) Figure 14. Eerimetal results of outut voltage (v BO, [50 V/div]) ad currets (i A, i B, i C, 10 A/div, i X 20 A/div) whe the rototye tested uder sigle-hase oliear load. Circuit of sigle hase oliear load, with two-hase load ( hase B discoected), (c) with oe hase load ( both hase B ad hase C discoected), ad (d) currets i A ad i X with oe hase load (hase B ad hase C discoected). (Time bases: 20 ms/div for ad (c), 5 ms/div for (d) ). 279

8 Fig.14 -(d) roves the rototye s ubalaced ad oliear load hadlig caability with roosed modulatio strategy uder closed-loo cotrol. The three sigle hase oliear load adoted i the eerimet is reseted i Fig.14, which is realized by diode rectifiers followed by arallel-coected resistors ad 330 μf/400v caacitors. Each load is coected betwee oe of the outut hase termials A, B, C, ad the eutral termial O. I the Fig.14 ad (c) are the hase outut voltage v BO ad outut currets i A, i B, i C, ad i Fig.14 (d) deict outut currets i A ad eutral curret i X. Fig.14 shows the eerimetal results with two-hase oliear load ad the other hase oe, ad Fig.14 (c) resets the eerimetal results with oe hase oliear load ad the other two hases oe. It elores that the rototye with the roosed modulatio strategy is to be uaffected by ot oly oliear but also ubalaced loadig situatio. I Fig. 14 (d), it is clear that the ubalaced curret betwee the outut hases flows through the fourth leg of the NPC iverter. V. CONCLUSION This aer has itroduced a simle ad fast-rocessig PWM modulatio strategy for the three-hase four-leg NPC iverter. The roosed strategy emloys a circuit-level decoulig method ad is able to decoule the ower trai ito three three-level Buck coverters i every 60 o regio. The roosed modulatio strategy for the four-leg NPC iverter has followig advatages. (1) Fast-rocessig: the structure of modulator is simle ad the algorithm ca be imlemeted easily, ad oly oe carrier sigal is eeded; (2) Average NP voltage self-balacig: it ca kee the NP voltage at oe half of the DC-lik voltage without ay feedback or feed-forward cotrol; (3) Ecellet load hadlig caability: it ca geerate balaced high-quality outut voltage waveforms with all sorts of balaced/ubalaced as well as liear/oliear loads; (4) Low switchig losses: The switchig loss is reduced sigificatly by ot switchig the hases which have the highest or lowest voltages, ad also two of the switches i the fourth-leg are ot oerated with the switchig frequecy. The eerimetal results measured o the rototye built i the lab are rovided to suort the theoretical aalysis ad verify the roosed cocet. I additio, this decoulig cocet ca be eteded ad utilized i other multilevel (5- level, 7-level ) iverters or active PWM rectifiers. While the mai drawback of the roosed modulatio scheme is that the THD of outut voltage ad curret waveforms, which will varies with the modulatio ide, is worse whe modulatio idices are lower, like the covetioal discotiuous SPWM modulatio schemes. This feature will be studied i deth ad reorted i the future aers. REFERENCES [1] A. Nabae, I. Takahashi ad H. Akagi, A ew eutral-oit-clamed PWM iverter, IEEE Trasactios o Idustrial Alicatios, vol. 1A-17, o. 5, , Ste.-Oct [2] J. Rodriguez, S. Beret, P. K. Steimer ad I. E. Lizama, A survey o eutral-oit-clamed iverters, IEEE Trasactios o Idustrial Electroics, vol. 57, o. 7, , [3] J. Rodriguez, B. Wu, M. Rivera, A. Wilso, V. Yaramasu ad ch. Rojas, Model Predictive Cotrol of Three-Phase Four-Leg Neutral-Poit- Clamed Iverters, i Iteratioal Power Electroics Coferece, 2010, [4] J. Yao ad T. Gree, Three-Dimesioal Sace Vector Modulatio for a Four-Leg Three-Level Iverter, i IEEE Euroea Cof. o Power Electroics ad Alicatios, 2005, [5] S. Ceballos, J. Pou, E. Robles, J. Zaragoza, P. Ibaez ad J. L. Marti, Fault Tolerat Hybrid Four-Leg Multilevel Coverter, i IEEE Euroea Cof. o Power Electroics ad Alicatios, 2007, [6] S. Ceballos, J. Pou, J. Zaragoza, J. L. Marti, E. Robles, I. Gabiola ad P. Ibaez, Efficiet Modulatio Techique for a Four-Leg Fault Tolerat Neutral-Poit-Clamed Iverter, IEEE Trasactios o Idustrial Electroics, vol. 55, o. 3, , Mar [7] N. Dai, M. Wog ad Y. Ha, Alicatio of a Three-Level NPC Iverter as a Three-Phase Four-Wire Power Quality Comesator by Geeralized 3DSVM, IEEE Trasactios o Power Electroics, vol. 21, o. 2, , Mar [8] L. Li ad K. M. Smedley, A ew aalog cotroller for three-hase fourwire voltage geeratio iverter, IEEE Trasactios o Power Electroics, vol. 24, o. 7, , [9] Z. Zhag, O. C. Thomse ad M. A. E. Aderse, The circuit level decoulig modulatio strategy for three-level eutral-oit-clamed (TL-NPC) iverter, i Euroea Coferece o Power Electroics ad Alicatios, 2011, [10] X. Rua, B. Li, Q. Che, S.-C. Ta ad C. K. Tse, Fudametal cosideratios of three-level dc-dc coverters: toologies, aalysis, ad cotrol, IEEE Trasactios o Power Electroics, vol. 55, o. 11, ,