Analysis of Neutral Point Clamped Multilevel Inverter Using Space Vector Modulation Technique

Transcription

1 Iteratioal Joural of Egieerig ad Techical Research (IJETR) ISSN: , Volume-3, Issue-2, February 215 Aalysis of Neutral Poit Clamped Multilevel Iverter Usig Space Vector Modulatio Techique M.Aad, R.Sethilkumar. Abstract I the field of high power ad medium voltage applicatio, the multilevel iverter seem to be the most promisig alterative. Such iverters sytheses a desired output voltage from several levels of dc voltage as iputs. This paper aalyses the performaces of Neutral Poit Clamped Iverter (NPCI) usig space vector pulse width modulatio (SVPWM) techique. I SVPWM techique, the voltage referece provided usig revolvig referece vector. I this case magitude ad frequecy of the fudametal compoet i lie side is cotrolled by the magitude ad frequecy respectively of the referece voltage vector. Space vector modulatio techique utilizes the DC bus voltage more efficietly ad geerate less harmoic distortio whe compared to siusoidal PWM (SPWM) techique. The space vector pulse width modulatio cotrol techique has bee applied to five level iverter ad their performace has bee aalyzed by usig MATLAB /Simulik. The output shows better performace results. The variatio based i Total harmoics distortio are also aalyzed Idex Terms DC Bus Voltage Utilizatio, Neutral Poit Clamped Iverter (NPCI), Less Harmoic Distortio, Siusoidal Pulse Width Modulatio (SPWM), Space Vector Pulse Width Modulatio (SVPWM). Capacitors, batteries ad reewable eergy voltage sources ca be used as the multiple DC voltage source. Space vector modulatio (SVM) is a algorithm for the cotrol of pulse width modulatio (PWM).It is used for the creatio of alteratig curret (AC) waveform; most commoly to drive 3 phase AC powered motor at varyig speeds. I space vector pulse width modulatio (SVPWM) methods, the voltage referece is provided usig a revolvig referece vector. Space vector modulatio techique utilizes DC bus voltage more efficietly ad geerates less harmoic distortio whe compared with Siusoidal pulse width modulatio (SPWM) techique [3]. A. BLOCK DIAGRAM OF PROPOSED SYSTEM DC SOURCE NPC INVERTER SVPWM LOAD I. INTRODUCTI Numerous idustrial applicatios have begu to require high power apparatus i recet years. Some medium voltage drives ad utility applicatios require medium voltage ad megawatt power level.for a medium voltage grid, it is troublesome to coect oly oe power semicoductor switch directly. As a result, a multilevel power coverter structure has bee itroduced as a alterative i high power ad medium voltage situatios. A multilevel coverter ot oly achieves high power ratigs but also eables the use of reewable eergy sources.reewble eergy sources such as photovoltaic, wid ad fuel cell ca be easily iterfaced to a multilevel coverter system for a high power applicatio. The cocept of multilevel iverter has bee itroduced sice 1975.the term multilevel bega with five level coverter.subsequetly several multilevel coverter topologies has bee developed.however,the elemetary cocept of multilevel coverter to achieve higher power is to use a series of power semicoductor switches with several lower voltage dc source to perform power coversio by sythesizig a staircase voltage waveform. Mauscript received February 3, 215. M.Aad, Electrical ad Electroics Egieerig, Baari Amma Istitute of Techology, Sathyamagalam, Erode, Tamil Nadu, Idia, Mobile No: R. Sethil Kumar, Electrical ad Electroics Egieerig, Baari Amma Istitute of Techology, Sathyamagalam, Erode, Tamil Nadu, Idia, Ph. No: Fig 1 Block Diagram The DC source may be ay reewable DC source like solar photovoltaic or fuel cells. The iverter that cosidered here is Neutral Poit Clamped Iverter (NPCI) also kow as Diode Clamped Multilevel Iverter (DCMLI) for five level output voltage. The modulatio techique adopted is Space Vector Pulse Width Modulatio (SVPWM) A.Itroductio II. MULTILEVEL INVERTER Multilevel Iverter has bee attracted a large iterest i the power idustry i the recet years. Idustry has started to ivolve i higher power equipmet, which already reaches megawatt level. Covetioal power electroic coverters are oly able to switch each idividual iput or output lik betwee two possible voltage levels, especially those of the iteral DC voltage lik. The geeral structure of the multilevel coverter is to geerate a siusoidal voltage from several levels of voltages which are usually obtaied from capacitor voltage sources. B. Multi-Level Iverter Topologies Multilevel power coversio techology is a very rapidly growig area of power electroics with good potetial for 32

2 Aalysis of Neutral Poit Clamped Multilevel Iverter Usig Space Vector Modulatio Techique further developmet. The most attractive applicatios of this techology are i the medium- to high-voltage rage (2-13 kv), ad iclude motor drives, power distributio, power quality ad power coditioig applicatios. There are differet types of multi-level circuits ivolved. The first topology itroduced was the series H-bridge desig. This was followed by the diode clamped coverter, which utilized a bak of series capacitors. A later ivetio detailed the flyig capacitor desig i which the capacitors were floatig rather tha series-coected. Aother multilevel desig ivolves parallel coectio of iverter phases through iter-phase reactors. I this desig, the semicoductors block the etire dc voltage, but share the load curret. Several combiatioal desigs have also emerged some ivolvig cascadig the fudametal topologies. These desigs ca create higher power quality for a give umber of semicoductor devices. Battery or Rectifier Vd Cd Iverter AC Voltage (a) Sie-Triagle Compariso (b)switchig Pulses Fig 3.PWM Illustratio by the Sie-Triagle Compariso C. Classificatio of Multilevel Iverter Based O Source Fig 2. Schematic for iverter system The schematic of iverter system is as show i fig 2 i which the battery or rectifier provides the dc supply to the iverter. The iverter is used to cotrol the fudametal voltage magitude ad the frequecy of the ac output voltage. AC loads may require costat or adjustable voltage at their iput termials, whe such loads are fed by iverters, it is essetial that the output voltage of the iverters is so cotrolled as to fulfil the requiremet of the loads For example if the iverter supplies power to a magetic circuit, such as a iductio motor, the voltage to frequecy ratio at the iverter output termials must be kept costat. This avoids saturatio i the magetic circuit of the device fed by the iverter. I the sigle phase voltage source iverters PWM techique ca be used i three phase iverters, i which three sie waves phase shifted by 12 with the frequecy of the desired output voltage is compared with a very high frequecy carrier triagle, the two sigals are mixed i a comparator whose output is high whe the sie wave is greater tha the triagle ad the comparator output is low whe the sie wave or typically called the modulatio sigal is smaller tha the triagle. As the output voltage from the iverter is ot smooth but is a discrete waveform ad so it is more likely tha the output wave cosists of harmoics, which are ot usually desirable sice they deteriorate the performace of the load, to which these voltages are applied. Recet advaces i power electroics have made the multilevel cocept practical. I fact, the cocept is so advatageous that several major drives maufacturers have obtaied recet patets o multilevel power coverters ad associated switchig techiques. It is evidet that the multilevel cocept will be a promiet choice for power electroic systems i future years, especially for medium-voltage operatio. Separate DC Sourcce Cascade Iverter Multilevel Iverter Commo DC Source Diode Clamped Iverter Fig 3. Classificatio of MLI Flyig Capacitor Iverter Three differet topologies have bee projected for multilevel coverters 1. Diode clamped multilevel iverter (DCMLI) 2. Flyig capacitor multilevel iverter (FCMLI) 3. Cascaded multilevel iverter (CMLI) Several modulatio ad cotrol strategies have bee developed or beig used for multilevel coverters icludig the followig 1. Multilevel siusoidal pulse width modulatio (MSPWM), 2.Multilevel selective harmoic elimiatio (MSHE) 3. Space-vector modulatio (SVM). D. Diode Clamped Multilevel Iverter The diode-clamped iverter is show i Fig. 4. I this circuit, the dc-bus voltage is split ito three levels by two series-coected bulk capacitors C 1 ad C 2. The middle poit of the two capacitors ca be defied as the eutral poit. The 33

3 output voltage has V a three states: /2,,-/2. For voltage level /2, switches S1 ad S2 eed to be tured o for -/2, switches S1 ad S2 eed to be tured o; ad for the level, S2 ad S1 eed to be tured o. Iteratioal Joural of Egieerig ad Techical Research (IJETR) ISSN: , Volume-3, Issue-2, February 215 C1 a C2 Vc2 /2 S1 C1 C3 Vc3 D1 S2 a C4 D2 S1' C2 S2' Fig 6. Cascaded Multilevel Iverter -/2 III..NEUTRAL POINT CLAMPED INVERTER (NPCI) Fig 4. Diode Clamped Multilevel Iverter E. Capacitor Clamped Multilevel Iverter The fudametal buildig block of a phase-leg capacitor-clamped iverter. The circuit has bee called the flyig capacitor iverter with idepedet capacitors clampig the device voltage to oe capacitor voltage level. The iverter i Fig 5 provides a three-level output across a ad, i.e. Va = /2,, /2 /2 C1 C2 Cl S1 S2 S1' S2' a The eutral poit clamped iverter (NPCI) was first itroduced by A. Nabae, I. Takahashi ad H. Akagi i 198 ad published i With this circuit cofiguratio, the voltage stress o its power switchig devices is half that for the covetioal two-level iverter. Because of this ature, it was applied to medium ad high voltage drives. Early applicatios icluded the steel idustry ad railroad tractio areas i Europe ad Japa. I additio to the capability to hadle high voltage, the NPC iverter has favorable features like lower lie-to-lie ad commo-mode voltage steps, more frequet voltage steps i oe carrier cycle, ad lower ripple compoet i the output curret for the same carrier frequecy. These features lead to sigificat advatages for motor drives over the covetioal two level iverters i the form of lower stresses to the motor widigs ad bearigs, less ifluece of oise to the adjacet equipmet, etc. Combied with a sophisticated PWM strategy, it also makes it possible to improve the dyamic performace employig the dual observer method. I order to beefit from the above-metioed features, geeral-purpose pulse-width modulated (PWM) NPC iverters have bee developed for low voltage drive applicatios. I this product, a uique techology is used to achieve balacig of the dc bus capacitor voltages [1] -/2 A. Basic Circuit Cofiguratio ad Its Behavior Fig 5. Capacitor Clamped Multilevel Iverter E/2 Sa1 Sb1 Sc1 F. Cascaded Multilevel Iverter A differet coverter topology is itroduced here, which is based o the series coectio of sigle-phase iverters with separate dc sources. Fig 6. Shows the power circuit for oe phase leg of a ie-level iverter with four cells i each phase. The resultig phase voltage is sythesized by the additio of the voltages geerated by the differet cells. Each sigle-phase full-bridge iverter geerates three voltages at the output +,, -.This is made possible by coectig the capacitors sequetially to the ac side via the four power switches. The resultig output ac voltage swigs from - 4 to 4 with ie levels, ad the staircase waveform is early siusoidal eve without filterig. E/2 D1a D2a Sa2 Sa1' Sa2' D1b Sb2 Sc2 a b c Sb1' Sc1' D2b Sb2' D1c D2c Fig 7. Basic Circuit Cofiguratio The circuit diagram of the NPC five-level iverter is show i Fig 7. Each phase has four switchig devices (IGBTs) coected i series. Takig phase a as a example, the circuit behaves i the followig maer. Whe IGBTs Sa1 ad sa2 are tured o, output A is coected to the positive mil (P) of Sc2' 34

4 Aalysis of Neutral Poit Clamped Multilevel Iverter Usig Space Vector Modulatio Techique the dc bus. Whe Sa2 ad Sa1 are o, it is coected to the mid-poit () of the dc bus, ad whe Sa1 ad Sa2 are o, it is coected to the egative rail (N). Thus, the output ca take five voltage values compared to two values for the covetioal two-level topology. Relatio betwee the switchig states of GBTs ad the resultig output voltage with respect to the dc mid-poit is summarized below. DC bus capacitors eed to be coected i series to get the mid-poit that provide the zero voltage at the output. This is ot a drawback sice series coectio of the dc capacitors is a commo practice i geeral-purpose iverters rated at 4-48 V rage due to the uavailability of high voltage electrolytic capacitors. State/Switch Sa1 Sa2 Sa1' Sa2' Vio 1-1 Table 1: Three level iverter switchig states E/2 - E/2 The curret from the iverter bridge ito the capacitor mid-poit is the oly ew issue for this topology, ad maitaiig the voltage Balace betwee the capacitors is importat ad iflueces the cotrol strategy IV. SPACE VECTOR MODULATI A. Itroductio A differet approach to PWM is based o the space vector represetatio of the voltages i the d-q plae. This chapter deals with space vectors ad the method of usig space vector cocept for derivig switchig istats for pulse width modulated voltage source iverter is discussed here. [4] B. Space Vectors The techique of the space vector modulatio ivolves the cocept of space vector. I ay five phase machie, the stator coils are distributed i space i a symmetrical maer i.e. each coil is placed at 12 degree with respect to each other. I this method the five phase quatities ca be trasformed to their equivalet 2-phase quatity either i sychroously rotatig frame or statioary referece frame. [4] Vc Vb 12 Fig 8. Three Phase Quatities Trasformed ito Two Phase From this 2-phase compoet the referece vector magitude ca be foud ad used for modulatig the iverter output. Let the three phase siusoidal voltage compoet be, V a =V m si ωt Va Vq 9 Vd V b =V m si( ωt-12) V c =V m si (ωt-24) Equatig the three phase machie quatities, we get V a + V b + V c = (1) Vd=-3/2(Vb)+3/2(Vc)=3/2Vmcosωt (2) Vq=Va-Vb/2-Vc/2= 3/2Vmsiωt (3) Rotatig vector, Vref=Vd=Vq=3/2e^(jωt) (4) From equatio (4) it ca be see that space vector moves with costat agular velocity ad costat amplitude. I case of o-siusoidal quatities, the space vectors will ot ecessarily move with costat amplitude or costat agular velocity. The output of the iverters which are usually used i various applicatios are ot perfectly siusoidal. It cotais appreciable amout of harmoics. So, the space vector of the stator voltages i these cases if of amplitude movig i steps ad ot with a costat agular velocity. I space vector modulatio, a referece vector of the stator voltages is geerated, which is made to move i the d-q plae i small steps so that it appears to move smoothly, as i the case with siusoidal supply. The space vector modulatio is based o the space vector represetatio of the voltages i d-q plae. After the trasformatio to the two phase quatities, the power as well as the impedace remai uchaged. I space vector modulatio we try to geerate a voltage referece vector at a poit of time ad the voltage referece vector Vref is sampled which approximately by a time sequece of five well defied switchig state vector earest to the referece vector. This is doe by samplig the switchig state vectors i such a way that the total volt secods geerated by these vectors over a iterval Ts equals the volt secods geerated by the referece vector Ts. C. Space Vector Represetatio of Five Level Iverter The switchig state vectors i this figure are ormalized with respect to. The three symbol represet the coditios of each phase voltages +/2,, -/2 ad zero meas zero voltage. The modulatio idex is the magitude of the referece vector V ref ormalized with respect to. It ca be see that the 12 vectors fallig o the outer hexago ca be realized by oly oe switchig state each whereas the 6 vectors fallig o the ier hexago ca be realized with two switchig states each ad zero voltage with five switchig states. V11 V17 V18 V1 V16 2 V3,V23 V2,V22 V9 V15 3 V7 V14 V4,V24 1 V1,V21 V8 V 6 4 V5,V25 V6,V26 V2 5 V12 V19 V13 Fig 1. Space vector represetatio of five level iverter Like two level iverter, i five level iverter each space vector is realized by usig five idices of the triagle i which the tip of the vector lies. 35

5 V9 Iteratioal Joural of Egieerig ad Techical Research (IJETR) ISSN: , Volume-3, Issue-2, February 215 B. Output Curret of five Level Iverter V2,V22 4 V ref V15 Lie Curret The output lie curret for five level iverter usig SVPWM is show i fig five phase curret is obtaied ad each is havig a phase delay of 12 V 1 3 V1,V21 2 V8 Fig 11. Four regio sector The above figure shows a 6 degree iterval which cosists of four triagles ad it has six vectors V to V5. If the referece vector is i triagle 1, V, V1, V2, V3 states have to be switched. If the referece vector is i triagle 2; V1, V2 ad V3 have to be switched. If it is i triagle 3; V1, V2 ad V4 are switched ad fir triagle 4, V2, V3 ad V5 are switched. The samplig itervals for each coditio foud usig same averagig priciple used i two level iverter. This techique i effect averages the five switchig state vectors over a sub cycle iterval/samplig iterval. The samplig itervals T1, T2 ad T are evaluated. For triagle 1, the switchig states are V, V1, ad V2. Similarly for triagle 2, the switchig states are V1,V2,V3 for Ta, Tb ad Tc duratio ad the samplig subitervals are derived as give i the table where m= Vref/(), Ts is the samplig time. Fig 13. Lie Curret geerated by SVPWM techique for five level iverter RL load Phase Curret The output Phase curret for five level iverter usig SVPWM is show i fig five phase curret is obtaied ad each is havig a phase delay of 12 V. SIMULATI AND RESULTS The simulatio ivolved i the Space vector pulse width modulatio of five level eutral poit clamped iverter are summarized below Simulatio Steps 1. Iitialize the system parameters usig Matlab 2. Build simulik model 3. Plot simulatio usig Matlab A.Simulik Model Of Five Level Neutral Poit Clamped Iverter The simulik model of five level NPC iverter is show i fig 12.the five level NPC iverter cosists of two DC source ad four switches per phase.the firig pulse are obtaied from space vector pulse width modulatio Fig 14. Phase Curret geerated by SVPWM techique for five level iverter RL load B.Output Voltage for Five Level Iverter Lie Voltage The output lie voltage for five level NPC iverter usig SVPWM is show i fig.five phase voltage is obtaied ad each is havig phase delay of 12.the stepped waveform gives lower distortio whe compared to lower levels of iverter Fig 12. Simulik Model of Five Level Neutral Poit Clamped Iverter Fig 15. Lie Voltage geerated by SVPWM techique for five level iverter usig RL load 36

6 Mag (% of Fudametal) Aalysis of Neutral Poit Clamped Multilevel Iverter Usig Space Vector Modulatio Techique Phase Voltage The output phase voltage for five level NPC iverter usig SVPWM is show i fig.five phase voltage is obtaied ad each is havig phase delay of 12.the stepped waveform gives lower distortio whe compared to lower levels of iverter discussed i terms of iverter output voltage,curret waveforms,total harmoic distortio.the applicatio of space vector pulse width modulatio cotrol startegy o five level eutral poit clamped iverter are aalysed.the mai aim of this method is to prove the effictiveess of SVPWM i the cotributio of reduced harmoic ijectio tha the covetioal pulse width modulatio techiques REFERNCES Fig 16. Phase voltage geerated by SVPWM techique for five level iverter RL load D.THD Aalysis Of five Level Iverter Selected sigal: 15 cycles. FFT widow (i red): 1 cycles Output voltage THD 1 Figure shows the FFT plot for output voltage of five level 5 NPC iverter for the modulatio idex values.from the figure it is clear -5 that output THD obtaied from the SVPWM -1 techique result i less distortio Time (s) Fudametal (5Hz) = 72.86, THD= 1.16% [1] Akira Nabae ad et al A New Neutral-Poit-Clamped PWM Iverter IEEE Trasactios o Idustry Applicatios, Vol. Ia-17, No. 5. September/October 1981 [2] Bi Wu, High-Power Coverters ad AC Drives, IEEE Press ad Wiley Itersciece, 26. [3] Chuduri Sreeharsha ad et al Study of siusoidal ad space vector pulse width modulatio techiques for a cascaded three level iverter, IJRET Volume: 2 Issue: 9 Sep 213 [4] Dori O. Neacsu, Space Vector Modulatio A Itroductio, IEEE Coferece o Idustrial Electroics Society, 21 [5] Hez willi Va Broeck ad Georg Viktor Stake, Aalysis ad Realizatio of a Pulsewidth Modulator Based o Voltage Space Vectors, IEEE Tras. Id. Appl., vol. 24, o , pp , [6] Leo M. Tolbert ad Thomas G. Habetler, Novel Multilevel Iverter Carrier-Based PWM Methods, IEEE IAS, October 1-15, 21, pp [7] McGrath P.B., D. G. Holmes, ad T. Lipo, Optimized space-vector switchig sequeces for multilevel iverters, IEEE Tras. Power Electro., vol. 18, o. 6,pp , Nov. 27. [8] Muhammad H. Rashid, Power Electroics, 2d Editio, Pretice Hall,1993 [9] Qi Lei ad Fag Zheg Peg, Space Vector Pulse width Amplitude Modulatio for a Buck Boost Voltage/Curret Source Iverter, IEEE Trasactios o Power Electroics, Vol. 29, No. 1, Jauary Frequecy (Hz) Fig 17. FFT Plot for output voltage of five level iverter usig SVPWM techique VI. CCLUSI I multilevel iverter,as the switchig ivolves several small voltages the rapid chage i voltage is smaller.but harmoic elimiatio is the major issue for multilevel iverters.space vector pulse width modulaio is cosidered a better techique of PWM implemetatio owig to its associated advatages like better fudametal output voltage,better harmoic performaces,efficiet DC voltage utilizatio ad easier to implemet i digital sigal process ad micro cotrollers The sector idetificatio space vector pulse width modulatio techiqueis used to aalyze the performace of multilevel iverter.the results has bee preseted ad aalyzed.the effectivess of these algorithm have bee BIOGRAPHY M.Aad I completed my Bachelour Degree i the year 213 ad completed research i wireless moitorig system for trasformer with the help of zigee module.at Preset I pursuig my Master degree i Power Electroics ad drives ad trarted my research i Neutral Poit clamped Iverter based o Space vector modulatio techique for PV Applicatio.I Published a paper i Iteratioal atioal Joural recetely DR.R.Sethil Kumar I completed my Ph.D by the year 213.I have a Teachig Experiece of 22 years from 1991 to till date.i orgaized two Natioal Cofereces,published Seve papers i Iteratioal Joural,Published Eight papers i Iteratioal Cofereces,Published eight paper i Natioal Cofereces.Life log member i Idia Society of Techiical Educatio (ISTE) ad i Istitutio of Egieers MIE,Member i Board of Studies i Baari Amma Istitute of Techology ad Nadha College of Egieerig 37