6.004 Computation Structures Spring 2009

Transcription

1 MIT OeourseWare htt://ocw.mit.edu 6.4 omutatio tructures rig 29 For iformatio about citig these materials or our Terms of Use, visit: htt://ocw.mit.edu/terms.

2 MO Techology ombiatioal evice Wish List NEXT WEEK: TUE: o lecture THU: Lab due! FRI: QUI!!! oly. Qualitative MOFET model 2. MO logic gates 3. MO desig issues diff metal diff V i V IH V i esig our system to tolerate some amout of error dd ositive oise margis VT: gai> & oliearity Lots of gai big oise margi hea, small hagig voltages will require us to dissiate ower, but if o voltages are chagig, we d like zero ower dissiatio Wat to build devices with useful fuctioality (what sort of oeratios do we wat to erform?) modified 2/9/9 5:7 L3 - MO Techology L3 - MO Techology 2 MOFET: ai & o-liearity Heavily doed (-tye or -tye) diffusios Very thi (<2Å) high-quality io 2 isulatig layer isolates gate from chael regio. source hael regio: electric field from charges o gate locally iverts tye of substrate to create a coductig chael betwee source ad drai. L bulk W gate Polysilico wire drai Iter-layer io 2 isulatio I W/L oed (-tye or -tye) silico substrate MOFETs (metal-oxide-semicoductor field-effect trasistors) are fourtermial voltage-cotrolled switches. urret flows betwee the diffusio termials if the voltage o the gate termial is large eough to create a coductig chael, otherwise the mosfet is off ad the diffusio termials are ot coected. L3 - MO Techology 3 FETs as switches The four termials of a Field Effect Trasistor (gate, source, drai ad bulk) coect to coductors that geerate a comlicated set of electric fields i the chael regio which deed o the relative voltages of each termial. gate source drai eletio regio (o carriers) forms at PN juctio. elf isulatig! INVERION: bulk sufficietly strog vertical field will attract eough electros to the surface to create a coductig - tye chael betwee the source ad drai. The gate voltage whe the chael first forms is called the threshold voltage -- the mosfet switch goes from off to o. E h E v iversio haes here ONUTION: If a chael exists, a horizotal field will cause a drift curret from the drai to the source. L3 - MO Techology 4

3 NFET: -tye source/drai diffusios i a -tye substrate. Positive threshold voltage; iversio forms -tye chael FETs come i two flavors The use of both NFETs ad PFETs comlimetary trasistor tyes is a key to MO (comlemetary MO) logic families. oect to N to kee PN reverse-biased (V < V); kees ad isulated from PFET: -tye source/drai diffusios i a -tye substrate. Negative threshold voltage; iversio forms -tye chael. oect to V to kee PN reversebiased L3 - MO Techology 5 MO Recie If we follow two rules whe costructig MO circuits the we ca model the behavior of the mosfets as simle switches: Rule #: oly use NFETs i ulldow circuits (aths from outut ode to N) Rule #2: oly use PFETs i ullu circuits (aths from outut ode to V ) NFET Oeratig regios: off : V < V TH,NFET o : V > V TH,NFET PFET Oeratig regios: off : V > V + V TH,PFET o : V < V + V TH,PFET ~V /5 ~ -V TH,NFET L3 - MO Techology 6 Whe is low, the fet is off ad the fet is o, so curret flows ito the outut ode ad V OUT evetually reaches V (= ) at which oit o more curret will flow. fet o fet off MO Iverter VT V IH I u I d teady state reached whe reaches value where I u = I d. V i Whe is high, the fet is off ad the fet is o, so curret flows out of the outut ode ad V OUT evetually reaches N (= ) at which oit o more curret will flow. fet off fet o Whe VIN is i the middle, both the fet ad fet are o ad the shae of the VT deeds o the details of the devices characteristics. MO gates have very high gai i this regio (small chages i roduce large chages i V OUT ) ad the VT is almost a ste fuctio. L3 - MO Techology 7 eyod Iverters: omlemetary ullus ad ulldows Now you kow what the i MO stads for! We wat comlemetary ullu ad ulldow logic, i.e., the ulldow should be o whe the ullu is off ad vice versa. ullu ulldow F(,,) o off drive off o drive o o drive X off off o coectio ice there s lety of caacitace o the outut ode, whe the outut becomes discoected it remembers its revious voltage -- at least for a while. The memory is the load caacitor s charge. Leakage currets will cause evetual decay of the charge (that s why RMs eed to be refreshed!). L3 - MO Techology 8

4 What a ice you have... MO comlemets o quiz! Thaks. It rus i the family... coducts whe V is high coducts whe is high ad is high:. coducts whe V is low coducts whe is low or is low: + =. 82 What fuctio does this gate comute? NN coducts whe is high or is high: + coducts whe is low ad is low:. = + 6 urret techology: = 45m OT: $35 er 3mm wafer 3mm roud wafer = (5e -3 ) 2 =.7m 2 NN gate = (82)(6)(45e -9 ) 2 =2.66e -2 m 2 2.6e NN gates/wafer (= billio FET!) margial cost of NN gate: 32$ L3 - MO Techology 9 L3 - MO Techology Here s aother eeral MO gate recie What fuctio does this gate comute? NOR te. Figure out ulldow etwork that does what you wat, e.g., F = ( + ) (What combiatio of iuts geerates a low outut) te 2. Walk the hierarchy relacig fets with fets, series subets with arallel subets, ad arallel subets with series subets te 3. ombie fet ullu etwork from te 2 with fet ulldow etwork from te to form fullycomlemetary MO gate. o, whats the big deal? L3 - MO Techology L3 - MO Techology 2

5 Quick Review ig Issue : Wires tatic discilie combiatioal device is a circuit elemet that has oe or more digital iuts oe or more digital oututs a fuctioal secificatio that details the value of each outut for every ossible combiatio of valid iut values a timig secificatio cosistig (at miimum) of a uer boud t P o the required time for the device to comute the secified outut values from a arbitrary set of stable, valid iut values R iut iut iut If is the coy to Y, otherwise coy to Y I will geerate a valid outut i o more tha 2 weeks after seeig valid iuts outut Y Today (i.e., m): R 5s/mm Imlies > s to traverse a 2mm x 2mm chi This is a log time i a 2Hz rocessor L3 - MO Techology 3 L3 - MO Techology 4 ue to uavoidable delays Proagatio delay (t P ): UPPER OUN o the delay from valid iuts to valid oututs. V IH V OUT < t P time costat = R P L < tp OL: miimize roagatio delay! IUE: kee aacitaces low ad trasistors fast time costat otamiatio elay a otioal, additioal timig sec INVLI iuts take time to roagate, too... V IH o we really eed t? V OUT > t ONTMINTION ELY, t LOWER OUN o the delay from ay ivalid iut to a ivalid outut = R PU L L3 - MO Techology 5 L3 - MO Techology 6 > t Usually ot it ll be imortat whe we desig circuits with registers (comig soo!) If t is ot secified, safe to assume it s.

6 The ombiatioal otract cyclic ombiatioal ircuits t P roagatio delay t cotamiatio delay If NN gates have a t P = 4 ad t = t is the miimum cumulative cotamiatio delay over all aths from iuts to oututs t P = 2 t = 2 Must be > t Y Note:. No Promises durig 2. efault (coservative) sec: t = Must be < t P t P is the maximum cumulative roagatio delay over all aths from iuts to oututs L3 - MO Techology 7 L3 - MO Techology 8 Oh yeah oe last issue What haes i this case? NOR: t P t MO NOR: t P t Iut aloe is sufficiet to determie the outut Recall the rules for combiatioal devices: Outut guarateed to be valid whe all iuts have bee valid for at least t P, ad, oututs may become ivalid o earlier tha t after a iut chages! May gate imlemetatios--e.g., MO adhere to eve tighter restrictios. L3 - MO Techology 9 LENIENT ombiatioal evice: Outut guarateed to be valid whe ay combiatio of iuts sufficiet to determie outut value has bee valid for at least t P. Tolerates trasitios -- ad ivalid levels -- o irrelevat iuts! NOR: Leiet NOR: X X L3 - MO Techology 2

7 moves from L to H to L ig Issue 2: Power V Eergy dissiated = V 2 er cycle Power cosumed = f V 2 er chi where f = frequecy of charge/discharge = umber of gates /chi V OUT V OUT moves from H to L to H discharges ad the recharges Ufortuately Moder chis (Ultraarc III, Power4, Itaium 2) dissiate from 8W to 5W with a Vdd.2V (Power suly curret is ms) oolig challege is like makig the filamet of a W icadescet lam cool to the touch! Worse yet Little room left to reduce Vdd ad f cotiue to grow Hey: could we omehow recycle the charge? L3 - MO Techology 2 L3 - MO Techology 22 MUT comutatio cosume eergy? (a tiy digressio ) How eergy-efficiet ca we make a gate? It seems that switchig the iut to a NN gate will always dissiate some eergy Ladauer s Pricile (96): discardig iformatio is what costs eergy! eett (973): Use reversible logic gates, ot NN, ad there s o lower boud to eergy use! htt:// htt:// P Q FEYNMN TE: 2 bits 2 bits (iformatio Preservig!) NN TE: 2 bits bit (iformatio Loss!) The fudametal hysical limits of comutatio, eett & Ladauer, cietific merica. Vol. 253, July 985 eett, Fredki, Feyma, others: omuter systems costructed from iforeservig elemets. Theory: NO lower boud o eergy use! Practice: Research frotier (qubits, etc.) ummary MO Oly use NFETs i ulldows, PFETs i ullus mosfets behave as voltage-cotrolled switches eries/arallel Pullu ad ulldow switch circuits are comlemetary MO gates are aturally ivertig (risig iut trasitio ca oly cause fallig outut trasitio, ad vice versa). Perfect VT (high gai, = V, = N) meas large oise margis ad o static ower dissiatio. Timig secs t P : uer boud o time from valid iuts to valid oututs t : lower boud o time from ivalid iuts to ivalid oututs If ot secified, assume t = Leiet gates: outut uaffected by some iut trasitios Next time: logic simlificatio, other caoical forms L3 - MO Techology 23 L3 - MO Techology 24