Overview of the Power Minimization Techniques Employed in the IBM PowerPC 4xx Embedded Controllers Anthony Correale, Jr.

Transcription

1 Overview of the Power Miimizatio Techiques Emloyed i the IBM PowerPC 4xx Embedded Cotrollers Athoy Correale, Jr. Itroductio The eed for ower efficiet embedded cotrollers became obvious whe the exlosio i ortable commuicatios ad cosumer segmets bega. While the IBM PowerPC TM 4xx 1 embedded cotroller family addresses a wide variety of market segmets, its low ower cosumtio makes it articularly attractive for the cosumer electroics ad ortable commuicatios market segmets. While low ower cosumtio is most ofte thought of as beig imortat to exted battery life, there are other advatages of usig a ower-efficiet embedded cotroller: The comoet ca oerate i a much harsher thermal eviromet because its low ower results i a broader oeratig ambiet. The eed for thermal ehacemets such as heat siks ad forced air coolig is elimiated, thereby resultig i lower comoet ad system costs. I alicatios where comoet lacemet is critical due to thermal costraits, usig the PowerPC 403GA gives the system desiger additioal flexibility. I alicatios where thermal limitatios are ot of cocer, the low ower dissiatio of the PowerPC 403GA affords ehaced reliability. Additioally, a ower-efficiet embedded cotroller macro allows for a more robust 'Core-lus' strategy ad imlemetatio. This aer discusses the may ower coscious aroaches used i the imlemetatio of the PowerPC 403GA. The PowerPC 403GA TM is the first member of the IBM 4xx embedded cotroller family. It is a 32-bit RISC embedded cotroller which cotais a 2K-Byte Istructio Cache ad a 1K-Byte Data Cache both of which are 2-way set associative. The chi also icororates a two-level iterrut cotroller, a 4 chael DMA cotroller, a serial ort uit, a Bus Iterface Uit ad a JTAG ort which is also used for real-time debug. Curretly, alicatios for the 403GA iclude office automatio (eg., riters, coiers, fax machies), cosumer electroics (eg., video games, set-to boxes, ad PDAs), telecommuicatios, ad etworkig. Table 1 highlights the characteristics of the silico rocess emloyed ad the hysical attributes of the PowerPC 403GA Effective ower maagemet begis with the realizatio that caacitace ad ode switchig must be miimized. Equatio 1 shows that AC ower dissiatio is iflueced by three elemets: ower suly voltage, caacitace, ad switchig frequecy. 1. Power = (0.5*C l *V 2 dd *f) + (I sc + I leakage )*V dd PowerPC Itegrated Solutios IBM Microelectroics, RTP, NC Oce the ower suly voltage has bee set, the remaiig terms that ifluece ower dissiatio are the caacitace, C l, ad the switchig frequecy, f. The other terms i total ower equatio are the short circuit ower, I sc *V dd, exeded whe both -chael ad -chael devices are o cocurretly durig a switchig evet, ad leakage ower, I leakage *V dd. Short circuit ower ca be miimized by maagig trasitio rates, ad leakage ower is dictated by the techology emloyed (rovided that circuit desig is doe roerly). Parameter Techology Chi Size Value IBM TM CMOS5L 2 0.5um, N-Well CMOS, 3 Levels of metal 6.05 X 6.05 mm Trasistors Aroximately 600,000 Arrays Periheral Uits Power Suly Power Performace Package I/O 1-Kbyte, 2-way set associative Data Cache 2-Kbyte, 2-way set associative Istructio- Cache 32 X 32 5-ort Geeral Purose Register File Iterrut Cotroller 4 chael DMA Cotroller Serial Port Bus Iterface Uit JTAG Port 3.3 volt omial 200 mw 3.3v, 10F load 660 mw 85C, 3.3v, 50F load 30 mw Wait State 54.5K 25 MHz 72K 33 MHz 160 i QPFP 127 sigal, CMOS/TTL levels, 5V comliat Table 1. Process ad chi hysical attributes Caacitace miimizatio ca be accomlished by miimizig the wirig distace betwee the drivig ad receivig circuit(s), usig a routig medium with the least caacitace er uit legth, selectig the roer drivig ad receivig circuit drive stregth (ower/ erformace code) ad elimiatig eedless stray arasitics. With IBM's advaced 0.5 micro CMOS5L techology, metal layer caacitace associated with the area comoet of the metal lie has bee miimized through the use of thick oxides ad iter-layer laarizatio. Lateral (lie- to-lie) caacitace becomes the

2 domiat term i the wirig caacitace equatio. Therefore, while the area comoet is miimized, the imortace of the lateral caacitace term icreases as wirig itches decrease. Hece, wirig caacitace while reduced, still lays a sigificat role i the overall et caacitace. For ets which have short routig distaces, the domiat caacitace is associated with the gate oxide, the diffusio juctio of the drivig circuit ad the arasitic field olysilico. For a give frequecy of oeratio, miimizatio of ay of the above will result i lower ower dissiatio. Power maagemet techiques emloyed o the PowerPC 403GA embedded cotroller iclude: 1. A rich ower/erformace circuit library 2. Post rocessig algorithms for miimizatio of udesirable arasitics due to lace ad route 3. Comiled 1xN Macros 4. Local clock slittig & geeratio 5. Dyamic o-chi clock activatio 6. Oerad trasitio isolatio 7. Gated ad clocked receivers ad commo I/O 8. Extesive use of NFET trasfer gates Circuit Library To miimize caacitace, a very robust circuit library was created that emulated a had-crafted custom realizatio, but afforded the use of automated lace ad route. To this ed, a broad sectrum of ower/erformace otimized circuits was realized. The graularity betwee the ower/erformace codes for each library elemet was defied to rovide offerigs i the caacitive loadig rages most frequetly used. Based o our desig exeriece from develoig other IBM embedded cotrollers, it was exected that the average caacitive loadig er et would eed to be aroximately 0.2F to achieve the desired ower/erformace for this embedded cotroller. Although there would exist ets which had sigificatly higher caacitace, those ets are tyically limited to a relatively arrow class of circuits ad logical fuctio. With this i mid, circuit drive stregths i icremets of 25fF were realized. The lowest ower circuit, A-ower, has a drive stregth of 25fF, whereas the highest ower code suorts 2500fF. Table 2 defies the corresodece betwee the ower/erformace code ad allowed maximum outut caacitace. As see by the table, the highest cocetratio of drive stregths is i the rage of 25fF to 250fF. Here, the caacitace graularity is 25fF. Drive stregths i the rage from 250fF to 500fF have a graularity of 50fF; the rage from 500fF to 1F have a graularity of 100fF; ad fially, the rage from 1F to 2.5F have a graularity of 500fF. Power/ Perf Code Maximum Ca.(fF) Power/ Perf Code A 25 P 600 B 50 Q 700 C 75 R 800 D 100 S 900 E 125 T 1000 F 150 U 1500 G 175 V 2000 H 200 W 2500 I 225 X J 250 Y K 300 Z L 350 M 400 N 450 O 500 Maximum Ca.(fF) Table 2. Assigmet of Power/Performace Codes to Maximum Ca To kee the umber of elemets i the circuit library maageable, ot all circuit elemets were created with all ower codes. Rather, the ower codes for each elemet were created as a fuctio of the circuit comlexity. The broadest offerig of ower/erformace codes were associated with the simlest fuctio circuit elemets (iverters ad buffers), ad the fewest ower/erformace codes were associated with the most comlex fuctios (RAMs, GPR, Multilier). Figure 1 illustrates the associatio of ower/erformace breadth to fuctio comlexity. I a tyical microrocessor desig, sigle level logic rimitives are used most frequetly. Therefore, we created the broadest sectrum of ower/erformace circuits for sigle level logic rimitives. Fuctio Comlexity MSI fuctios Latches, Clock Ge, MPX, Decode Parity Ge / Chk XOR, XNOR Two level logic rimitives Sigle level logic rimitives Figure 1. Fuctio Comlexity versus Power/Performace Breadth Power / erformace breadth

3 The ext most frequetly used fuctios are two level logic realizatios, ad the rage of their ower/erformace circuits offered is smaller tha the sigle level logic rimitives. Sythesis ca create these fuctios by usig comoets from the sigle level logic rimitives, but ot with the same overall area, wirig efficiecy ad ower/erformace. Therefore, this class of circuits was desiged, albeit with fewer ower/erformace otios tha the sigle level logic class. The most comlex fuctios are used with less frequecy ad as such, required fewer ower/erformace otios. Hece, as fuctio comlexity icreases, the ower/erformace breadth decreases. The library of circuits was comrised of the followig fuctios; NOR 1-4 OR 1-4 NAND 2-4 AND 2-4 AOI!(ab+c, ab+cd, ab+cd+e, ab+cd+ef, ab+cd+ef+g, ab+cd+ef+gh) AO (ab+c, ab+cd, ab+cd+e, ab+cd+ef, ab+cd+ef+g, ab+cd+ef+gh) XOR 2 XNOR 2 4-bit Full Adder Selectors (1-2, 1-3, 1-4, 1-5, 1-6, 1-8) Decoders (1-2, 2-4) Polarity Hold L1/L2 LSSD latches Clock Slitters Off Chi Driver / Off Chi Receiver The umber of iuts for the rimitive logic fuctios, such as NOR, NAND, AND ad OR was limited to four. Both ivertig ad o-ivertig fuctios were created to take advatage of the ower/erformace ad area of the library elemet. The circuits do ot suort both olarities cocurretly. All the circuits were desiged to satisfy a 1s outut trasitio time, as measured from the 10 to 90% oits, at rated maximum caacitace whe the alied iut trasitio rate was betwee 0.1s ad 1s. The fast trasitio time requiremets were imosed to miimize the ower associated with the time that both the ullu ad ull-dow devices were active. This trasitio time is also cosistet with the 0.5 micro techology beig emloyed. The higher comlexity radom logic circuits were sythesized. This elimiated the guesswork of how best to realize the higher iut cout circuits for otimal ower, erformace ad area. The umber of ower/erformace codes reseted a logistics roblem for the sythesis egie ad, as such, a three-hase sythesis aroach was emloyed. The first stage reseted the sythesis egie with a subset of the library wherei the ower/ erformace icremets were relatively large, with a maximum of 5 otios for each fuctio. The secod stage used a ost-sythesis otimizatio wherei the etire library was rereseted. After lace ad route, a additioal i-lace otimizatio was emloyed, wherei circuits were relaced with differet drive stregths to better match the eeded miimal ower/erformace requiremets. Sice the library was very graular i ower/erformace, accurate redictio of caacitace loadig was imerative. The chi was imlemeted usig hierarchical logic, sythesis, ad lace ad route artitios. To accout for the differet tye of domais ad requiremets, each artitio could use a differet wire load model for sythesis. A domai wherei the orgaizatio was comosed of rimarily radom logic could be treated differetly tha a data flow stack. Post route wire caacitace was fed back to the sythesis egie for i-lace otimizatio. The circuits were hysically desiged so that may ower codes of a give fuctio would occuy the same hysical sace with oly wirig i target differeces. The sythesis egie was iformed of eligible relacemets for the i-lace otimizatio. If caacitace violatios remaied after these otimizatios, the egieerig evaluatios were made as to how to roceed. O occasio, maual maiulatio of the layout was eeded to effect the desired results. I additio to the sythesis egie s limited ability to choose from the broad sectrum of ower/erformace circuits available i the library, the iability to directly secify the ower cosumtio of the circuit ad request a ower miimizatio sythesis left much to be desired. This was esecially frustratig because the tyical metrics used i the miimizatio rocess are erformace ad area. Sice may like fuctio circuits of differig ower/erformace codes occuied the same area, the tool would choose the higher ower circuit. To this ed, we heuristically adjusted the area metric to steer the tool to a more reasoable choice. This is a area where much imrovemet is eeded for ower otimized sythesis. Comiled Etities All circuits were desiged with the same hysical form factor (itch). This allowed combiatorial logic to be laced ad routed with more comlex fuctios. Registers were comiled from the base latches ad clock slitters. The comiled register allowed variatios i bit width, olarity ad ower code o a er-bit basis, ad variatios i clock gatig ad sca directio ad defiitio. Similarly, selectors were comiled from the base select circuits ad decoders. Power code defiitio was secifiable o a er-bit basis. The ower code of the decoder, like the clock slitter, was a fuctio of the bit width. Defaults could be overridde by the desiger to effect imroved erformace, but there were miimum defaults that could ot be overridde. Five ower/erformace codes were used for the clock slitters ad four for the decoders. Great care had to be exercised i the develomet of the clock slitters to esure that uder the broad rage of register bit widths, clock overla was miimized without sacrificig erformace. The comiled etities were istatiated i the schematic with a "do't touch" roerty, thereby disallowig the sythesis egie from modifyig them. To this ed, all comiled etities were iitially realized as havig miimum ower code comoets uless the desiger required otherwise. The sythesis egie was deceived to thik that the comiled etities had the highest ower code to miimize the additio of uecessary re-owerig buffers by the sythesis egie. After sythesis ad lace ad route, the actual ower codes were revealed, ad timig aalysis determied which bits of the comiled etities required chage. The register ad selector bits were the chaged to the aroriate ower code. Sice the register ad selector bits were all iterchageable from a ower viewoit, wirig modificatios were't ecessary. This ractice esured that the miimum ower code o a er-bit basis was emloyed. The registers also ermitted olarity chages without area icreases, but did result i wirig erturbatio. This was esecially helful whe the sythesis egie eeded higher drive stregth tha the highest ower code register bit could suort. I this case, high ower buffers which were added to the register outut would be relaced by the same ower iverters, ad the hase of the latch could be chaged. While this did require some routig modificatios, it saved ower ad ehaced erformace. Area could be saved if the regio were comressed ad rerouted. Parasitic Caacitace Miimizatio IBM s CMOS5L techology requires that each device gate be coected to a diffusio at comletio of M1 rocessig to avoid

4 otetial threshold voltage shifts ad reduced hot-electro reliability due to subsequet rocess stes. This "floatig gate" requiremet ca be most easily satisfied by emloyig a floatig gate cotact structure o all gate iuts. While this aroach has the beefit of esurig all gates are rotected without elaborate checkig algorithms, it is the least ower efficiet aroach. For examle, each floatig gate cotact structure has a 2fF caacitace, ad while this may seem isigificat it reresets 40% of the overall iut caacitace of the A-ower code iverter. Furthermore, i the desig of a low ower library, eve the field olysilico coectios eed to be miimized. Protectig each gate requires ositioig the floatig gate cotact i a give wirig chael ad coectig the field oly to it. Sice may of the devices are extremely small (less tha 3um), there would be cosiderable field oly betwee the gate ad the outermost wirig track i the cell. We chose to imlemet a algorithmic aroach to fid all floatig gates ad correct them automatically. The aroach was aroximately 99% effective. I less tha 1% of the cases, maual itervetio was required. Sice the registers ad selectors were comiled, all ecessary itra-macro coectios requirig floatig-gate rotectio were itegrated i the base cells durig desig. I additio, the extesive use of NFET trasfer gates for the selector ad latch iuts heled miimize the umber of floatig gate cotacts. Trasfer gates were used for the obvious reasos of ower, erformace ad area. 3 The floatig gate rotectio beefit, while secodary, was quite welcome. I this regard the use of algorithmic alicatio of floatig gates ot oly miimizes the caacitace of the floatig gate cotact structure, but it also reduces the field olysilico itercoect. Field olysilico coects were also miimized by algorithmically creatig the eeded olysilico stras betwee the wirig target locatio ad the actual gate. I may libraries, the olysilico exteds from each gate ito the wirig tracks to rovide amle wirig targets. This adds field olysilico ad hece, iut caacitace to all circuits emloyig it. Pseudo-olysilico aths or flight lies were icororated ito each circuit from the wirig field i to the resective gate. This allowed for cotour routig to avoid blockages ad miimize area. The aroriate flight lie was the algorithmically coverted to field olysilico based o global wirig target ersoalizatio. This aroach saved at least 50% of all field olysilico. Figure 2 illustrates this cocet. A similar aroach was emloyed o diffusios associated with trasfer gate source iuts ad outut circuit source ad drais. Local Clock Slittig ad Geeratio Figure 3 shows that the o-chi clock distributio etwork took the form of a itchfork with the source beig located at the hadle. No o-chi receiver or redrive buffer was emloyed other tha the distributed local clock slitters located alog the ties of the itchfork. While this results i icreased module i caacitace (22F) the ower saved i receivig ad reowerig the clock tree is estimated at 10mW. The ties were all routed i M3 to miimize caacitace. To hadle the curret desity requiremets, the widths of the lies were icreased but the sacig to adjacet lies was also icreased to reduce coulig ad erimeter caacitace Local Chi ad Figure 3: Clock Distributio Network Dyamic O-chi Clock Activatio Clock Slitter / re-drive Buffers.... Dyamic o-chi clock activatio was used extesively to miimize ower. Each comiled register had a itegrated clock overhead cell which served as a 2-hase clock slitter, re-drive buffer ad ower maagemet cotrol. The ower maagemet was i the form of a air of cotrol sigals which, whe deactivated, disabled the clock slitters ad the redrive buffers from switchig. This scheme allowed ideedet cotrol of the C1 (L1 latch) ad the C2 (L2 latch) clocks. This ideedet cotrol allowed the desiger the ultimate flexibility i maagig ower ad erformace. For cases where erformace was of critical imortace, the C1 clock gate would be eabled. This was ecessary oly for critical half-cycle aths. Very rarely would the C2 clock gate be byassed. This clock gatig scheme was emloyed throughout the chi desig. The gatig of clocks ot oly affords ower reductio i the clock slitter, but also i the latches themselves. This is evidet i the case of L2 latches which are disabled for a give cycle ad the cotet of the L1 latch is a "do't care". Loadig the L1 latch o this cycle ot oly causes eedless ower dissiatio i the clock slitters, but also i the L1 latches. Furthermore, L1 latches with oututs cause eedless ower dissiatio i the circuits they drive whe uecessarily erturbed. If a C2 clock were allowed to free-ru, the for each cycle whe the latch cotet was a do't care, all the dowstream logic would Poly Flight Lie Termiatio Poly(i) Diffusio Poly (Flight lie) Diffusio(i) Figure 2: Poly & Diffusio Flight lie Illustratio Poly Gate Diffusio (Flight lie)

5 be ueccessarily erturbed. Sice a LSSD 4 desig has the bulk of its logic betwee L2 ad L1 latches, this is a area where ower maagemet is cocetrated. Oerad Isolatio Oerad isolatio is aother techique used i the 403GA for ower coservatio. Oerad isolatio, as the ame imlies, isolates sectios of circuitry from "seeig" chages o their iuts uless they are exected to resod to them. Figure 4 illustrates oerad isolatio for a simle ALU. I a ALU, all the executio uits (logical uits, arithmetic uits, shifters ad rotators) share (a) commo oerad bus(es). If oerad isolatio is ot used, all executio uits execute cocurretly ad a sigle result is selected ad roagated. Meawhile, ower has bee eedlessly exeded i those o-selected uits. By emloyig oerad isolatio, oerads are steered oly those executio uits which are goig to be active i a give cycle. This may ot be critical i the rimitive logical uits, but it saves ower i the more robust fuctios. For the adders, it is imortat ot to forget to cotrol the carry-i sigal sice the etire state of the adders ca be affected by a chage i carry-i. The cotrol sigals for the oerad isolatio ca be the same as those used to select the result i the most simle case. Power distributio area ca also be miimized, as oly selective fuctios will be activated. Oerad Bus A t1 c1 t3 c3 t2 c2 t4 c4 Figure 4: Oerad Isolatio Fuctio 1 Fuctio 2 Fuctio 3 Fuctio 4 t1:t4 Multilexor c1:c4 Gated ad Clocked Receivers ad Commo I/O Additioal ower savigs were achieved by both clockig ad gatig the 403GA s sychroous iuts ad commo I/O receivers. 5 I the case of commo I/O, the receivers are oly active whe the system clock is low ad whe the gate eable is active. I the most simlistic realizatio, the receiver gate eable is the iverse of the driver eable. This disables the receiver whe the driver is active ad elimiates ay eedless ower due to the receiver ad ay dowstream circuit switchig. Extesive use of NFET trasfer gates NFET trasfer gates were emloyed extesively i the realizatio of latches, selectors, exclusive-ors, receivers, ad adders. The use of NFET-oly trasfer gates i the selectors ad latches allowed for the use of sigle hase clocks ad cotrols. This saved both ower ad area. I the case of latches, the trasfer gates were used for clock ad sca activatio, ad trasfer betwee L1 ad L2. 6 The selectors emloyed a PFET ull-u whose gate was cotrolled by the outut of the first iverter of the selector to rovide u-level voltage adjustmet. I fact, a PFET stack was emloyed wherei oe of the series PFET's gate was grouded. This was emloyed to more tightly cotrol the feedback curret over broad rocess rages. The chael legth of both devices was sigificatly larger tha miimum to miimize delta L effects, ad sice two devices were emloyed, the chael width variaces could also be miimized. Trade-offs were made for how much additioal iterodal caacitace was added versus cotrol of feedback curret. The use of trasfer gates certaily reseted some challeges i iut caacitace reresetatio. For the uroses of timig aalyses oly the iut caacitace whe the gate was activated was reseted. A secod caacitace value was geerated for the case whe the gate was deactivated, but this value was used to modify the et caacitace files maually whe kowledge of the gate activatio was kow. This is esecially imortat whe multile selector data iuts are beig drive from a sigle source ad oly a artial set of selects are active. The differece i iut caacitace betwee a active ad iactive gate is aroximately oe order of magitude. Hece, by alyig kowledge of the gate activatio, the caacitace file could be reduced for the et ad a lower ower circuit could be used to drive it. As metioed earlier, the use of trasfer gates had the added beefit of easig the floatig gate icororatio. Results The PowerPC 403GA has a tyical ower dissiatio of 200mW at 25 mhz. This was determied by ruig a "tyical" istructio mix comrised of the followig: 33% brach, 25% load, 17% comare, 17% arithmetic ad 8% store oeratios. The code assumes a 90% Istructio Cache hit rate. The worst case ower assumes maximum I/O switchig activity ad heavy use of the Caches. The wait state ower is 30 mw with the system clock ruig. The average iteral et caacitace is aroximately 90 ff. The distributio of ower-erformace codes is heavily biased to the low ed of the offerig, with the average beig D-ower. Figure 5 is a histogram of all radom logic gate drive stregths emloyed o the PowerPC 403GA. Summary I summary, techiques have bee described wherei a robust graular ower/erformace cell library has bee develoed ad used i cojuctio with algorithmic arasitic caacitace miimizatio ad other ower maagemet techiques to roduce a ower efficiet embedded cotroller.

6 Number of Radom Logic Circuits A B C D E F G H I J K L M N O P Q R S U V W Power/erformace Code Figure 5: Histogram of Radom Logic Circuit Power/Performace Codes Ackowledgmets I would like to thak the etire PowerPC403 develomet team, based i Research Triagle Park, N.C., for all their efforts i develoig a first ass successful desig ad their coscious efforts to maage ower. I also thak Joh McKeema, David Artz, Charlie Hoffma, Dave Weitzel, Doa Correale, Chuck Freema ad Steve Harris for their cotributios i the rearatio of this mauscrit. Fially, may thaks to Ala Botula for his CMOS5L techology kowledge. Refereces 1. IBM PowerPC 403GA 32-Bit RISC Embedded Cotroller data sheet Documet No.MPR403DSU CMOS5L Desig Maual, IBM Egieerig Secificatio 02G A.P.Chadrakasa,S.Sheg ad R.W.Broderse, "Low- Power CMOS Desig," i IEEE Joural of Solid State Circuits, Vol. 27, NO. 4, Aril 1992, g E.B.Eichelberger ad T.W.Williams, "A logic desig structure for LSI testability," i Proc. 14th Desig Automatio Cof., Jue 1977, Athoy Correale, Jr., "Power Reductio Techique for Chis Usig Commo I/O'", i IBM Techical Disclosure Bulleti, Vol. 37, No. 01, Jauary Athoy Correale, Jr., "Desig cosideratios of a static LSSD olarity hold latch air", i IBM Joural of Research ad Develomet, Vol.28, No. 4, July 1984, TM IBM, PowerPC, ad PowerPC 403GA are all trademarks of Iteratioal Busiess Machies Cororatio.