Processing Information: The Digital Abstraction. Concrete Encodings of Information
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1 page Processing Information: The igital bstraction. Making bits concrete 2. Getting bits under contract 3. Processing bits with transistors Processing Information oncrete Encodings of Information To this point we ve discussed encoding information using bits. ut where do bits come from? If we re going to design a machine that manipulates information, how should that information be physically encoded? What makes a good bit? - cheap (we want a lot of them) - stable (reliable, repeatable) - ease of manipulation (access, transform, combine, transmit, store) Processing Information 2
2 page 2 ubstrate for omputation We can build devices for processing and representing bits using almost any physical phenomenon Wait! Those last ones might have potential... trained elephants engraved stone tablets sequences of amino acids polarization of a photon fluid pressure Processing Information 3 Representing Information with Voltage Representation of each point (x, y) on a &W Picture: volts: LK volt: WHITE.37 volts: 37% Gray etc. Representation of a picture: can points in some prescribed raster order generate voltage waveform How much information at each point? Processing Information 4
3 page 3 Information Processing = omputation First let s introduce some processing blocks: v opy v INV v -v Processing Information 5 Let s build a system! opy INV input opy opy INV INV (In Theory) (Reality) opy INV? output Processing Information 6
4 page 4 Why id Our ystem Fail? Why doesn t reality match theory?. OP Operator doesn t work right 2. INVERION Operator doesn t work right 3. Theory is imperfect 4. Reality is imperfect 5. Our system architecture stinks NWER: all of the above! Noise and inaccuracy are inevitable; we can t reliably reproduce infinite information-- we must design our system to tolerate some amount of error if it is to process information reliably. Processing Information 7 The Key to ystem esign system is a structure that is guaranteed to exhibit a specified behavior, assuming all of its components obey their specified behaviors. How is this achieved? ontracts Every system component will have clear obligations and responsibilities. If these are maintained we have every right to expect the system to behave as planned. If contracts are violated all bets are off. Processing Information 8
5 page 5 The igital Panacea... Why IGITL? because it keeps the contracts simple! The price we pay for this robustness? or ll the information that we transfer between modules is only crummy bit! ut, in exchange, we get a guarantee of reliable processing. Processing Information 9 The igital bstraction Real World Manufacturing Variations Noise Ideal bstract World / its Volts or Electrons or Ergs or Gallons Keep in mind, the world is not digital, we simply engineer it to behave that way. Furthermore, we must use real physical phenomena to implement digital designs! Processing Information
6 page 6 Using Voltages igitally Key idea: don t allow to be mistaken for a or vice versa Use the same uniform representation convention, for every component and wire in our digital system To implement devices with high reliability, we outlaw close calls via a representation convention which forbids a range of voltages between and. Valid Invalid Forbidden Zone Valid volts ONEQUENE: Notion of VLI and INVLI logic levels Processing Information igital Processing Element tatic iscipline combinational device is a circuit element that has one or more digital inputs one or more digital outputs a functional specification that details the value of each output for every possible combination of valid input values a timing specification consisting (at minimum) of an upper bound t pd on the required time for the device to compute the specified output values from an arbitrary set of stable, valid input values input input input Output a if at least 2 out of 3 of my inputs are a. Otherwise, output. I will generate a valid output in no more than 2 minutes after seeing valid inputs output Processing Information 2
7 page 7 ombinational igital ystem set of interconnected elements is a combinational device if each circuit element is combinational every input is connected to exactly one output or to some vast supply of s and s the circuit contains no directed cycles No feedback (yet!) ut, in order to realize digital processing elements we have one more requirement! Processing Information 3 That must mean that we have different standards for outputs than we do for inputs V in (marginally valid) Noise Margins! oes a wire obey the static discipline? V out (invalid!) No! combinational device must restore marginally valid signals. It must accept marginal inputs and provide unquestionable outputs (to leave room for noise). Valid Noise VLI INPUT REPREENTTION Forbidden Zone V ol V il V ih V oh NOIE MRGIN VLI OUTPUT REPREENTTION Valid That s what the small print was about! volts Processing Information 4
8 page 8 uffer simple UFFER: Voltage Transfer urve V out V oh V ih V il V ol V ol V il V ih V oh V in tatic iscipline requires that our devices avoid the forbidden zones, which correspond to valid inputs but invalid outputs. Net result: combinational devices must have GIN > and be NONLINER. Processing Information 5 igital Processing Elements ome digital processing elements occur so frequently that we give them special names and symbols I will copy and restore my input to buffer my output I will output the complement of my input inverter I will only output a N if all my inputs are I will output a if any OR of my inputs are I will only output a if an XOR odd number of my inputs are Processing Information 6
9 page 9 igital Processing Elements ome digital processing elements occur so frequently that we give them special names and symbols buffer inverter N OR XOR Processing Information 7 For your information only (not exam material) uilding Gates in ilicon emiconductors can be used to achieve both requirements of a digital system, gain and nonlinearity. emiconductors are special elements that neither tend to give up or accept electrons in order to stabilize their outer orbitals. Pure crystalline samples of these elements tend to be nonconducting insulators. However, with the introduction of a small impurities, they can be coerced into conducting an electric current. Moreover, the amount of conductance can be controlled with an externally provided electric field. This property has been used to create electrically controlled devices for conducting current. ome of the first devices were made from Germanium, but over time, ilicon, has proven to be the most useful. Processing Information 8
10 page n For your information only (not exam material) PN Junctions as Insulation There are two kinds of impurities that we can introduce, those with mobile electrons in their outer orbitals (N-type), and those lacking mobile electrons (P-type). oth materials conduct, but their behavior is even more interesting when they come in contact. If two materials, with opposite impurities are in placed contact a junction is formed. The mobile carriers about each side of the junction move: p n diffusion of holes from P to N and electrons from N to P depletion of majority carriers in boundary region. drift of majority carriers due to E field formed by fixed ions acts in opposite direction of diffusion depletion region p If V PN, the two regions are electrically isolated t equilibrium, the sum of the drift currents = sum of the diffusion currents. depletion region is formed with a voltage across it due to induced field. t room temp, with doping concentrations of 5 /cm 3, this voltage is.6v. The net result is a diode: n p I pn V pn Processing Information 9 For your information only (not exam material) FET = Field-Effect Transistor We can layout junctions in various ways to take advantage of, and control their conducting and insulating properties. This creates a device called a transistor. The four terminals of a FET (gate, source, drain and bulk) connect to conducting surfaces that generate a complicated set of electric fields in the channel region which depend on the relative voltages of each terminal. gate inversion happens here E h source E v drain INVERION: sufficiently strong vertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain. bulk ONUTION: If a channel exists, a horizontal field will cause a drift current from the drain to the source. Processing Information 2
11 page For your information only (not exam material) Qualitative NFET Model G I = Picture shows configuration when < V TH n+ n+ Terminal with higher voltage is labeled, the other is labeled so I >=. p mobile holes, fixed negative ions depletion layer no mobile carriers, but fixed negative ions (slight intrusion into n+, but mostly in p area) mobile electrons, fixed positive ions (n+ means heavily doped with donors, doesn t imply positive charge!) The substrate (bulk) terminal for nfets is almost always connected to ground to keep V PN. Processing Information 2 Linear Operating Region V > V TH < V < V sat For your information only (not exam material) I L Why is this bigger here than on other side? Larger creates deeper channel which increases I I I proportional to µ (W/L) Increasing Larger V increases drift current but also reduces vertical field component which in turn makes channel less deep. t some point, electrons are traveling as fast as possible through the channel ( velocity saturation ) and the current stops growing linearly. V Processing Information 22
12 page 2 aturated Operating Region V > V TH V sat < V For your information only (not exam material) I L = L - δl δl V sat -V TH This looks just like a FET with a channel length of L < L. horter L implies greater I. s V increases, δl gets larger. When V = -V TH the vertical field component is reduced and the channel is pinched-off. Electrons just keep traveling across depletion region I Increasing VG V Processing Information 23 NFET Review For your information only (not exam material) + G G + V Operating regions: - - cut-off: < V TH linear: V TH V < V sat.8v I linear saturation -V TH saturation: V TH V V sat V Processing Information 24
13 page 3 P-channel MOFET For your information only (not exam material) G p+ p+ threshold voltage is negative since we need attract holes to form inversion layer PFET is built inside its own substrate : a n-type well diffused into p-type bulk substrate. n p The substrate (bulk) terminal for pfets is almost always connected to power supply to keep V PN. Processing Information 25 PFET Review For your information only (not exam material) - G G + V Operating regions: - + cut-off: > V TH.8V -V linear: V TH V > V sat - saturation: V TH V V sat -V TH saturation linear -I Processing Information 26
14 page 4 Finally Using Transistors to uild Logic Gates! V Inverter recipe: pullup: make this connection when near so that V OUT = V V OUT pulldown: make this connection when near V so that V OUT = Processing Information 27 MO Inverter = v I PU = v V in G = power supply I PU V out = 2v = 3v = 4v I PU vs V OUT for PULLUP V OUT G I P = V I P = 5v = 4v = 3v = 2v = v I P vs V OUT for PULLOWN V OUT Processing Information 28
15 page 5 MO Inverter VT I pd I pu V in =.5V V out V out I pd I pu V in = 3.5V I pd I pu V in =.5V V out V out I pd I pu V in = 4.5V I pd I pu V in = 2.5V V OL V IL V IH V OH V in V out V out When both FETs are saturated, small changes in V in produce large changes in V out Processing Information 29 an We uild a MO uffer? Not with just two transistors! Here s why: V OUT Nfets turn off when falls below the threshold voltage V TH. o, even if the input voltage is, say, 5V, then the pullup will turn off when V OUT reaches 5V V TH = 4.2V. The pulldown will also turn off before V OUT reaches V. V OUT V TH,N V TH,P Processing Information 3
16 page 6 omplementary Pullups and Pulldowns Now you know what the in MO stands for! We want complementary pullup and pulldown logic, i.e., the pulldown should be on when the pullup is off and vice versa. pullup pulldown F(,,n) on off driven off on driven on on driven X off off no connection ince there s plenty of capacitance on the output node, when the output becomes disconnected it remembers its previous voltage -- at least for a while. The memory is the load capacitor s charge. Leakage currents will cause eventual decay of the charge (that s why RMs need to be refreshed!). Processing Information 3 What a nice V OH you have... MO omplements Thanks. It runs in the family... conducts when is high conducts when is low conducts when is high and is high:. conducts when is low or is low: + =. conducts when is high or is high: + conducts when is low and is low:. = + Processing Information 32
17 page 7 Two Input Logic Gate What function does this gate compute? Processing Information 33 Here s nother What function does this gate compute? Processing Information 34
18 page 8 General MO Gate Recipe tep. Figure out pulldown network that does what you want, e.g., F = *(+) tep 2. Walk the hierarchy replacing nfets with pfets, series subnets with parallel subnets, and parallel subnets with series subnets tep 3. ombine pfet pullup network from tep 2 with nfet pulldown network from tep to form fullycomplementary MO gate. ut isn t it hard to wire it all up? Processing Information 35 One Last Exercise Lets construct a gate to compute: F = + = NOT(OR(,N(,))) V dd tep : The pull-down network tep 2: The complementary pull-up network F Processing Information 36
19 page 9 One Last Exercise Lets construct a gate to compute: F = + = NOT(OR(,N(,))) F tep : The pull-down network tep 2: The complementary pull-up network tep 3: ombine and Verify V dd F Processing Information 37 Review The igital ontract and ompromise: ) In order to design processing elements that are robust to outside influences (like noise) we choose to use only a narrow range of possible voltages to encode valid information. Moreover, valid voltage ranges are separated by regions of invalid ranges. 2) The range of valid output voltages must more demanding than the range of valid input voltages to provide a noise margin. 3) Gain and nonlinearity are required to provide noise margins. Transistors, in particular, field-effect transistors can provide both the required gain and nonlinearity ) Gain is used to move rapidly through the invalid voltage range 2) Nonlinearities of cut-off and saturation provide switch-like behavior 3) NFET transistors are good at pulling down nodes, PFETs are good at pulling nodes up 4) omplementary switch networks are used to build useful digital logic gates. Processing Information 38
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