InGaAs-based Tunneling Field-effect Transistor with Stacked Dual-metal Gate with PNPN Structure for High Performance

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.2, APRIL, 2017 ISSN(Print) ISSN(Online) InGaAs-based Tunneling Field-effect Transistor with Stacked Dual-metal Gate with PNPN Structure for High Performance Ra Hee Kwon *, Sang Hyuk Lee *, Young Jun Yoon, Jae Hwa Seo, Young In Jang, Min Su Cho, Bo Gyeong Kim, Jung-Hee Lee, and In Man Kang Abstract We have proposed an InGaAs-based gateall-around (GAA) tunneling field-effect transistor (TFET) with a stacked dual-metal gate (DMG). The electrical performances of the proposed TFET are evaluated through technology computer-aided design (TCAD) simulations. The simulation results show that the proposed TFET demonstrates improved DC performances including high on-state current (I on ) and steep subthreshold swing (S), in comparison with a single-metal gate (SMG) TFET with higher gate metal workfunction, as it has a thinner sourcechannel tunneling barrier width by low workfunction of source-side channel gate. The effects of the gate workfunction on I on, the off-state current (I off ), and S in the DMG-TFETs are examined. The DMG-TFETs with PNPN structure demonstrate outstanding DC performances and RF characteristics with a higher n- type doping concentration in the In 0.8 Ga 0.2 As sourceside channel region. Index Terms Band-to-band tunneling (BTBT), tunneling field-effect transistors (TFETs), InGaAs, dual-metal gate, PNPN Manuscript received Aug. 24, 2016; accepted Nov. 1, 2016 A part of this work was presented in the 2016 Asia-Pacific Workshop on Fundamentals and Applications of advanced Semiconductor Devices, Hakodate in Japan, Jul School of Electronics Engineering, Kyungpook National University, Daegu , Korea * Ra Hee Kwon and Sang Hyuk Lee are co-first author imkang@ee.knu.ac.kr I. INTRODUCTION The tunneling field-effect transistor (TFET) is considered a next-generation logic device based on the CMOS technology [1]. TFETs should have low power consumption and subthreshold swing (S) below 60 mv/dec [2]. The on-state current (I on ) of the TFETs based on Si, however, is very low; therefore, it is necessary that new semiconductor materials replace Si [3]. The III-V compound semiconductor TFETs have been raised as substitutes for the Si TFETs [4]. From among various III-V materials, The InGaAs has various merits such as high electron mobility, small band gap, and low effective mass [5, 6]. In particular, as the Incomposition increases, the electron transport characteristics of InGaAs improve. The high-k dielectrics deposited by atomic-layer deposition (ALD) have been researched to achieve good interfacial qualities with InGaAs [7]. Furthermore, the use of nano-scale gate-allaround (GAA) FETs cna improve the gate controllability [8]. The improved gate controllability of TFETs improves the current drivability and the suppression of leakage current. In this paper, the GAA InGaAs-based TFETs with the stacked dual-metal gate (DMG) structures are designed and are investigated using technology computer-aided design (TCAD) simulations. The channel region of the designed TFET is divided into the source-side channel and the drain-side channel, which are termed as the top and the bottom of channel, respectively. The DMG structure and the source-side channel with small bandgap

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.2, APRIL, 2017 Fig. 1. Schematic of SMG-TFET, DMG-TFET. energy at a high In-composition can boost the Ion of the proposed TFETs [9-11]. The electrical performances of the DMG GAA TFETs with PNPN structure are investigated [12, 13]. It is observed that the various parameters of the proposed devices are extracted in such as Ion, Ioff, S, gate capacitance (Cgg), intrinsic delay time (τ), cut-off frequency (ft), etc. 231 Fig. 2. Transfer curves of InGaAs-based SMG- and DMGTFETs. drain channel length (LDC) [14]. The workfunctions of the SMG (ψsmg) are 4.46 ev and 4.61 ev. For the DMGTFET, the workfunction of the source-side gate metal (M1) (ψm1) is 4.46 ev and that of the drain-side gate metal (M2) (ψm2) is 4.61 ev. The doping concentrations of the p+-source, p--source-side channel, p--drain-side channel, and n+-drain are cm 3, cm 3, cm 3, and cm 3, respectively. The ATLAS 2-D simulation was used for demonstrating the performance of this device, and it includes the nonlocal band-to-band tunneling (BTBT) model, the Shockley Read Hall (SRH) recombination model, the Fermi-Dirac statistical model, the band-gap narrowing model, and the trap-assisted tunneling (TAT) model for accuracy in the simulations [15]. The S from the IDS VGS curves is defined as the average reverse slope of the log (drain current) (IDS) between the two points where the IDS begins to increase abruptly and where the IDS = 10-7 A/μm. The Ion is defined as the IDS at a gate voltage (VGS) of 0.5 V and a drain voltage (VDS) of 0.5 V. III. RESULTS AND DISCUSSION II. DEVICE STRUCTURE AND DESIGN 1. DMG-TFETs compared to SMG-TFETs Fig. 1 shows the cross-sectional view of a singlemetal gate GAA InGaAs-based TFET (SMG-TFET) with a gate length (LG) of 50 nm, a radius (R) of 10 nm, and a gate oxide thickness (tox) of 3 nm. The DMG GAA InGaAs TFET (DMG-TFET) is shown in Fig. 1. The devices consist of an In0.53Ga0.47As source, In0.8Ga0.2As source-side channel, In0.53Ga0.47As drain-side channel, and In0.53Ga0.47As drain. The channel region is divided into two parts, a source-side channel length (LSC) and a Fig. 2 shows the IDS-VGS curves for the InGaAs-based TFETs with the SMG- and the DMG-structures. The DMG-TFET has approximately 50 % higher than that of the SMG-TFET with a ψsmg of 4.61 ev, because the potential well in the source-side channel goes down by a small ψ M1. The I off of the DMG-TFET, however, increases slightly due to the lowering of the barrier between the source-side channel and the drain-side channel,

3 232 RA HEE KWON et al : INGAAS-BASED TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKED DUAL-METAL GATE Table 1. Performance summary of SMG- and DMG-TFETs Parameters SMG- TFET (ψ SMG = 4.46 ev) DMG- TFET (ψ M1 = 4.46 ev, ψ M2 = 4.61 ev) SMG-TFET (ψ SMG = 4.61 ev) V t [V] I on [A/μm] I off (@ V G = 0 V) [A/μm] I on/i off ratio S [mv/dec] compared to that of the SMG-TFET with a higher ψ SMG. The SMG-TFET with a ψ SMG of 4.46 ev has not only a high I on but also high I off. Fig. 3 shows the energy band diagrams below the gate oxides for the SMG- and DMG-TFETs in the off-state (V GS = 0 V, V DS = 0.5 V). The energy band potential of the SMG-TFET with a ψ SMG of 4.46 ev in the off-state is a low barrier between the source-side channel and the drain-side channel junction. Therefore, the I off of the proposed TFET with a low workfunction at the drain-side channel is higher than that of the proposed TFET with a high workfunction at the drain-side channel. The DMG structure results in a thinner energy barrier between the source region and the source-side channel region in an on-state (V GS = V DS = 0.5 V), as shown in Fig. 3. Therefore, the I on and subthreshold slope of the DMG-TFET are higher than that of the SMG-TFET with a higher ψ SMG. The extrapolated I on values of the SMG-TFET with higher ψ SMG, the SMG-TFET with lower ψ SMG and the DMG- TFET were 1.01 ma/μm, 2.28 ma/μm and 1.6 ma/μm, respectively. In addition, the S values of the SMG-TFET with higher ψ SMG, the SMG-TFET with lower ψ SMG and the DMG-TFET were 20.1 mv/dec, 21.6 mv/dec and 15.8 mv/dec, respectively. The device performance is summarized in Table 1. The DMG-TFET can be applied to low-power devices as it has a low I off and a high I on /I off ratio. 2. DC Characteristics of DMG-TFETs Fig. 4 shows the I DS V GS curves of the proposed TFETs for different L SC s. The region that is confined by the L SC forms an electron well in the source-side channel, which increases the tunneling current probability. As the L SC becomes longer, the electron well becomes wider. The width of the electron well is the shortest at an L SC of Fig. 3. Energy band diagrams below gate oxide of SMG- and DMG-TFETs in off-state, on-state. Fig. 4. Transfer characteristics of the proposed TFETs with different L SC s. 5 nm. Thus, the tunneling barrier width at L SC = 5 nm is relatively thicker when compared to the tunneling barrier width at a different L SC. Therefore, the I on at L SC = 5 nm has the lowest value. The I on increases and the tunneling barrier width decreases steadily as the L SC becomes longer. Therefore, BTBT in the DMG-TFETs occurs easily at longer L SC s. The DMG-TFETs with long L SC s

4 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.2, APRIL, Fig. 5. The energy band diagrams below gate oxide with different L SC at the on-state (V GS = V DS = 0.5 V), the offstate (V GS = 0 V, V DS = 0.5 V). Fig. 6. Electrical performances for various L SC s I on and I off, S and I on /I off ratio of the DMG-TFETs as functions of L SC in the In 0.8 Ga 0.2 As source-side channel metal gate region. have the shifted the V t higher I off. Fig. 5 shows the energy band diagrams with different L SC s in the on-state with V GS = V DS = 0.5 V. The tunneling barrier of the devices with L SC = 5 nm is the widest, as shown in Fig. 5. Therefore, the I on at L SC = 5 nm is lower than that at a different L SC. The DMG-TFET with L SC = 5 nm has a higher conduction band edge (E c ) to increase the tunneling barrier width. The tunneling barrier width in the proposed device becomes lesser as the L SC becomes longer. Fig. 5 shows the energy band diagrams for different L SC s the off-state with V GS = 0 V and V DS = 0.5 V. The tunneling region increases monotonously as the L SC becomes longer. When the tunneling region is larger, the I off in the off-state increases. Therefore, the I off of the device is lower as the L SC is below 10 nm. Fig. 6 and show the I on, I off, S, and the I on /I off ratio as a function of the L SC. The I on increases as the L SC becomes longer until L SC is 20 nm. The reason is that the tunneling barrier width decreases steadily until L SC is 20 nm. The I on becomes saturated as L SC increases beyond 20 nm. The S value of the device with L SC = 15 nm is the lowest. The tunneling barrier width between the source region and the source-side channel region at L SC = 15 nm is narrow. The S value of the proposed TFET increases because of the increase in I off as L SC increases above 20 nm. However, the I off at L SC = 15 nm is larger than that at L SC = 10 nm. The I on /I off ratio at L SC = 15 nm is less than The electrical performances at an L SC of 10 nm are superior. The DMG-TFET is optimized as L SC is 10 nm. The proposed TFET devices can have low power consumptions with I off of A/μm and S of 15.8 mv/dec. 3. DC Performances of DMG-TFETs with PNPN Structure Fig. 7 shows the I DS V GS curves of the TFETs with different doping concentrations (D SC s) in the InGaAs source-side channel. The D SC s were varied from intrinsic to n-type of cm 3. The device with a cm 3

5 234 RA HEE KWON et al : INGAAS-BASED TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKED DUAL-METAL GATE Fig. 7. The I DS -V GS curves for different D SC s of the In 0.8 Ga 0.2 As source-side channel region. Fig. 8. I on and I off as functions of D SC. of the D SC has an I on of 2.9 ma/μm, which is about 2 times higher than that of the device with a D SC of cm 3. As the D SC increases, the tunneling barrier width decreases slightly. The proposed TFET had a lower I off while maintaining a high I on. The effect of high D SC is noticeable in the I on. The high D SC makes the energy barrier to source-side channel thin. Consequently, the tunneling barrier between the source region and the channel region becomes thinner for the given operating condition, which increases the probability of source-tochannel BTBT [16]. In case of D SC of cm 3, the highest I on and a lower S were obtained because of the narrower tunneling barrier width. Fig. 8 shows the I on and S as a function of a D SC. At the D SC of cm 3, the highest I on of 2.9 ma/μm and the lowest S of 15 mv/dec were obtained because of the narrow tunneling barrier width. The proposed TFET demonstrates that the improvement in S is less because the PNPN DMG- TFETs in a given operating mode have already strong gate controllability because of the low gate workfunction Fig. 9. RF parameters Capacitances (C gs, C gd, and C gg ), τ, as functions of the D SC. over the source-side channel region. IV. RF PERFORMANCES The radio frequency (RF) parameters are extrapolated from the Y-parameter simulations, by the small-signal equivalent circuit analysis [14, 17, 18]. Fig. 9 shows the capacitances (C gs, C gd, and C gg ) as functions of the D SC. In ordinary TFETs, the value of C gd is larger than that of C gs [19]. The proposed TFET demonstrates a similar trend. The C gs and C gd are almost constants dependent on the D SC. Because the electron density of the source-side channel is much higher, the D SC has an insignificant effect on C gs. The C gd is not associated with the D SC. As a result, the C gg is nearly constant and is dependent on the D SC. The extracted τ is plotted in Fig. 9. τ is defined as following equations. t C V gg DD = (1) I on

6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.2, APRIL, Future Planning (2016R1C1B ), and in part by Samsung Electronics Company. This work was supported by the BK21 Plus project and Global Ph.D. Fellowship Program through the NRF funded by the Ministry of Education (21A , 2013H1A2A ). This work was supported by IDEC (DEA Tool, MPW). REFERENCES Fig. 10. The g m and f t of the DMG-TFETs as a function of the D SC. The τ is inversely proportional to I on and directly is proportional to C gg. The I on reaches its maximum value at a D SC of cm 3. Accordingly, the τ at a D SC of cm 3 decreases dramatically compared to that at a D SC of cm 3. Fig. 10 shows the g m and the f t as functions of the D SC. The improved g m of the DMG-TFETs is due to the superior current drivability. The variation of g m is much greater than that of C gg as can be observed from Fig. 9 and 10. Therefore, the f t confirms a large rise for a D SC of cm 3. V. CONCLUSIONS We have investigated the stacked DMG GAA TFETs based on InGaAs. The proposed TFET with a high doping concentration at the source-side channel had an I on of 2.9 ma/µm, I off of A/µm, I on /I off ratio of , S of 15 mv/dec, τ of 42 fs, g m of 14 ms/µm, and f t of 8.8 THz at V DS = 0.5 V. The proposed TFET demonstrated a low power consumption and high performance, which varied according to the values L SC, L DC, and the doping concentration at the source-side channel region. Consequentially, the performance of the proposed TFET could be improved through design improvement using the DMG structure. ACKNOWLEDGMENTS This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & [1] A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, Tunnel field-effect transistor without gate-drain overlap, Applied Physics Letters, Vol.91, No.5, pp , Jul., [2] Y. J. Yoon, J. H. Seo, S. Cho, H.-I. Kwon, J.-H. Lee, and I. M. Kang, Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications, Journal of Semiconductor Technology and Science, Vol.16, No.2, pp , April [3] U. E. Avci, D. H. Morris, and I. A. Young, Tunneling Field-Effect Transistors: Prospects and Challenges, Journal of the Electron Devices Society, Vol.3, No.3, pp.88-95, May., [4] R. Iida, S.-H. Kim, M. Yokoyama, N. Taoka, S.-H. Lee, M. Takenaka, and S. Takagi, High transconductance self-aligned gate-last surface channel In 0.53 Ga 0.47 As MOSFET, Electron Devices Meeting, IEDM Technicla Digest. IEEE International, 5-7, pp , Dec., [5] R. Iida, S.-H. Kim, M. Yokoyama, N. Taoka, S.-H. Lee, M. Takenaka, and S. Takagi, Planar-type In 0.53 Ga 0.47 As channel band-to-band tunneling metal-oxidesemiconductor field-effect transistors, Journal of Applied Physics, Vol.110, No.12, pp , Dec., [6] Y. Sun, E. W. Kiewra, S. J. Koester, N. Ruiz, A. Callegari, K. E. Fogel, D. K. Sadana, J. Fompeyrine, D. J. Webb, J.-P. Locquet, M. Sousa, R. Germann, K. T. Shiu, and S. R. Forrest, Enhancement-Mode Buried-Channel In 0.7 Ga 0.3 As/ In 0.52 Al 0.48 As MOSFETs With High-κ Gate Dielectrics, IEEE Electron Device Letters, Vol.28, No.6, pp , June., [7] H. Zhao, Y. Chen, Y. Wang, F. Zhou, F. Xue, and J. Lee, InGaAs Tunneling Field-Effect-Transistors

7 236 RA HEE KWON et al : INGAAS-BASED TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKED DUAL-METAL GATE With Atomic-Layer-Deposited Gate Oxides, IEEE Transactions on Electrin Devices, Vol.58 No.9, pp , Sept., [8] A. S. Verhulst, B. Soree, D. Leonelli, W. G. Vandenberghe, and G. Groeseneken, Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor, Journal of Applied Physics, Vol.107, No. 2, pp , Jan., [9] K. boucart and A. M. Ionescu, Double-Gate Tunnel FET With High-κ Gate Dielectric, IEEE Transactions on Electron Devices, Vol.54, No.7, pp , July., [10] Wataru Saito, Yoshiharu Takada, Masahiko Kuraguchi, Kunio Tsuda, and Ichiro Omura, Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations, Journal of Nanoscience and Nanotechnology, Vol.15, No.10, pp , Oct., [11] N. Cui, R. Liang, and J. Xu, Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation, Applied Physics Letters, Vol.98, No.14, pp , Apr., [12] N. Cui, R. Liang, and J. Xu, Single Grain Boundary Dopingless PNPN Tunnel FET on Recrystallized Polysilicon: Proposal and Theoretical Analysis, IEEE Journal of the Electron Devices Society, Vol.3, No.3, pp , May., [13] D. B. Abdi and M. J. Kumar, In-Built N + Pocket p-n-p-n Tunnel Field-Effect Transistor, IEEE Electron Device Letters, Vol.35, No.12, pp , Dec., [14] Y. J. Kim, Y. J. Yoon, J. H. Seo, S. M Lee, S. Cho, J.-H. Lee, and I. M. Kang, Effect of Ga fraction in InGaAs channel on performances of gate-allaround tunneling field-effect transistor, Semiconductor Science and Technology, Vol.30, No.1, pp , Nov., [15] ATLAS User s Manual, SILVACO International, Feb., [16] S. Cho and I. M. Kang, Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics, Current Applied Physics, Vol.12, No.3, pp , May., [17] J. H. Seo, Y. J. Yoon, S. Lee, J.-H. Lee, S. Cho, and I. M. Kang, Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling fieldeffect transistor (TFET), Current Applied Physics, Vol.15, No.3, pp , May., [18] S. Cho, K. R. Kim, B.-G. Park, and I. M. Kang, Non-Quasi-Static Modeling of Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistor and Its Model Verification up to 1 THz, Japanese Journal of Applied Physics, Vol.49, No.11, pp , Nov., [19] Y. Yang, X. Tong, L.-T. Yang, P.-F. Guo, L. Fan, and Y.-C. Yeo, Tunneling Field-Effect Transistor: Capacitance Components and Modeling, IEEE Electron Device Letters, Vol.31, No.7, pp , Jul., Ra Hee Kwon She received the B.S. degree in electrical engineering from the school of Electronics Enginering, Kyungpook National University (KNU), Daegu, Korea, in She is currently working toward the M.S. degree in electrical engineering with the School of Electronics Engineering (SEE), Kyungpook National University (KNU). Her research interests include the design, fabrication, and characterization of compound CMOS, compound tunneling FET, and tunneling FET with interface traps. Sang Hyuk Lee is currently with the School of Electronics Engineering (SEE), Kyungpook National University (KNU), working toward a B.Sc. degree in Electrical Engineering. His research interests include the design, fabrication, and characterization of compound CMOS, tunneling FETs, and compound transistors.

8 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.2, APRIL, Young Jun Yoon He received the B.S. degree in electrical engineering from the School of Electronics Engineering, Kyungpook National University (KNU), Daegu, Korea, in He is currently working toward the Ph.D. degree in electrical engineering with the School of Electronics Engineering (SEE), Kyungpook National University (KNU). His research interests include the design, fabrication, and characterization of nanoscale tunneling FETs, GaNbased transistors, and GaN-based circuits. Jae Hwa Seo He received the B.S degree in electrical engineering from the School of Electronics Enignnering, Kyungpook National University (KNU), Daegu, Korea, in He is currently working toward the Ph.D. degree in electrical engineering with the school of Electronics Enginnering (SEE), Kyungpook National University (KNU). His research interests include design, fabrication and characterization of nanoscale CMOS, tunneling FETs, III-V compound transistors, and junctionless silicon devices. Young In Jang He received the B.S. degree in electrical engineering from the School of Electronics Engineering, Kyungpook National University (KNU), Daegu, Korea, in He is currently working toward the M.S. degree in electrical engineering with the School of Electronics Engineering (SEE), Kyungpook National University (KNU), His research interests include the design, fabrication, and characterization of compound CMOS, GaN-based devices, and RF modeling. Min Su Cho He received the B.S. degree in Computer Engineering from the College of Electrical and Computer Engineering, Chungbuk National University (CBNU), Cheongju, Chungcheongbuk-do, Korea, in He is currently working toward the M.S. degree in electrical engineering with the School of Electronics Engineering (SEE), Kyungpook National University (KNU), His research interests include design, fabrication, and characterization of compound CMOS, tunneling FETs, and III-V compound transistors. Bo Gyeong Kim She received the B.S. degree in electrical engineering from the school of Electronics Enginering, Kyungpook National University (KNU), Daegu, Korea, in She is currently working toward the M.S. degree in electrical engineering with the School of Electronics Engineering (SEE), Kyungpook National University (KNU). Her research interests include the design, fabrication, and characterization of compound tunneling FETs and III-V compound transistors. Jung-Hee Lee He received the B.S. and M.S. degrees in electronic engineering from Kyungpook National University, Daegu, in 1979 and 1983, respectively, the M.S. degree in electrical and computer engineering and computer engineering from Florida Institute of Technology, Melbourne, in 986, and the Ph.D. degree in electrical and computer engineering from North Carolina State University, Raleigh, in His doctoral research concerned carrier collection and laser properties in monolayer-thick quantum-well heterostructures. From 1990 to 1993, he was with the Compound Semiconductor Research Group, Electronics and Telecommunication Research Institute, Daejeon, Korea. Since 1993, he has been a Professor with the School of Electronics Engineering (SEE), Kyungpook National University, Daegu. He is the author or coauthor of more than 200 publications on semiconductor materials and devices. His current research is focused on the growth of nitride-based epitaxy, the fabrication and characterization of gallium-nitride-based electronics and optoelectronic devices, atomic layer epitaxy for metaloxide-semiconductor application, and characterizations and analysis for the 3-D devices such as fin-shaped FETs.

9 238 RA HEE KWON et al : INGAAS-BASED TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKED DUAL-METAL GATE In Man Kang He received the B.S. degree in electronic and electrical engineering from School of Electronics and Electrical Engineering, Kyungpook National University (KNU), Daegu, Korea, in 2001, and the Ph.D degree in electrical engineering from School of Electrical Engineering and Computer Science (EECS), Seoul National University (SNU), Seoul, Korea, in He worked as a teaching assistant for semiconductor process education from 2001 to 2006 at Inter-university Semiconductor Research Center (ISRC) in SNU. From 2007 to 2010, he worked as a senior engineer at Design Technology Team of Samsung Electronics Company. In 2010, he joined KNU as a full-time lecturer of the School of Electronics Engineering (SEE). Now, he has worked as an assistant professor. His current research interests include CMOS RF modeling, silicon nanowire devices, tunneling transistor, low-power nano CMOS, and III-V compound semiconductors. He is a member of IEEE EDS.