Simulation of dual material ground plane bottom spacer FinFET

Transcription

1 Simulation of dual material ground plane bottom spacer FinFET Pallavi Narware 1, Dr.Vadthiya Narendar 2 1 Lecturer, Electronics and Telecommunication, Govt. Polytechnic College, Itarsi, MP, INDIA 2 Assistant Professor, Electronics and Telecommunication, MNNIT, Allahabad, UP, INDIA Abstract- FinFETs are popular in complex circuit applications due to excellent scalability and better short channel effects. Bottom spacer FinFET concept is used to achieve improved short-channel and reduced selfheating issues to solve width quantization effect. Fully depleted dual material concept provides novel features like threshold voltage roll-up, transconductance enhancement and suppression of short channel effects by work function engineering. Further, to reduce coupling of electric field between source and drain and hence reducing drain induces barrier lowering (DIBL), ground plane concept is introduced. Figures of merit (FOM) such as transconductance (gm), output conductance (gd), transconductance generation factor (TGF), early voltage (VEA), intrinsic gain (AV), cut-off frequency (ft), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are systematically presented for different active fin height using 3-D simulation of dual material ground plane bottom spacer FinFET. Index Terms- FinFET, Self-Heating, Transconductance, Multistage Devices, Threshold Voltage. I. INTRODUCTION To optimize the performance of double-gate MOSFETs, self-aligned processes and structures were proposed like FinFETs [1-3]. Multigate FinFET devices have exceptionally high packing density and improved logic performance, along with improved analog, RF and mixed-signal circuit performance in sub-32-nm node CMOS technologies[4], [5]. Bulk- FinFETs have the advantages of low cost of fabrication, low defect density, less process complexity, low self-heating, and more stability against negative bias-temperature instability [6], [7]. When compared to bulk-finfets, SOI-FinFETs have less leakage current, higher saturation current, better subthreshold behaviours, and less sensitivity to the substrate-doping [8]. But FinFETs have problems like complex spice models and RC extraction, increased layout dependencies, additional parasitic capacitances and width quantization effects [9]. The effective device width WFin of a single fin where HFin is height of the fin and TFin is thickness of the fin is WFin ~ 2HFin + TFin (1) The problem of highly energetic and accelerated hot carriers damaging the Si SiO2 interface can be solved using dual material gate field effect transistor, using gate-material engineering instead of doping engineering [10]. Two materials with different work function improve carrier transport efficiency resulting in screening effect to suppress short-channel effects. To improve subthreshold slope buried oxide thickness must increase while this causes high DIBL due to electric field penetration through the BOX [11]. The ground plane (GP) concept in fully SOI MOSFET helps reduce DIBL effect and it is effective only when distance between ground plane and drain is small compared to gate length [12, 13]. So, it is not possible to achieve both reduced DIBL and high subthreshold slope for sub-100-nm channel lengths. Fully depleted SOI MOSFET with ground plane introduced in BOX (GPB) minimizes both DIBL and leakage current while improving subthreshold slope compared to conventional FD SOI MOSFET and FD SOI MOSFET with ground plane in substrate [14, 15]. In this paper we propose dual material ground plane bottom spacer FinFET to improve short channel performance. This paper is organized as follows. Section II explains device structure, process steps and models used. Section III includes two subsections that includes analog and RF performance matrices of the device including SCEs like ION/IOFF current IJIRT INTERNATIONAL JO URNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 248

2 ratio, SS and DIBL. Section IV provides conclusion that substantiates novelty of the paper. II. DEVICE STRUCTURE AND PROCESSING STEPS The device analysed has been simulated using 3D ATLAS simulator at 300K. Fig. 1 shows the threedimensional view of the device structure. The specifications considered for the device are: gate length (LG) is 20nm, gate oxide thickness (Tox) is 1.1nm, thickness of fin (TFin) is 10nm, fin height (HFin) is 60nm and source/drain extension length (Lext) is 8nm. The doping of the Silicon substrate is 1015 cm-3 p-type, source/drain are doped 1020 cm-3 n-type, active fin doping is 1015 cm-3 p-type, inactive fin doping is 1017 cm-3 p-type and polysilicon island below source/drain extension doping is 1020 cm-3 p-type. The device has symmetric dual material gate with 4.7 work function of gate near source M1 and 4.5 near drain M2 to produce more positive threshold voltage near the source. The work function of metal M1 is varied as 4.9 and 5.1 keeping work function of metal M2 constant. Fig. 1 Device structure Device simulation is performed using drift-diffusion transport model along with quantum correction for effects of quantum confinement in the inversion layer. The Lombardi constant voltage and temperature (CVT) mobility model is used which considers the effect of transverse fields along with doping and temperature dependent mobility parameters. It also models the effect of surface roughness scattering and acoustic phonon scattering. Shockley Read Hall carrier recombination model and band to band Auger recombination are considered to determine carrier lifetime and density. The silicon band gap narrowing that determines intrinsic carrier concentration in heavily doped regions is actuated. The Newton and Gummel methods are simultaneously used for the numerical solution. The proposed structure can be created by using SOIAS technology by bonded-simox approach. The proposed process flow is: [1] High dose oxygen ion implantation into the silicon wafer, followed by high-temperature annealing step to form a BOX layer. [2] On the top of single crystalline silicon, oxide layer is thermally grown followed by amorphous silicon deposition. [3] Device wafer is inverted and bonded to oxidized handle wafer. [4] Using chemical and mechanical polishing and wet chemical etching bulk of SIMOX wafer is removed. [5] BOX is removed by conventional wet etching and thermal oxidation thinning is performed. [6] Form ground plane using ion implantation of boron through silicon steps in two masking steps, resulting in p+ island formation insulated by intrinsic polysilicon after thermal anneal. [7] After silicon fin is etched over BOX, isotropic deposition of Low-K oxide to form bottom spacer around the silicon fin [8] Mask silicon film using Si3N4 followed by vertical anti-punch through (p-type for n-channel FET) implant. Due to dopant straggle through bottom spacer, the inactive fin gets eventually doped. [9] Si3N4 is etched to form gate oxide. Dual material gate using single reactive ion etching (RIE) process to simultaneously pattern dissimilar gate metals, highly uniform nanowire and CMOS transistor with adjustable work function were fabricated. Other Dual Metal Gate fabrication techniques for nanoscale transistor are metal inter diffusion, Split-Gate MOSFET using fully silicide gate process and metal wet etch process. III. SIMULATION RESULTS IJIRT INTERNATIONAL JO URNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 249

3 Fig. 2 shows threshold voltage variation. It increases with increase in work function difference. On current ION (at VGS = 1V) for different BSH values are given in fig. 3 where on current decreases with increase in BSH and work function difference. Fig. 4 shows off current IOFF (at VGS =0V) for different BSH where IOFF reduces as BSH increases. In case of conventional FD SOI MOSFET, electric field lines from the drain side approach the source through buried oxide (BOX) layer. When ground plane is used, electric field lines concentrate the field along the channel and the field coupling is minimized. This helps in reduction of DIBL and hence suppresses short channel effects. Fig. 2. Threshold voltage comparison with respect to BSH Fig. 4. IOFF variation with different BSH For VDS = 0.1V subthreshold slope (SS) value remains around 84mV/dec. For higher VDS, SS reduces with increase in BSH and decrease in work function difference. In fig. 5 due to high potential barrier provided by 50nm BSH it has lowest DIBL at 2.43mV/V. It is observed that as we increase ΔW, device performance degrades giving high DIBL. SS and DIBL degrades as ΔW increases while ION/IOFF ratio (fig. 6) increases so we choose optimum work function as ΔW=0.4. Fig. 3. ION comparison for different BSH Fig. 5. DIBL variation with different BSH IJIRT INTERNATIONAL JO URNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 250

4 Fig. 7 Transconductance generation factor (TGF) and transconductance (gm) variation with gate to source voltage (VGS) at VDS =1.0V and ΔW=0.4 Fig. 6. ION/IOFF ratio variation with different BSH Transconductance gm ( I_D/ V_GS) determines the gain of an amplifier which is high around 203.4µS for lower BSH as shown in fig. 7. TGF (transconductance generation factor) which is equal to gm/ ID show the available gain per unit value of power dissipation. Higher TGF values indicate strong capability to convert dc power into ac gain performance at a certain drain current bias. The ideal value of TGF is limited to 40 V-1 at minimum SS of 60 mv/decade of the device. Variation of TGF occurs in subthreshold region while it gets constant in strong inversion. BSH=50nm provides best TGF at 36.3 V-1 for both VDS variations. As seen from fig. 8 drain current is increasing with decrease in BSH which in turn makes output conductance (gd) high for these configurations. Fig. 9 shows that 50nm BSH has high early voltage and gain. Fig. 8 Output conductance (gd) and drain current (ID) variation with drain to source voltage (VDS) at VGS =1.0V and ΔW=0.4 Fig. 9 Early voltage (VEA) and intrinsic gain (AV) variation with gate to source voltage (VGS) at VDS =1.0V and ΔW=0.4 RF parameters below are calculated at VDS =0.1V. From fig. 10 we can infer that intrinsic gate capacitances Cgs and Cgd increase with the decrease in BSH or increase in active fin height. This is because of increase in the fringing field lines emanating from the gate edges for higher fin heights. Cut-off frequency (ft) in fig. 11 initially increases and reaches peak value owing to the minimum intrinsic capacitance and maximum gm. It falls with gate bias due to the combined effect of increase of intrinsic capacitances (Cgs and Cgd) and saturation of gm due to mobility reduction by the gate field. It increases with decrease in BSH height. IJIRT INTERNATIONAL JO URNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 251

5 Fig. 10. Gate to source capacitance (Cgs) and gate to drain capacitance (Cgd) variation with gate to source voltage (VGS) at VDS =0.1V and ΔW=0.4 Fig. 12.Gain frequency product (GFP) and transconductance frequency product (TFP) variation with gate to source voltage (VGS) at VDS =0.1V and ΔW=0.4 IV CONCLUSION In the present work, a systematic investigation of analog/rf performance of dual material ground plane bottom spacer FinFET is performed. The results show that use of dual material improves the ION/IOFF ratio because of step change in potential while the use of ground plane reduces the DIBL because of increase in potential barrier. From this paper we can conclude that for higher BSH, we obtain better electrical characteristics like IOFF, ION/IOFF current ratio and DIBL. When considering analog performance, higher BSH provides more intrinsic gain and early voltage. When considering RF performance, lower BSH proves better as it provides higher ft. Hence we choose an optimum value of BSH that suits both analog and RF circuit applications as 40nm. Fig. 11 Cut-off frequency (ft) and gain transconductance frequency product (GTFP) variation with gate to source voltage (VGS) at VDS =0.1V and ΔW=0.4 Tansconductance frequency product (TFP) represents a trade off between power and bandwidth and is utilized in moderate to high speed designs. From fig 12, for VDS =0.1V, BSH 30nm and 40nm show almost same TFP and gain frequency product (GFP) while 50nm shows lowest because of high gm and ft. REFERENCES [1] H.-S. P. Wong, K. K. Chan, and Y. Taur, Selfaligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel, IEDM Tech. Dig. 1997, pp [2] J.-H. Lee, G. Taraschi, A. Wei, T. A. Langdo, E. A. Fitzgerald, and D. A. Antoniadis, Super selfaligned double-gate (SSDG) MOSFETs IJIRT INTERNATIONAL JO URNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 252

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