A. Extraction of FPSC of PCC Voltages

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1 Discrete SOGI Bsed Control of Solr Photovoltic Integrted Unified Power Qulity Conditioner Schin Devssy, Student Memer, IEEE Electricl Engineering Dept. IIT Delhi New Delhi1116, Indi Bhim Singh, Fellow, IEEE Electricl Engineering Dept. IIT Delhi New Delhi1116, Indi Astrct A discrete second order generlized integrtor (DSOGI) sed control is presented in this work for control of solr photovoltic integrted unified power qulity conditioner (SPVUPQC). Two DSOGI sed ndpss filters re used to extrct fundmentl positive sequence component (FPSC) of unlnced grid voltges. The shunt compenstor of SPV UPQC is controlled sed on philosophy of drwing lnced positive sequence currents (BPSC) from the point of common coupling (PCC). The shunt compenstor hs the dul function of compensting for lod power qulity issues long with injecting power from solr photovoltic (SPV) rry. Sensitive lods re protected ginst grid voltge fluctutions such s voltge sgs/swells etc with the help of the series compenstor of SPV UPQC. A stepup DCDC converter is used for coupling SPV rry to the DCus of SPVUPQC. A Mximum power point trcking (MPPT) lgorithm genertes pproprite duty cycle for the dcdc converter so tht the SPV rry is operted t its pek power. The performnce of DSOGI sed SPV UPQC is simulted in MtlSimulink environment nd tested under dynmic conditions of grid voltge disturnces, lod disturnces nd solr irrdition vrition. Index Terms Power qulity, SPVUPQC, solr mppt, FPSC, DSOGI, series compenstion, shunt compenstion, stepup converter, ndpss filter. I. INTRODUCTION WITH dvnces in power electronics nd microelectronics technology, there is n incresed prolifertion of power electronics sed systems which re energy efficient. However, these power electronics systems re nonliner nd hence inject hrmonic currents into the grid. Aprt from hrmonics, vrious other lod side power qulities in distriution system include excessive neutrl current, lod unlncing, excessive rective power demnd [1]. In mny countries, the incresed instlltion of renewle energy systems (RES) hs strted ffecting the voltge qulity prticulrly in low voltge distriution systems []. The grid voltge fluctutions ffect sensitive industril lods leding to frequent tripping nd thus incresed economic losses. Voltge sgs re the most commonly encountered fluctution [3] which occur due to fults or due to hevy loding t the point of common coupling. A detiled discussion on vrious types of voltge sgs nd its cuses re descried in [3] /14/$31. c 16 IEEE Custom power devices re n ttrctive option for the mitigtion of power qulity issues. Custom power devices include distriution sttic compenstor (DSTATCOM) for shunt compenstion, dynmic voltge restorer (DVR) for series compenstion nd unified power qulity conditioner (UPQC) for oth shunt nd series compenstion [4]. Due to its shunt nd series compenstion cpility, UPQC provides complete solution to power qulity issues s compred to DSTATCOM nd DVR. In the recent yers there hs een n incresed focus on integrting RES/energy storge systems with custom power devices [5]. A study of use of custom power devices for integrting wind frms to grid ws reported in [6]. In [7], DVR with n energy storge system with fult current limiting functionlity hs een reported. Comining renewle energy systems with custom power devices gives dvntges of improving power qulity, providing clen energy nd lso incresed fult ride through cpility [8], [9]. A comprehensive review of vrious UPQC topologies nd control structures hve een discussed in [1]. Along with issues of nonliner currents, nother mjor prolem in distriution systems which re threephse fourwire (3P4W) systems is tht of lod neutrl current. Even under cse of lnced lods neutrl currents re present if the lods in ech phse re nonliner. For compenstion of neutrl current, the commonly topologies of shunt VSC include fourleg VSC or threeleg VSC with split cpcitor. Similrly, s most of the sgs encountered in distriution systems re unlnced, the required series compenstor [11] topology is lso four leg VSC with single cpcitor or threeleg VSC with split cpcitor. The control of fourleg VSC is simpler s compred threeleg VSC with split cpcitor which involves extr control loop of lncing the split cpcitors nd hence fourleg sed topology is preferred for the series nd shunt compenstor of UPQC. Digitl signl processing is n importnt function in the control of custom power devices (CPD). Most of the methods employed for control of CPD re time domin sed techniques s it involves simpl clcultions nd less memory requirements [1]. The commonly used methods include pq theory [1], d q theory[13] nd instntneous symmetricl component theory (ISC) [4]. In order to inject lnced positive sequence

2 currents into grid under conditions of symmetricl voltges or hrmonic distortion t PCC, the extrction fundmentl positive sequence component (FPSC) of PCC voltge ecomes vitl. In [14], the use of two SOGI sed ndpss filters hve een proposed for extrcting FPSC. In [15], cscded dely signl cncelltion (CDSC) sed technique for extrction of FPSC hs een proposed to e used s prefiltering scheme in threephse pll. Some other FPSC detection methods include using dptive notchfilter (ANF) [16], using complex vector filter method [17] etc. In this pper DSOGI sed control is proposed for the control of SPVUPQC. An implementtion of DSOGI sed ndpss filter is simple s it siclly consists of two integrtors, three gin locks nd two summers. Two DSOGI sed ndpss filters re used for extrction of FPSC components of PCC voltges sed on which the reference for shunt compenstor is generted. The resulting currents re lnced nd sinusoidl nd UPF with the FPSC of PCC voltges. The ojective of the series compenstor is to mintin the voltge of the lod terminls t desired mgnitude nd inphse with the FPSC of PCC voltges. A stepup DCDC converter is used for integrting the SPV rry t the DClink of SPV UPQC. For operting the SPV rry t its MPP, MPPT lgorithm [18] is used to generte pproprite duty rtio for the stepup converter. The SPVUPQC is tested in 3P4W system consisting of single phse nonliner lod in ech phse. The performnce of SPVUPQC is evluted under commonly encountered dynmic conditions of low voltge distriution system such s lod unlncing, irrdition level vrition nd symmetricl voltge sgs. II. CONFIGURATION OF SPVUPQC The configurtion of SPVUPQC for 3P4W system is presented in Fig.1. The mjor prts of the system re series compenstor nd shunt compenstor connected ck to ck with common DCus. As the shunt compenstor hs to compenste for unlnced lods nd the neutrl current in 3P4W system, fourleg shunt VSC is used for shunt compenstion. The series VSC used is four leg VSC which cn compenste for unlnced voltge sgs. The stepup converter is utilized for coupling the SPV rry to the DCus of SPVUPQC. The shunt nd series compenstors re interfced to the grid through interfcing inductors L f nd L r respectively. A series injection trnsformer is use to inject the voltges (e, e, ec ) generted y the series compenstor to protect sensitive lods ginst grid voltge sgs/swells. Ripple filters (R r C r, R fs, R fsh ) re used to ypss the hrmonics generted due to switching. III. CONTROL OF DSOGI BASED SPVUPQC The four mjor control locks of SPVUPQC re the discrete SOGI sed fundmentl positive sequence component (FPSC) extrctor for extrcting FPSC of PCC voltge, MPPT control lock for the stepup DCDC converter, shunt compenstor control lock nd series compenstor lock. These locks re discussed in detil s follows. vm vm vmc PV Arry ipv vpv vs is is vs vsc isc isn L Cpv Ripple Filter Rfs, Cfs Cr vse vse vsec Rr Ripple Filter Rfsh, Cfsh Cdc ish vdc ish Fig. 1. Configurtion of SPVUPQC A. Extrction of FPSC of PCC Voltges ishc vl il il ilc iln vl vlc ishn 3Phse 4wire Liner nd Nonliner Lod The extrction of FPSC components of PCC voltge is mjor tsk in control of SPVUPQC s the reference signl genertion of oth shunt compenstor nd series compenstor depends upon FPSC of PCC voltge. In this work, the FPSC re extrcted using discrete SOGI (DSOGI) ndpss filter. The structure of DSOGI ndpss filter is shown in Fig. (). As cn e seen from Fig. (), in the DSOGI ndpss filter there re two discrete integrtors, two summers nd three gin locks. The Trpezoidl version of integrtor is used in SOGI s it gives more ccurte results s compred to forwrd or ckwrd Euler discrete integrtion methods. The gins ω is set t nominl grid frequency. The gin lock K is djusted sed on compromise etween ccurcy nd speed of extrction of FPSC. For n input signl, the DSOGI ndpss filter gives the fundmentl frequency component1 nd fundmentl qudrture shifted component q1. In order to extrct FFPS components using DSOGI [14] ndpss filter, two DSOGI ndpss filters re used s shown in Fig.() The PCC voltges (,, ) re trnsformed into α β domin using Clrk s Trnsform. The α component v α nd β component v β re filtered using DSOGI ndpss filter to otin the fundmentl component (1α, 1β ) nd its qudrture shifted version (q1α, q1β ). The reltion etween the FPSC nd fundmentl frequency components is given s, 1α = 1 [ ] α q1β v s1β = 1 [ ] β q1α (1) ()

3 c K c αβ vs vs Discrete SOGIBPF Discrete SOGIBPF q1 w s w s () DSOGI ndpss filter q q 1 1 () DSOGI sed FPSC Extrctor KTs( z 1) ( z1) KTs( z 1) ( z1) Fig.. Structure of DSOGI nd DSOGI sed FPSC extrction c αβ 1 v s1 v s1 v The FPSC of PCC voltge in α β domin (v s1α, 1β ) re trnsformed ck using inverse Clrk trnsform to otin FPSC of PCC voltge in sttionry frme (v s1, 1, 1c ). B. Control of StepUp Converter A stepup converter is used for integrting the SPV rry to the DClink of SPVUPQC. The SPV rry is operted t its MPP y controlling the stepup converter using MPPT lgorithm. In this work, pertur & oserve (P&O) lgorithm is implemented for trcking MPP. The MPPT lgorithm directly genertes the duty rtio for the next switching period of the stepup converter. The duty rtio updting rule is given s, d n1 = d n δd.sgn(δ ) (3) where d n1 is duty cycle for next switching cycle, d n is duty cycle rtio of current switching period, δd is perturtion size of duty rtio, δ is difference in power clculted etween two cycles of MPPT lgorithm. C. Control of Shunt Compenstor of SPVUPQC The two mjor functions of the shunt compenstor is to mitigte the lod side power qulity prolems nd supply rel power otined from the SPV rry. The control methodology for the shunt compenstor control is such tht, the currents drwn from PCC re lnced positive sequence currents, oth under unlnced sgs of PCC voltges or unlnced condition of nonliner lods. The shunt compenstor control structure is shown in Fig.3. The verge lod rel power (P Lvg ) is extrcted y filtering the dot product of lod voltges nd currents. The filter used is moving verge filter (MAF), the window length of which, is fixed t hlf the grid fundmentl period s during unlnced condition the instntneous lod power hs doule I pv v Lc c MAF Dot Product () LPF MAF PI () P Lv P loss Gting Signls Hysteresis Current Controller v s1 v v s1 Fig. 3. Shunt Compenstor Control Structure c = c hrmonic ripple. The DCus of SPVUPQC is regulted t its desired reference vlue using digitl proportionl integrl (PI) controller. The reference for DCus PI controller is set t 7V. The sensed DCus voltge is filtered through MAF, the window length of which, is kept t hlf the grid period s DClink hs even hrmonics. The PI controller gives the power loss component of the SPVUPQC. The reference power to e drwn from the grid is then derived s, P = P Lvg P loss (4) where is the SPV rry power. The lnced positive sequence reference grid currents re otined s, i s1,c = 1,c 1α 1β 1 P (5) where P is verge power drwn from grid. The reference neutrl current (i s) is set s zero. The reference currents (i s, i s, i sc, i sn ) re compred with the sensed currents (,, c, ) in hysteresis controller to generte gting pulses corresponding to shunt VSC. D. Control of Series Compenstor of SPVUPQC The purpose of the series compenstor is the protection of sensitive lod ginst disturnces in PCC voltges. The series compenstor injects voltge inphse with the FPSC of the PCC voltges. The series compenstor control lock digrm is presented in Fig. 4. The mplitude of FPSC of PCC voltges is clculted s, V s = v s1α 1β (6) The unit templtes of FPSC of PCC voltges re otined s, u s1,c = 1,c V s The lod reference voltges (vlc ) re otined y multiplying the pek reference voltge (VL ) with the unit templtes (u s1,c ). The reference for the fourth leg of series VSC (v Lu ) (7)

4 (kw) i SHn i SH n v L V L v s1 v s1 v Amplitude Clcultion u s1 u s1 u Lu v L v L v = v Lc Gting Signls Voltge Hysteresis Control Fig. 4. Series Compenstor Control Structure 1 vlu v L v L v Lc is set s zero. The reference voltges (v L, v L, v Lc, v Lu ) re compred with the sensed voltges (v L, v L, v Lc, v Lu ) in voltge hysteresis controller, which genertes the series compenstor gting pulses. IV. PERFORMANCE EVALUATION The DSOGI sed SPVUPQC is simulted in Mtl/Simulink softwre using SimPowerSystems lockset. The dynmic performnce is evluted t different scenrios such s unlnced sg of PCC voltges, irrdition vrition nd lod disturnces. The lod used consists three single phse currentfed nonliner lods ech connected etween phse nd neutrl of the system. The detiled design vlues of the SPVUPQC re given the Appendix. A. SPVUPQC performnce during Lod Disturnces The dynmic ehvior of SPVUPQC under lod disturnce is presented Fig.5. The irrdition(g) of SPV rry is kept t 1W/m. The signls shown re PCC voltges( ), lod voltges (v L ), DCus voltge ( ), grid currents ( ), grid neutrl current ( ), lod current ( ), lod neutrl current (n ) shunt compenstor current (i SH ), shunt compenstor neutrl current (i SHn ),SPV rry power ( ), SPV rry voltge ( ). It is to e noted tht the PCC nd lod voltges shown re phse to neutrl voltge. As oserved from Fig.5, the shunt compenstor keeps the PCC neutrl current ( ) t nerly zero y compensting for lod neutrl current. It cn lso e oserved tht the though the lod is nonliner, the grid current is sinusoidl t unity power fctor. From t=.6s to t=.7s phse is opened through circuit reker. It is oserved tht the grid currents re still sinusoidl nd lnced. The DCus voltge settles within 4% reference vlue of 7V within.6s fter slight overshoot/undershoot during opening nd closing of circuit reker. B. SPVUPQC performnce during Irrdition chnge The dynmic performnce of DSOGI sed SPVUPQC is evluted y giving rmp decrese in solr irrdition. The relevnt signls re shown in Fig.6. The signls shown re threephse PCC voltges ( ), lod voltges (v L ), DCus voltge ( ), grid currents ( ), grid neutrl current ( ), lod current of phse ( ), lod neutrl current (n ), shunt compenstor current of phse (i SH ), shunt compenstor Fig. 5. Performnce of SPVUPQC under Lod Disturnces neutrl current(i SHn ), SPV rry Power ( ), SPV voltge ( ), nd irrdition (G(W/m )). As the lod is symmetricl, the shunt compenstor currents re symmetricl nd hence only phse current is shown in cse of lod currents nd shunt compenstor currents. From.6s to.65s, the solr irrdition(g) is uniformly vried from 1W/m to W/m. As oserved from Fig.6, s the power from the SPV rry reduces, the rel power demnd of the lod side is supplied y the PCC. The DClink is regulted t its desired vlue. C. SPVUPQC during Asymmetricl Sg in PCC Voltges Fig.7 presents the SPVUPQC performnce under symmetricl sg in PCC voltges. The SPV rry is t STC conditions of 1W/m nd 5 C. Signls shown re grid voltges ( ), lod voltges (v L ), series compenstor voltges (v SE ), DCus voltge ( ), grid currents ( ), grid neutrl currents

5 G(w/m ) (kw) (kw) I SHn i SHn i SH i SH n n e v L v L Fig. 6. SPVUPQC performnce under vrying irrdition condition Fig. 7. SPVUPQC performnce during symmetricl sgs in PCC voltge ( ), phse lod current ( ), lod neutrl current (n ), phse shunt compenstor current (i SH ), shunt compenstor neutrl current (i SHn ), SPV rry power ( ), SPV rry voltge ( ). As the lod is symmetricl ut nonliner, the shunt compenstor signls re lso symmetricl nd nonliner; hence, only phse current is shown in cse of lod nd shunt compenstor signls for good clrity in representtion. As cn e seen from Fig. 7, from t=.6s to t=.7s there is n unsymmetricl sg of.3pu in phse nd c long with phse jump. It cn e noted tht the lod voltge is sinusoidl nd t its reference vlue despite the distortions in the grid voltge. Under nominl conditions the series compenstor does not inject voltge. The grid current rises during sg to mintin rel power lnce. The hrmonic spectr of grid currents nd lod currents re given in Fig.8. The DSOGI sed SPVUPQC compenstes for the hrmonics of lod current. It cn e noted tht though the totl hrmonic distortion (THD) of the nonliner lod current is 36.44%, the THD of the grid current is.17% nd is thus within limits prescried in IEEE519 stndrd [19]. V. CONCLUSION A DSOGI sed SPVUPQC nd its dynmic performnce hs een presented in this work. Two DSOGI ndpss filters hve een used to extrct FPSC of PCC voltges. The extrcted FPSC hs een used for reference signl genertion in cse of shunt nd series compenstor. The SPVUPQC performs stisfctorily under conditions of lod unlnce, symmetricl sgs nd solr irrdition vrition. The grid currents re lnced nd sinusoidl even under conditions of nonliner nd unlnced lod. The lod voltges re lso lnced nd sinusoidl under conditions of symmetricl sgs. The integrtion of SPV rry with SPVUPQC enhnces the functionlity of the UPQC. SPVUPQC integrtes the concept of clen energy long with power qulity improvement.

6 Mg. (% of Fundmentl) Mg. (% of Fundmentl) Fundmentl (5Hz) = 55.93A THD =.17% Frequency(Hz) () Hrmonic Spectr of Grid Current Fundmentl (5Hz) = 85.6A THD = 36.44% Frequency(Hz) () Hrmonic Spectr of Lod Current Fig. 8. Hrmonic Spectr of Grid nd Lod currents ACKNOWLEDGMENT This work is sponsored y Deprtment of Science nd Technology, Govt. of Indi, under Grnt Numer: RP583. APPENDIX Detiled Design Vlues: Per phse grid voltge: 39.6V, 5Hz; Grid Impednce:.1mH,.Ω; Reference DCus Voltge: 7V; DCus Cpcitor: 1mF; Nonliner Lod in ech phse: Bridge Rectifier with RL: 3Ω, 1mH; Shunt Compenstor Interfcing Inductor:1mH; Shunt compenstor neutrl leg Inductor:.8mH; Averge switching frequency of shunt nd series VSC: 1kHz; Ripple Filter of Shunt VSC:1µF, 1Ω; Ripple Filter Series VSC:5µF,5Ω; Ripple Filter t PCC:1µF, 1Ω; Interfcing Inductor of Series Compenstor: 4mH; Injection Trnsformer: 1kVA, 415V/138V; VA Rting of Shunt Compenstor=38kVA, Rting of Series Compenstor=1kVA; Gins of DCus PI contoller: K p =,K i =3; MAF Prmeters for DC us filtering:n=1,t w =.1,T s =1e4; MAF Prmeters for Lod Power Clcultion:N=1,T w =.1,T s =1e4; DSOGI Prmters: T s =5e5,K=.8; DC Inductor: L=.5mH; Input Cpcitor of StepUp Converter:1µF; SPV rry dt: P =13.8kW, V oc =73V, I sc 5.8=A, V mpp =568V, I mpp =4.1A. REFERENCES [1] B. Singh, A. Chndr, K. A. Hddd, Power Qulity: Prolems nd Mitigtion Techniques. London: Wiley, 15. [] H. Hfezi, G. D Anton, R. Frnd, D. D. Giustin, A. Dede, nd G. Mss, Power qulity conditioning in lv distriution networks: Results y field demonstrtion, IEEE Trnsctions on Smrt Grid, vol. PP, no. 99, pp. 1 1, 16. [3] M. Bollen, Understnding Power Qulity prolems: Voltge Sgs nd interruptions. New York: IEEE Press,. [4] A.Ghosh nd G. Ledwich, Power Qulity Enhncement using Custom Power devices. London: Kluwer Acdemic Pulishers,. [5] C. Jin nd B. Singh, A singlephse twostge grid interfced spv system with djustle dc link voltge for vsc under non idel grid conditions, in IEEE Interntionl Conference on Power Electronics, Drives nd Energy Systems (PEDES), Dec 14, pp [6] M. F. Fris, M. G. Cendoy, nd P. E. Bttiotto, Wind frms in wek grids enhncement of ridethrough cpility using custom power systems, in IEEE/PES Trnsmission nd Distriution Conference nd Exposition, Aug 8, pp [7] S. S. Choi, T. X. Wng, nd D. M. Vilthgmuw, A series compenstor with fult current limiting function, IEEE Trns. Power Del., vol., no. 3, pp , July 5. [8] S. Devssy nd B. Singh, Dynmic performnce of solr PV integrted UPQCP for criticl lods, in Annul IEEE Indi Conference (INDI CON), Dec 15, pp [9] S. Devssy nd B. Singh, Enhncement of power qulity using solr pv integrted upqc, in 39th Ntionl Systems Conference (NSC), Dec 15, pp [1] V. Khdkikr, Enhncing electric power qulity using UPQC: A comprehensive overview, IEEE Trns. Power Electron., vol. 7, no. 5, pp , My 1. [11] K. M. Prveen, K. M. Mhesh, nd J. Sndeep, Switching minimiztion of threephse fourleg dynmic voltge restorer, in Annul IEEE Indi Conference, Dec 9, pp [1] H. Akgi, E. Wtne, M. Aredes, Instntneous Power Theory nd Applictions to Power Conditioning. New Jersey: Wiley, 7. [13] P. Knjiy, B. Singh, A. Chndr, nd K. AlHddd, SRF Theory Revisited to control selfsupported dynmic voltge restorer (dvr) for unlnced nd nonliner lods, IEEE Trns. Ind. Appl., vol. 49, no. 5, pp , Sept 13. [14] P. Rodriguez, R. Teodorescu, I. Cndel, A. V. Timus, M. Liserre, nd F. Bljerg, New positivesequence voltge detector for grid synchroniztion of power converters under fulty grid conditions, in Power Electronics Specilists Conference, 6. PESC 6. 37th IEEE, June 6, pp [15] Y. F. Wng nd Y. W. Li, Threephse cscded delyed signl cncelltion pll for fst selective hrmonic detection, IEEE Trns. Ind. Electron., vol. 6, no. 4, pp , April 13. [16] M. Mojiri, M. KrimiGhrtemni, nd A. Bkhshi, Processing of hrmonics nd interhrmonics using n dptive notch filter, IEEE Trns. Power Del., vol. 5, no., pp , April 1. [17] W. Li, X. Run, C. Bo, D. Pn, nd X. Wng, Grid synchroniztion systems of threephse gridconnected power converters: A complexvectorfilter perspective, IEEE Trns. Ind. Electron., vol. 61, no. 4, pp , April 14. [18] B. Suudhi nd R. Prdhn, A comprtive study on mximum power point trcking techniques for photovoltic power systems, IEEE Trnsctions on Sustinle Energy, vol. 4, no. 1, pp , Jn 13. [19] IEEE recommended prctices nd requirements for hrmonic control in electricl power systems, IEEE Std , pp. 1 11, April 199.