UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

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1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Jan Rabaey EECS 141 Spring 2010 LDPC Decoder Project Phase 3 Due Noon, Wednesday, May 5th, 2010 Introduction The principal goal of project phase 3 is to analyze the energy-delay trade-off and optimize a full LDPC decoder for three different design targets on the energy-delay curve as shown in the Fig.1. Fig.1 Energy-Delay Curve In the previous two phases, you have learned how to implement check node and bit node for a LDPC decoder. As with these previous phases, the primary constraint on your design is making the circuit function correctly and minimizing the delay of the critical path. In the final phase of the project, you will learn how to optimize the circuits for different design metrics. Below are four different LDPC codes. Ignoring the edge effects, each group has to design for a 256 bitnode LDPC code. The template for the code is shown in Fig.2. Fig.2 Code Structure Template EECS141: SPRING 10 PROJECT Phase 3 1

2 Code A: Fig.3 Code A The idea here is that the structure is the same as that in the template. However, there are two alternating sequences of blocks. The two sequences are not interconnected, but they contribute to increased wirelength. Code B: Similar to the problem of Code A, this group has to design for four such sequences of alternating blocks (obviously, no permutations of blocks are allowed! However, you do have some freedom in the floor plan design that is detailed later). Code C: Similar to the problems of Codes A and B, this group has to design for eight such sequences (and same design restrictions as those for Code B). Code D: Similar to the problems of Codes A, B, C, this group has to design for sixteen such sequences (and same design restrictions as those for Code B). Each group has to choose one code structure from Code A, B, C or D, and design for a 256 bit-node LDPC code. Floorplan of LDPC Decoder and Wire Loading Estimation As the code length of a LDPC decoder increases, floorplan and wire routing strategy will highly impact wire loading and total energy consumption of the decoder. Instead of using the real dimension of your check node and bit node layout from phase 2, we assume the dimension of check node and bit node layout is 20 um x 20 um. Two examples of the possible floorplans are shown in Fig.4. In example #1, check nodes, bit nodes and wire routing area are arranged in single-row style. This may not be the optimal solution for a given LDPC code structure and code length. In example #2, we divide the bit nodes into two rows so that the worst case wire length may be reduced by half in this floorplan. Be creative in your own floorplan and wire routing so that you can minimize the wire loading and make wire routing efficiently. EECS141: SPRING 10 PROJECT Phase 3 2

3 Example #1 Example #2 Fig.4 Floorplan Examples In phase 3, you don t need to do the tedious layout work and wire parasitic extraction of the LDPC decoder. (After the layout work of phase 2, you must know it is really time-consuming to layout all the wires by hand.) Instead, the wire loading will be estimated by a simple model in hand calculation. Here are the assumptions: Only Metal 3 (vertical) and Metal 4 (horizontal) are allowed for wire routing between check nodes and bit nodes. The wire routing is Manhattan style as shown in Fig.5. The width of M3 and M4 wires is 0.14um. The spacing of the M4 wires is kept as the minimum without violating design rules. The horizontal direction of routing area is densely filled by M4 wires. There is a M2 meshed plane under routing area for shielding purpose. You can assume that the meshed M2 lines are just big metal plane. EECS141: SPRING 10 PROJECT Phase 3 3

4 M3 M4 Fig.5 Example of Wire Routing The wire loading includes parallel plate, fringe and coupling capacitances(interlayer capacitance) as shown in Fig.6. That is Cw = C p-p + 2C fringe + 2C coupling. The capacitance table and resistance table are given on the project webpage. Ccoupling Ccoupling M3 or M4 Cp-p+2Cfringe M2 (Shielding Layer) Fig.6 Wire Capacitances Based on the given code structure and wire model, you can follow the steps to estimate the worst case wire loading. Step 1: Find the optimal floorplan of your code structure. Be creative in this step!! Step 2: Figure out the width and height of your routing area. The width and height of the routing area will determine the worst case wire loading. (Note: Height is determined by the minimum distance that can pass the worst case number of wires on the vertical cross section of the routing area. Width is usually determined by the width of your floorplan for accommodating check nodes or bit nodes.) Step 3: Find the worst case connection of bit nodes and check nodes. Calculate the value of the worst case wire loading. It may not be easy to figure out the optimal solution for floorplan and wire routing in just one shot. You may need to iterate in these steps. EECS141: SPRING 10 PROJECT Phase 3 4

5 Design Optimization Part 1: Design for the minimum energy consumption for a given delay We would like to design the LDPC decoder for a given clock cycle, 10ns. The goal is to achieve the lowest energy consumption under the timing constraints. The result can be shown as a design point on the energy-delay curve in Fig.7. For this part, you can either use your circuits from phase 1 and phase 2 or re-design the circuits to achieve the lowest energy consumption. You also can change the supply voltage to further reduce the energy consumption. You should use the method from phase 2 for simulating delay and energy consumption. Fig.7 Energy-Delay Curve Part 2: Find (T d,min, E max ) and (T d,max, E min ) by varying the supply voltage of the circuit Now, we want to see two extreme design points on the energy-delay curve for your circuits in part 1. By varying the supply voltage, you can find these two points on the energy-delay curve as shown in Fig.8. First, by increasing the supply voltages, you can reduce the delay but increase the energy consumption. You can find the first extreme point (T d,min, E max ) on the energy-delay curve. Second, you can lower the supply voltage to find the minimum energy consumption. The result is the other extreme point (T d,max, E min ) on the energy-delay curve. Note that the lowest supply voltage is the voltage under which your circuits still function properly without any failure. Fig.8 Energy-Delay Curve with Two Extreme Design Points EECS141: SPRING 10 PROJECT Phase 3 5

6 After finding the total energy consumption in part 1 and part 2, please find the ratio of energy consumed by computation and energy consumed by interconnection. Objective Objective of phase 3 of the project is to analyze the energy-delay tradeoffs and optimize a full LDPC decoder for three different design targets on the energy-delay curve. Floorplan and wire loading plays an important role in the design and optimization process. After finding your optimal solution of flooplan, the design is started from optimizing the total energy consumption for a give delay. Then you find two extreme design points by varying the supply voltage in the same circuit. The results you get from the above processes are the three important points on the energy-delay curve. No layout work is required in Phase 3. Design Constraints Technology: GPDK 90nm in the EE141 Lab Library; Supply Voltage: 1.2V; Input Capacitance: (1) The input capacitance of the check node is 4C (2) The input capacitance of the bit node is 4C. (3) The input capacitances of the CLK and SEL signals are 4C. C is the gate capacitance of a unit-size inverter (NMOS: 120nm/100nm, PMOS: 240nm/100nm); Wire Capacitance: The wire capacitance table can be found on the project webpage. and Dimensions: x Metal Layers: M3 and M4 for long wires Minimum cycle: Clock signal in the simulation has rise and fall times of 100 ps. Poster Instead of a text report, results of this phase of the project will be presented in a poster session at 1:00~5:00 pm on Wednesday May 5 th, Each team will be given 10 minutes to present thee design, followed by 3 minutes Q&A. Time slot sign-up sheet will be passed around during the lecture on April 28. Make sure at least one of the team members will be present. The poster session will be held at BWRC (Berkeley Wireless Research Center, directions: Poster template as well as mounting instructions can be found on the course website. Also remember to your poster to ee141@cory.eecs.berkeley.edu by noon, Wednesday, May 5 th, Have fun, and good luck! EECS141: SPRING 10 PROJECT Phase 3 6