EDA for IC Implementation, Circuit Design, and Process Technology

Transcription

1 EDA for IC Implementation, Circuit Design, and Process Technology Edited by Louis Scheffer Cadence Design Systems San Jose, California, U.S.A. Luciano Lavagno Cadence Berkeley Laboratories Berkeley, California, U.S.A. Grant Martin Tensilica Inc. Santa Clara, California, U.S.A. QfP) Taylor &. Francis >V J Taylor & Francis Group Boca Raton London New York A CRC title, part of the Taylor & Francis imprint, a member of the Taylor & Francis Group, the academic division of T&F Informa plc.

2 Contents SECTION I RTL to GDS-II, or Synthesis, Place, and Route 1 Design Flows Leon Stok, David Hathaway, Kurt Keutzer, and David Chinnery Introduction Invention Implementation Integration Future Scaling Challenges Condusion Logic Synthesis Sunil P. Khatri and Narendra V. Shenoy Introduction Behavioral and Register Transfer-Level Synthesis Two-Level Minimization Multilevel Logic Minimization Enabling Technologies for Logic Synthesis Sequential Optimization Physical Synthesis Multivalued Logic Synthesis Summary Power Analysis and Optimization from Circuit to Register-Transfer Levels Jose Monteiro, Rakesh Patel, and Vivek Tiwari Introduction Power Analysis Circuit-Level Power Optimization Logic Synthesis for Low Power Conclusion 3-15

3 4 Equivalence Checking Andreas Kuehlmann and Fabio Somenzi Introduction 4_1 4.2 Equivalence Checking Problem Boolean Reasoning Combinational Equivalence Checking Sequential Equivalence Checking 4_ Summary 4_17 5 Digital Layout Placement Andrew B. Kahng and SheriefReda Introduction: Placement Problem and Contexts Global Placement 5,4 5.3 Detailed Placement and Legalizers 5_ Placement Trends _ 5.I7 5.5 Academic and Industrial Placers Conclusions 5_20 6 Static Timing Analysis Sachin S. Sapatnekar Introduction g_l 6.2 Representation of Combinational and Sequential Circuits Gate Delay Models Timing Analysis for Combinational Circuits Timing Analysis for Sequential Circuits Clocking Disciplines: Edge-Triggered Circuits Clocking and Clock-Skew Optimization Statistical Static Timing Analysis Conclusion Structured Digital Design Fan Mo and Robert K. Brayton Introduction 7_1 7.2 Datapaths 7_2 7.3 Programmable Logic Arrays Memory and Register Files 7_ Structured Chip Design Summary 7_2i 8 Routing Louis Scheffer Introduction Types of Routers 8_2 8.3 A Brief History of Routing Common Routing Algorithms Additional Router Considerations Exploring Challenges of Libraries for Electronic Design James Hogan and Scott T. Becker Introduction What Does It Mean to Design Libraries? 9-1

4 9.3 How Did We Get Here, Anyway? Commercial Efforts What Makes the Effort Easier? The Enemies of Progress Environments That Drive Progress Libraries and What They Contain Summary Design Closure Peter J. Osler and John M. Cohn Introduction Current Practice The Future of Design Closure Conclusion Tools for Chip-Package Codesign Paul D. Franzon Introduction Drivers for Chip-Package Codesign Digital System Codesign Issues Mixed-Signal Codesign Issues I/O Buffer Interface Standard and Other Macromodels Conclusions Design Databases Mark Bales Introduction History Modern Database Examples Fundamental Features Advanced Features Technology Data Library Data and Structures: Design-Data Management Interoperability Models FPGA Synthesis and Physical Design Mike Hutton and Vaughn Betz Introduction System-Level Tools Logic Synthesis Physical Design Looking Forward SECTION II Analog and Mixed-Signal Design 14 Simulation of Analog and RF Circuits and Systems Jaijeet Roychowdhury and Alan Mantooth Introduction Differential-Algebraic Equations for Circuits via Modified Nodal Analysis 14-2

5 14.3 Device Models Basic Circuit Simulation: DC Analysis Steady-State Analysis Multitime Analysis Noise in RF Design Conclusions Simulation and Modeling for Analog and Mixed-Signal Integrated Circuits Georges G.E. Gielen and Joel R. Phillips Introduction Top-Down Mixed-Signal Design Methodology Mixed-Signal and Behavioral Simulation Analog Behavioral and Power Model Generation Techniques Symbolic Analysis of Analog Circuits Conclusions Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip: A Survey Rob A. Rutenbar and John M. Cohn Introduction Analog Layout Problems and Approaches Analog Cell Layout Strategies Mixed-Signal System Layout Field-Programmable Analog Arrays Conclusions SECTION III Physical Verification 17 Design Rule Checking Robert Todd, Laurenze Grodd, and Katherine Fetty Introduction Geometrie Algorithms for Physical Verification Hierarchical Data Structures Time Complexity of Hierarchical Analysis Connectivity Models Parallel Computing Future Roles for Verification Resolution Enhancement Techniques and Mask Data Preparation Franklin M. Schellenberg Introduction Lithographie Effects RET for Smaller Jfcj Software Implementations of RET Solutions Mask Data Preparation Summary Design for Manufacturability in the Nanometer Era Nicola Dragone, Carlo Guardiani, andandrzejj. Strojwas Introduction Taxonomy of Yield Loss Mechanisms 19-3

6 19.3 Logic Design for Manufacturing Parametric Design for Manufacturing Methodologies Design for Manufacturing Integration in the Design Flow: Yield-Aware Physical Synthesis Summary Design and Analysis of Power Supply Networks David Blaauw, Sanjay Pant, Rajat Chaudhry, and Rajendran Panda Introduction Voltage-Drop Analysis Modes Linear System Solution Techniques Models for Power Distribution Networks Conclusions Noise Considerations in Digital ICs Vinod Kariat Introduction Why Has Noise Become a Problem for Digital Chips? Noise Effects in Digital Designs Static Noise Analysis Electrical Analysis Fixing Noise Problems Summary and Conclusions Layout Extraction William Kao, Chi-Yuan Lo, Mark Basel, Raminderpal Singh, Peter Spink, and Louis Scheffer Introduction Early History Problem Analysis System Capabilities Converting Drawn Geometries to Actual Geometries Designed Device Extraction Connectivity Extraction Parasitic Resistance Extraction Capacitance Extraction Techniques Inductance Extraction Techniques Network Reduction Process Variation Conclusions and Future Study Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and Validation Nishath Verghese and Makoto Nagata Introduction Mechanisms and Effects of Mixed-Signal Noise Coupling Modeling of Mixed-Signal Noise Coupling Mixed-Signal Noise Measurement and Validation Application to Placement and Power Distribution Synthesis Summary 23-21

7 SECTION IV Technology CAD 24 Process Simulation Mark D. Johnson Introduction Process Simulation Methods Ion Implantation Diffusion Oxidation Etch and Deposition Lithography and Photoresist Modeling Silicidation Mechanics Modeling Putting It All Together Conclusions Device Modeling From Physics to Electrical Parameter Extraction Robert W. Button, Chang-Hoon Choi, and Edwin C. Kan Introduction MOS Technology and Intrinsic Device Modeling Parasitic Junction and Inhomogeneous Substrate Effects Device Technology Alternatives Conclusions High-Accuracy Parasitic Extraction Mattan Kamon and Ralph Iverson Introduction 26-2 Part I: Extraction via Fast Integral Equation Methods Introduction Forms of MaxwelPs Equations Fast Field Solvers: Capacitance Solution Fast Inductance Solution Distributed RLC and Füll Wave Conclusions Part II: Statistical Capacitance Extraction Introduction Theory Characteristics Summary index Index-1