Roadmap Semiconductor Equipment Innovation Agenda

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1 Roadmap Semiconductor Equipment Innovation Agenda Societal and economic relevance Over the years, electronics have become an inseparable part of our lives. Think of the internet, the cloud, electronic banking, communication and navigation but also surveillance and health applications. Moreover, today s trends; the closure of the gap between smart phones and personal computing, the onset in automotive of autonomous driving cars, 5G, augmented & virtual reality, artificial intelligence and connecting all devices, the Internet of Things ( IoT ) 1 will increase the need for electronics even further. It is estimated that the internet of things will connect 50 billion devices by 2020, each device containing at least one chip which promises to drive the amount of unstructured data by orders of magnitude, requiring significant computing power to translate it into end user value. Hence, still exponential curves ahead; while at the same time efforts will be needed to keep the power consumption of the devices much lower. The aforementioned rapid advancement of microchips is described by Moore s Law (1965). Intel s cofounder Gordon Moore recognized that technology progress allows us to double the number of components on a chip every months. Advancements on three fronts have enabled this: miniaturization of components (geometric scaling), device innovations and material innovations. The roadmap for R&D in Semiconductor Equipment is dominated by the same three driving forces providing sequential steps in technology advancements called nodes. The IRDS (International Roadmap for Design and System) group, previously called ITRS, published a white paper on the road map for technology 2. The continuation of Moore s Law (which is essentially a cost roadmap) will result in increasingly powerful and capable electronics, allowing faster processing of data enabling the world to progress within a multitude of fields, such as healthcare, communication, energy, mobility and entertainment. Combining and processing vast amounts of data from a variety of sources will provide opportunities for holistic solutions to tackle grand societal challenges in addressing themes such as: Automotive & Transportation Connectivity & Digital Networks Energy Efficiency Health & Aging Society Sustainable Food & Water Supply Safety & Security Looking farther ahead, the semiconductor market is expected to grow from $343B in 2016 to $415B in 2021 (Ref. Gartner Q1, 2017 update). This drives the global Semiconductor Equipment market (SCE) to be in the order of 43B$ (2016 Forecast, source: VLSI May 2017) composed of 36B$ wafer front-end, 3B$ test and 4B$ assembly equipment. About one fifth is delivered from the Netherlands. 1 AENEAS Strategic Research Agenda: 2 See IRDS (International Roadmap for Design and System) white paper: 1 of 6

2 Consequently virtually all State-of-the-Art chips in the world contain Dutch IP and are manufactured on and/or measured with equipment from the Netherlands. In the past the market has been extremely volatile with year on year variations as large as 30%. More recent data shows that industry and market have become more stable. Driven by today s trends, Moore s law will from a technical viewpoint continue well into the next decade. The total R&D investment in this sector in the Netherlands by the industry is less cyclic and estimated over 1B, more than one sixth of the Dutch private R&D 3. As a result, in certain areas the Dutch industry is dominant, like in lithography, where ASML has a market share in excess of 80%, in some areas significant, especially at the high-end side (high resolution imaging, atomic layer depositions, assembly & packaging, etc.). The increased business demand driving Moore s law will provide growth to the total semiconductor equipment market of at least 25% ( B$). The litho content now estimated to be over 8B$ (VLSI, May 2017) is likely to exceed this growth as it will mainly be driven by new technology nodes. 2. Application and technology challenges The strength of the Dutch national semiconductor equipment ecosystem finds its roots in the above mentioned consistency in R&D investments in the areas of Lithography, metrology, Imaging, deposition and assembly technologies. Moreover, this ecosystem taps into a strong knowledge base in Research Institutes, Academia and Industry together with a world class, interconnected supply chain. The knowledge base includes scientific fields such as light-, electron- and EUV-optics, plasma physics, surface physics and chemistry, heat- and fluid-transport, precision mechanics, mechatronics, System Architecture & Design, electronics, vision, applied mathematics, materials science, vacuum technology, contamination control, embedded system technology, thin film technology, Advanced Data Science, etc. This knowledge is applied in the Dutch SCE industry providing exceptional strengths in the following areas: Lithography systems, in particular (D)UV (Deep Ultra Violet) and EUV (Extreme Ultra Violet) technology, including tools, optics, and radiation sources, as well as NGL (next-generation lithography) technologies including E-Beam and mask-less lithography, (e.g. for unique chip manufacturing at low volume production) and advanced (often complementary) patterning strategies such as DSA (Direct Self Assembly) and Nano-Imprint. And application of e-beam inspection technology to enhance & expand lithography solution. Novel materials for new nano-structuring technologies, such as substrate materials, resists, chemical gases and pre-cursers etc. for next applications. Process equipment for thin-film manufacturing, including deposition, diffusion, anneal and removal techniques, and the corresponding manufacturing infrastructure. Preassembly technologies and Wafer preparation: equipment and processes for wafer cutting, slicing, etching, polishing, cleaning, epitaxial deposition, thinning, and laser marking. 3 See TW.nl article on R&D 2017: 30/item of 6

3 nanometer-scale characterization techniques (imaging and analysis) for materials, device and process testing, using scanning probe, electron beam and Xray methods to measure geometrical, elemental, thermal, electrical, topographic and chemical properties (mostly multi-dimensional and multi-domain). Wafer processing related Advanced Process Control systems for Multi-Dimensional Metrology (MDM) challenges of latest transistor and the application in large area, high volume/throughput processing and (in-line) metrology. (e.g. gate-all-around (GAA) and Fin- FET) and connectivity (e.g. through silicon via (TSV)) architectures. In particular advanced inline metrology, such as Thin-Film metrology by Optical and X-Ray techniques, Critical Dimension by E-Beam and Scatterometry (multi-dimensional or beyond 3D) techniques, and Overlay by Optical, Scatterometry and E-Beam techniques. Equipment and materials for Quantum Computing device development & manufacturing. Implementing existing and new technologies in adjacent markets such as integrated photonics by collaboration of SME s active in the semiconductor equipment market, e.g. by sharing the system architecture role (architecture community); increasing the speed in developing system architecture roles also in SME s. 2.1 State of the art in industry and science The forefront of semiconductor manufacturing, regarding lithography, is Logic and High Performance Memory which are used mainly in portable devices. Currently, double patterning immersion lithography is used at line widths of less than 20nm. The reduction of line widths is a major drive in the industry, since it reduces production cost, improves performance and the quality of the manufactured products. Continuous increase of the device density (number of devices per unit of area) is the first business principle that makes commercial success in the semiconductor industry. Enabled by current Deposition, Litho, Etch, Processing and Metrology tools and their performance, the 10nm technology node is about to be ramped-up by market leaders and solutions for 7nm and beyond are being explored. Productivity improvement is a constant drive in the industry. To reduce cost, the number of wafers that are processed per hour is constantly pushed upwards. This can be achieved by either throughput improvements of semiconductor manufacturing equipment or process simplifications, such as moving from double patterning in DUV to single patterning in EUV. Current state of the art throughput levels in DUV litho is 275 wafers per hour and 125 wafers per hour in EUV litho. 2.2 Future outlook, in present and emerging markets In the next five years the semiconductor market is likely to continue growing with a CAGR of 5% (ref. Gartner May 2017 update). The complexity will keep increasing with a rapid pace. The number of process steps and use of diverse materials will increase and can be seen as more Moore. This is all good news for the equipment industry. 3 of 6

4 At the same time there will be new markets which will be served by heterogeneous solutions in which different technology will be combined through assembly technologies showing a high level of More than Moore. For example the coupling of a photonics interface to an integrated circuit application. Some more specific developments can be expected over the next years: Development of new transistor and device architectures, such as (strained) Gate All Around (horizontal or vertical) transistor channels which pose challenges for processing, litho and multi-dimensional metrology Need for closer loops and tool-connectivity between litho, process and metrology to enhance the productivity of the FABs Industry 4.0: introduction of Big Data sciences (including machine learning and deep-learning methods) in the FAB, which will have an impact on the equipment as well. Emphasis on tool availability and predictability for the FABs. 2.3 Major industry challenges Given the above solid industrial base, the Dutch semiconductor equipment sector is well equipped to tackle the following challenges in alignment with the European strategic research agenda: Develop Dutch know-how for advanced semiconductor Equipment for sub-10nm technology for advanced and distributed computing infrastructure to enable performance and cost scaling according to Moore s law. Strengthen Dutch competitiveness by developing advanced semiconductor equipment solutions; heterogeneous integration and More than Moore. 3. Priorities and implementation The goal of the programs in this roadmap is to further strengthen the semiconductor equipment Ecosystem. In the Netherlands the semiconductor equipment ecosystem is built on excellent knowledge institutes, strong 1 st TIER suppliers providing integrated technology solutions and Dutch OEM s. Several young SME s provide innovative and disruptive solutions. Several large OEM s play an international leading role in their field and provide international market access to customers often located in Asia or the US. All of this is supported by knowledge institutes and academia providing the fundamental knowledge required. 4 of 6

5 For the implementation of public private partnerships it recommended to drive for a good mix of companies and knowledge institutes in the projects. This should stimulate the R&D across the entire semiconductor equipment supply chain including SME s. Projects can be prioritized based on their respective contribution to the grand societal challenges, and/or on their relevance as (key) enabling technologies for the Netherlands. Implementation can be through TKI, national or international programs. 3.1 TKI Program The best possible institute should in principle be charged with executing work under the TKI program, not necessarily the institute that provides the base for the TKI. Application of the TKI funds as counter financing source for institutes and universities might improve quality and solve the problem of financing in international programs. Quite a diverse group of projects take place under the SCE TKI program, many litho related: regarding immersion lithography, EUV, mirror technology, E-beam litho technology, improved and plasma resistant mirrors, alignment technologies to assure an overlay substantially less than 1nm and a wafer stage capable of 300 wafers/hour and if feasible the realization of a technology demonstrator for a flexible printer. 3.2 European Program First focus in the SCE Roadmap for the International cooperation is on the realization of enabling equipment and process modules for 7nm and beyond on 300mm wafers. The Dutch supply chain will broadly participate in the Dutch contingent of these large international projects. Projects will be submitted in ECSEL and/or Penta, with process, litho and/or metrology focus. The ultimate goal is to realize a pilot facility for 7nm and beyond, maximally equipped with European generated equipment. 4. Partners and process Some thirty Dutch OEMs, like ASM, ASML, Mapper and Thermo Fisher and smaller companies like BESI, ALSI, SolMateS and Bronkhorst are all active in the SCE sector, while a very large number are active in the supply chain. This dynamic group of more than 200 companies is committed to actively participate in the SCE program. Also Carl Zeiss SMT is a major investor in Dutch R&D, presently mainly in EUV mirror program at the UTwente. Prime scientific participants are ARCNL, UT, TUD, TU/e, DIFFER, while RUG, UvA, VU, UU, UL, VU, SRON, ASTRON, Nikhef are also participating. Important institutes are M2I, ESI and TNO. 5. Investments The SCE sector is by far the largest private R&D investor in the Netherlands, more than 1B yearly or more than one sixth of the total Dutch private R&D investment and more than one third of the R&D investment in the HTSM sector. The tables below show estimated contributions of the stated parties in public-private collaborations in relation to the Semiconductor Equipment roadmap. The trend clearly shows the impact of recent introduction of capping of the ECSEL JU projects to a maximum of 150M from 2016 onwards. Hence the European and National contributions in the sector is declining, further increasing the gap between total private R&D investment and the EU and national funded R&D cooperation programs and challenge the SCE sector to curb this trend. 5 of 6

6 Roadmap Industry TNO NLR NWO Universities Departments 4 and regions Grand total European agenda within roadmap Industry TNO NLR NWO Universities Co-financing of European programs European Commission Ministries, excluding contributions to TKI HTSM 5 Regional and Local Authorities 6 Ministry of Economic Affairs contributions to JU ECSEL and EUREKA clusters 6 of 6