Facing Moore s Law with Model-Driven R&D

Transcription

1 Facing Moore s Law with Model-Driven R&D Markus Matthes Executive Vice President Development and Engineering, ASML Eindhoven, June 11 th, 2015

2 Slide 2 Contents Introducing ASML Lithography, the driving force behind Moore s Law How to continue driving Moore s law? Summary and conclusions

3 Introducing ASML Slide 3

4 It s hard to imagine a world without chips Global market 2014: 221 billion chips, $333 billion Slide 4

5 ASML makes the machines for making those chips Slide 5 Lithography is the critical tool for producing chips All of the world s top chip makers are our customers 2014 sales: 5.9 bln People: ~14,000 FTEs

6 Founded in 1984 as a spin-off from Philips Slide 6

7 with global presence! Slide 7 3,100 employees 8,600 employees 2,400 employees Source: ASML Q Over 70 sales and service offices located worldwide

8 Moore s law Slide 8

9 Driving the semiconductor industry: Moore s Law Slide 9 Gordon Moore (1965): Number of transistors per chip doubles every year. Later adjusted to two years, the trend has held for half a century

10 Flash price per GB (in dollars) Moore s Law makes chips cheaper Slide $110 for 1 GB $0.46 for 1 GB Total 2005 Total 2006 Total 2007 Total 2008 Total NAND Flash price 1 GB [$] 2009 Total 2010 Total 2011 Total 2012 Total 2013 Total 2014 Est. Total 0,1

11 Computations per kwh and more energy-efficient Computations per Kilowatt hour double every 1.5 years Slide 11 1.E+16 1.E+15 1.E+14 1.E+13 1.E+12 1.E+11 1.E+10 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 Univac I Eniac EDVAC SDS 920 IBM PC Cray 1 supercomputer DEC PDP-11/20 Univac II Univac III (transistors) Dell Dimension 2400 Gateway P MHz IBM PS/2E + Sun SS1000 IBM PC-AT IBM PC-XT Commodore laptops SiCortex SC5832 Dell Optiplex GXI 486/25 and 486/33 Desktops Regression results: N = 76 Adjusted R-squared = Comps/kWh = exp( x year ) Average doubling time (1946 to 2009) = 1.57 years 1.E Source: Jonathan Koomey, Lawrence Berkeley National Laboratory and Stanford University, 2009

12 Lithography, the driving force behind Moore s Law Slide 12

13 A chip is made of dozens of layers Slide 13

14 The manufacturing loop Slide 14 Ion implantation Stripping Deposition Etching Developing Exposure (the Lithography step) Photoresist coating

15 Lithography is critical for shrinking transistors Slide 15 Like a photo enlarger of old, lithography forms the image of chip patterns on a wafer

16 The ASML ecosystem makes this happen Slide 16

17 Open Innovation from design to manufacturing Slide 17 Customers Semiconductor producers Co-solution network Mask, Resist, Wafer track Wafer processing Supplier and partner network Optics, measurement systems, parts, subsystems Virtual innovation network Academia, technology providers, research institutes

18 Open Innovation from design to manufacturing Customers Slide 18 Co-solution partners Suppliers Academia Technology partners Advanced Research Center for Nanolithography

19 Slide 19 Increasing complexity, increasing challenges

20 Scanner functionality and hardware become increasingly more complex Slide 20 The world is far from perfect at (sub-)nanometer level Flat is no longer flat, straight is no longer straight Variations due to flow, temperature and humidity variations Sensitivity to dynamics, magnetics, and pressure differences

21 Physics, mathematics and software correct hardware imperfections at (sub-)nanometer level Slide 21

22 Example: Lens Model Laser beam heats up lens A sensor measures the lens aberrations The lens model calculates how to adjust the lens (within 12 ms) Lens is adjusted and wafer is exposed in optimum state Laser Beam Reticle Projection Lens Reticle stage Slide 22 Lens model implemented in MATLAB Timing constraints met by code optimization together with MathWorks: 39% speed gain Wafer stage Wafer

23 ASML software development reflects increasing complexity Slide 23 TWINSCAN software consists of 40 million lines of code More than 500,000 lines of MATLAB code in TwinScan archive 20+ computing nodes running more than 200 processes Our software supports old as well as new systems SW archive embeds > 10 years of development history, thousands of man years of work

24 Slide 25 How to continue driving Moore s law?

25 The other side of Moore s medal Development & engineering costs rapidly growing Slide s: 1990s: 2000s: 2010s: PAS 2000/5000 PAS 5500 TWINSCAN NXE EUV R&D: 50 mln R&D: 400 mln R&D: 1500 mln R&D: > 2000 mln How to continue driving Moore s law and ensure customer profitability, while keeping R&D cost under control?

26 Investing in early development phase leads to gain in Slide 27 product maturing phase and earlier customer profitability Effort vs. time Less issues at integration, less redesigns to meet spec; availability, good dies/day Early development phase Product Quarters maturing phase

27 But how to invest more in the early development phase? Let us look at a Development and Engineering work flow Slide 28 design validation integration validation model realization integration component realization validation

28 Different approach needed to reduce development effort Slide 29 solution implementation, testing and maintenance paradigms, models, technology and tools

29 Model Driven Engineering vision Slide 31 Requirements Tracing Define Requirements Model in the Loop (Simulation) Property Proving System-Level Specification Formal Verification Standards Checking Models i.s.o. Documents Subsystem Design Simulink Plant Model TPD / Code Generation Subsystem Implementation Subsystem Integration and Test System-Level Integration and Test Module Validation Software in the Loop Complete Integration and Test Hardware in the Loop Subsystem Validation System Validation

30 Slide 32 Summary and conclusions

31 Summary and Conclusions Slide 33 Moore s Law has shaped the world as we know it Lithography has enabled and driven Moore s Law Moore s law for product development is not sustainable To continue driving Moore s law, the R&D way of working needs to evolve towards a system-wide model driven engineering approach Directions pursued are: higher abstraction levels, executable specifications (models instead of documents), formal model verification and design time validation, automatic code generation Further elaboration of industry standards is desirable to easily connect solutions across the development chain Strategic partnerships, such as between ASML and MathWorks, are instrumental to achieve this

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