Co-Design Pain Points, Tooling Gaps, and Lessons from the Past
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1 Co-Design Pain Points, Tooling Gaps, and Lessons from the Past Andrew B. Kahng, UC San Diego CSE and ECE Depts. ECTC Evening Panel, May 29, 2018
2 Pain Heterogeneous integration à multi-everything physics, scale, domain, hierarchy Tech files, signoff criteria, corners AVS STA-IR loop IR Drop Map Sim Results (Dyn.) Activity Factor (Static) Workload-Thermal loop Power Trace Functional Sim Thermal Analysis Sim vectors Benchmark RTL Slack Timing / Glitches Power Analysis STA-Thermal loop Temp Map P&R + Optimization Timing/ Noise Reliability Report Task Mapping/ Migration/ (DVFS) STA-Reliability loop MTTF & Aging
3 Pain Heterogeneous integration à multi-everything Imagine the pain of system-on-chip design physics, scale, domain, hierarchy
4 Pain Heterogeneous integration à multi-everything physics, scale, domain, hierarchy Imagine the pain of system-on-chip design, for which guidance looks like:
5 Extreme Pain Heterogeneous integration à multi-everything physics, scale, domain, hierarchy Imagine the pain of system-on-chip design Now imagine the pain of system-in-package, 2.xD / 3D, heterogeneous integration co-design = today s panel J MISSING: Pathfinding (tech,system,design) Design Space Exploration Optimization vs. Checking What is possible vs. Will it work
6 Pain Points = Tool Gaps IC, Package, Board tools: different worlds (R&D $, usage, ) Many cross-domain integrations: power delivery, timing signoff, cost High-quality system partitioning, layout; Physics signoff with less margin HI co-design adds system, architecture to layout, signoff System designers are not like layout engineers! à DSE, Pathfinding, Architecture Specification, synthesis, verification at system / HI level Mix-and-match of chiplets to meet system spec What chiplets should be available for co-integration? Encapsulation of co-integration technology usable by design tools Interoperability wrapper for co-integration within package
7 10000x Gaps: Not Business As Usual! Multiphysics Checker has 10000x Speed Gap vs. Optimizable Objective Function Analysis ¹ Optimization Accuracy ¹ Fidelity Machine Learning (predictors, optimizable models) likely essential!!!
8 Must Have Starting Die-Pkg-PCB Backplane
9 Lessons From the Past Fact: Non-emergence of commercial EDA solutions for Co-Design Long history of multi-die integration: MCM, SIP, 3-D / 2.5-D, Small available market mismatches commercial EDA model Lots of chicken-egg interlocks L Fact: Co-design tools and flows exist today (evidenced by products) Based on existing IC design standards, tool flows, methodologies Which system products will drive fundamentally new co-design tools/methods? Could a free, open-source software (FOSS) ecosystem address HI co-design tool needs? See: DARPA IDEA (!) Andreas Olofsson, DARPA ISPD-2018 keynote March 27,
10 Avi s Three Questions What is the state of the art in co-design? Unchanged preoccupation with analyses/checkers: +physics, +scale, +layers Lack of pathfinding, DSE, optimization has unknown cost But, harms design schedule, system optimizations (cross-layer, multiphysics, ) What are the key challenges that need to be overcome? Lack of well-defined co-design enablements, methodologies, automation of design synthesis and optimization What needs to happen for these challenges to be overcome? Not sure.! History: heart attacks ( Pentium bug, ASP competition) drive tool R&D investment Tool specs, benchmarks, problem statements can be enormously influential! Invest in machine learning (e.g., to span 10000x gaps in optimization vs. analysis) Enable open-source tool ecosystem for co-design optimization (= outsource beyond commercial tool providers)
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