Optimal design methodology for RF SiP - from project inception to volume manufacturing

Transcription

1 Optimal design methodology for RF SiP - from project inception to volume manufacturing Chris Barratt Insight SiP 905 rue Albert Einstein Valbonne France 06560

2 Outline RF SiP Technologies Design Methodology Initial Design Phase Detailed Design Phase Examples Bluetooth Modules WLAN Modules Integrated IQ Mixer

3 Motivation RF SiP is a road to get system solutions to market fast and at reasonable cost Optimized choice of SiP Technology gives lowest production costs The design methodology has to be: Fast and accurate Adaptable to all available technologies Allow for maximum design creativity for new passive structures The design strategy is proven for LTCC, Laminate and Thin Film IPD

4 Pros & Cons Feasibility study is key to make best SiP choice Methodology gives close to first pass success for embedded passives (matching, filters, baluns,..) System related issues tend to be discovered during initial testing Requires a pro-active approach to reduce digital/clock interference issues Design spins can be created by chip related issues that are discovered during SiP debug

5 RF System in Package Complete 3D RF system RF BB semi-conductors SMT passives Buried RF passives Interface to application PCB (LGA, BGA) Fully self contained system Tested Semiconductor package format

6 Rôle of SiP in System Life Cycle Time to Market in Months Design cost à à x x x SiP 10 x 10 mm 1 st level of Integration on PCB 30 x 30 mm 3.5 x SiP 5 x 5 mm 6 à 12 (Bluetooth Model) Prototypes 50 x 50 mm Design Complexity Level of integration Size reduction

7 RF SiP Substrate Technologies Laminate based (ε r 3 5) 4 to 6 metal layers Interco. RF Baluns in substrate LTCC based (ε r 7 10) 6 to 20 metal layers Interco. RF baluns, Filters, matching in substrate

8 RF SiP Substrate Technologies Silicon Based (ε r 11.2) 2 to 4 metal layers + doping Interco. RF baluns, Filters, matching and high C in substrate

9 Thin Film on Silicon from NXP

10 RF SiP Design Design for manufacture Highly integrated (RF) systems and subsystems System in Package approach Multi-technologies : PCB, LTCC, Thin film, Thick film Emphasis on optimum overall cost in production Use of mature non proprietary technologies available on the open market

11 RF SiP Design Initial Design & Feasibility Determine tradeoffs Select technology platform Determine system partitioning

12 RF SiP Design Detail Design Create and optimize schematic Generate and validate layout and assembly Build and validate prototypes

13 Initial Design & Feasibility - Aim Chose System Architecture Performances according to the Market Requirement, Production and Development Costs, Design to Production Lead Time.

14 Initial Design Feasibility - Method System partition Semiconductor Technology Choice : Si, GaAs, SiGe, SiP Technology Choice : Laminate, LTCC, Silicon Based, Thin Film on Glass, Assembly options (Flip-chip vs Bond-wires) Buried passives vs thin film passives vs SMT Compare SiP substrates Size, Cost, NRE Compare Assembly options Wire-bonding, Flip-chip, RDL, bumping, SMT, Compare test options

15 Initial Design Feasibility - Example

16 Initial Design Feasibility - Example SiP Comparison Substrate Size & Performances vs type Assembly options Cost & Time to Production

17 Detail Design System Design Partition Functions Die, SMT, Substrate Detailed Design of Buried Functions Layout Complete SiP Integrate all Functions Measure Buried Functions Adjust BoM Test Complete SiP N OK? Production Electrical Schematic Optimise Choose Layer Structure Generate Parametric Mechanical Objects EM simulate Parametric Objects Optimise Circuit with Parametric Objects Auto generate 3D layout Full EM simulation of 3D layout N OK? Y Optimise Layout Standard EDA software based Flexible process no fixed libraries Step-by-step Process

18 Detail Design System model development Project-specific component library Circuit Optimization taking interactions into account Exhaustive simulation of electromagnetic behavior Performance Optimization through electro-magnetic simulation feedback to circuit model. Proven two-pass success (with one-pass objective)

19 Detail Design EDA Tools S Parameters Active Circuits Parametrical/Mechanical Objects S Parameters For Each Object Circuit Simulation, ADS, Designer, EM/Circuit Simulation, ADS, Designer, HFSS, CTS Layout/EM ADS, Cadence, Designer, Circuit Design L, C, Balun Buried Function Design Layout Design SiP Final Test Test of Buried Functions Substrate Manufacturing Multi-layers / Thin Film

20 Design Flow for Buried Functions Electrical Schematic L Choose Layer Structure C1 C2 One pass success Generate Parametric Mechanical Objects Optimise Circuit with Mechanical Parameters Auto Layout Generation EM Check Layout Y X X L S(X,Y) Parameters X,Y TL 1 TL 2 TL 3 TL 4 X C1 X C2 Optimise Layout OK X C1 X L XC2

21 UWB Filter Example Paremeter Units Spec Comments IL db < to 4.7 GHz RL db > to 4.7 GHz Rej WLAN b/j db >20 2 to 2.6 GHz Rej WLAN a db > to 6 GHz Schematic Z=Zs Ohm E=Es Z=Zs1 Ohm E=Es1 Z=Zs Ohm E=Es Z=Zs1 Ohm E=Es1 Z=Zint Ohm E=Eint Z=Zs2 Ohm E=Es2 Z=Zs3 Ohm E=Es3 Z=Zs2 Ohm E=Es2 Z=Zs3 Ohm E=Es3 Z=Zint1 Ohm E=Eint1 Z=Zs4 Ohm E=Es4 Z=Zs5 Ohm E=Es5 Z=Zs4 Ohm E=Es4 Z=Zs5 Ohm E=Es5 0 S21 < -20dB GHz S11 < -20 db S GHz db(s(1,1)) db(s(2,1)) -20 < -20 db GHz Num=1 Z=50 Ohm Z=Zp Ohm E=Ep Z=Zp1 Ohm E=Ep1 Z=Zp2 Ohm E=Ep2 Num=2 Z=50 Ohm freq, GHz

22 1 2 L3000 to 7500 um 1 1 UWB Filter Example Generate Parametric Objects using EM simulator Schematic Layout L3000 to 7500 um 1 2 Optimize Circuit with Parametric Objects W=W L=L W=W L=L W=W2 L=L2 W=W2 L=L2 W=W4 L=L4 W=W4 L=L4 L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 W=Wint L=Lint L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 W=Wint1 L=Lint1 L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 W=W1 L=L1 W=W1 L=L1 W=W3 L=L3 W=W3 L=L3 W=W5 L=L5 W=W5 L=L5 L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 L3000 to 7500 um 1 2 Num=1 Z=50 Ohm W=Wp L=Lp L3000 to 7500 um 2 W=Wp1 L=Lp1 L3000 to 7500 um 2 W=Wp L=Lp Num=2 Z=50 Ohm

23 UWB Filter Example Auto-generate Layout Simulate layout Optimise to lock performance S21 < -20dB GHz S11 < -20 db S21 db(s(1,1)) db(s(2,1)) GHz < -20 db GHz freq, GHz

24 Examples Bluetooth Module WLAN Module 8 x 8 x 1.4 mm LTCC IQ Mixer 4 x 4 mm IPD for 433 MHz Various GPS Modules Laminate and Silicon UWB LTCC and Laminate

25 Conclusions RF SiP offers short time to market Feasibility allows choice of best technology Design process is under control Design process remains flexible Close to first pass design success