CD4051BMS, CD4052BMS and CD4053BMS analog multiplexers/demultiplexers

Transcription

1 CDBMS, CDBMS CDBMS December Features Logic Level Conversion High-Voltage Types (V Rating) CDBMS Signal -Channel CDBMS Differential -Channel CDBMS Triple -Channel Wide Range of Digital and Analog Signal Levels: - Digital V to V - Analog to Vp-p Low ON Resistance: Ω (typ) Over Vp-p Signal Input Range for - = V High OFF Resistance: Channel Leakage of ±pa (typ) at - = V Logic Level Conversion: - Digital Addressing Signals of V to V ( - = V to V) - Switch Analog Signals to Vp-p ( - = V); See Introductory Text Matched Switch Characteristics: RON = Ω (typ) for - = V Very Low Quiescent Power Dissipation Under All Digital Control Input and Supply Conditions:.µW (typ) at - = - = V Binary Address Decoding on Chip V, V and V Parametric Ratings % Tested for Quiescent Current at V Maximum Input Current of µa at V Over Full Package Temperature Range; na at V and + o C Description CMOS Analog Multiplexers/Demultiplexers CDBMS, CDBMS and CDBMS analog multiplexers/demultiplexers are digitally controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to V peak-topeak can be achieved by digital signal amplitudes of.v to V (if - = V, a - of up to V can be controlled; for - level differences above V, a - of at least.v is required). For example, if = +.V, =, and = -.V, analog signals from -.V to +.V can be controlled by digital inputs of to V. These multiplexer circuits dissipate extremely low quiescent power over the full - and - supply voltage ranges, independent of the logic state of the control signals. When a logic is present at the inhibit input terminal all channels are off. The CDBMS is a single channel multiplexer having three binary control inputs, A, B, and C, and an inhibit input. The three binary signals select of channels to be turned on, and connect one of the inputs to the output. The CDBMS is a differential channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select of pairs of channels to be turned on and connect the analog inputs to the outputs. The CDBMS is a triple channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single pole double-throw configuration. The CDBMS, CDBMS and CDBMS are supplied in these lead outline packages: Braze Seal DIP HX HT Break-Before-Making Switching Eliminates Channel Overlap Applications Analog and Digital Multiplexing and Demultiplexing A/D and D/A Conversion Signal Gating When these devices are used as demultiplexers the CHANNEL terminals are the outputs and the COMMON OUT/IN terminals are the inputs. Frit Seal DIP Ceramic Flatpack CDB Only HE HW CDB, CD Only CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. --INTERSIL or -- Copyright Intersil Corporation - File Number

2 CDBMS, CDBMS, CDBMS Pinouts CDBM TOP VIEW CDBMS TOP VIEW CHANNELS COM OUT/IN CHANNELS INH A CHANNELS Y CHANNELS COMMON Y OUT/IN Y CHANNELS INH X CHANNELS COMMON X OUT/IN X CHANNELS B A C B CDBMS TOP VIEW by bx OUT/IN bx or by cy OUT/IN ax or ay OUT/IN CX or CY CX ay ax INH A B C Functional Diagrams CHANNEL A B C LOGIC LEVEL CONVERSION BINARY TO OF DECODER WITH INHIBIT COMMON OUT/IN INH ALL INPUTS PROTECTED BY STANDARD CMOS PROTECTION NETWORK CDBMS -

3 CDBMS, CDBMS, CDBMS Functional Diagrams (Continued) X CHANNELS A B LOGIC LEVEL CONVERSION BINARY TO OF DECODER WITH INHIBIT COMMON X OUT/IN COMMON Y OUT/IN INH Y CHANNELS CDBMS ALL INPUTS PROTECTED BY STANDARD CMOS PROTECTION NETWORK LOGIC LEVEL CONVERSION BINARY TO OF DECODERS WITH INHIBIT cy cx by bx ay ax OUT/IN ax or ay A B OUT/IN bx or by C OUT/IN cx or cy INH CDBMS -

4 Specifications CDBMS, CDBMS, CDBMS Absolute Maximum Ratings DC Supply Voltage Range, () V to +V (Voltage Referenced to Terminals) Input Voltage Range, All Inputs V to +.V DC Input Current, Any One Input ±mA Operating Temperature Range o C to + o C Package Types D, F, K, H Storage Temperature Range (TS) o C to + o C Lead Temperature (During Soldering) o C At Distance / ± / Inch (.mm ±.mm) from case for s Maximum Reliability Information Thermal Resistance θ ja θ jc Ceramic DIP and FRIT Package..... o C/W o C/W Flatpack Package o C/W o C/W Maximum Package Power Dissipation (PD) at + o C For TA = - o C to + o C (Package Type D, F, K) mw For TA = + o C to + o C (Package Type D, F, K).....Derate Linearity at mw/ o C to mw Device Dissipation per Output Transistor mw For TA = Full Package Temperature Range (All Package Types) Junction Temperature o C TABLE. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A LIMITS PARAMETER SYMBOL CONDITIONS (NOTE ) SUBGROUPS TEMPERATURE MIN MAX UNITS Supply Current IDD = V, VIN = or GND + o C - µa + o C - µa = V, VIN = or GND - o C - µa Input Leakage Current IIL VIN = or GND = + o C - - na + o C - - na = V - o C - - na Input Leakage Current IIH VIN = or GND = + o C - na + o C - na = V - o C - na On-State Resistance RL = K Returned to - / RON = V VIS = to = V VIS = to + o C - Ω + o C - Ω - o C - Ω + o C - Ω + o C - Ω - o C - Ω = V + o C - Ω VIS = to + o C - Ω - o C - Ω N Threshold Voltage VNTH = V, ISS = -µa + o C V P Threshold Voltage VPTH = V, IDD = µa + o C.. V Functional (Note ) Input Voltage Low (Note ) Input Voltage High (Note ) Input Voltage Low (Note ) Input Voltage High (Note ) Off Channel Leakage Any Channel OFF Or All Channels Off (Common Out/In) NOTES: F =.V, VIN = or GND = V, VIN = or GND + o C + o C VOH > / = V, VIN = or GND A + o C = V, VIN = or GND B - o C VOL < / VIL = V = VIS thru k,,, + o C, + o C, - o C -. V = VIH RL = k to, IIS < µa OFF Channels,, + o C, + o C, - o C. - V VIL = V = VIS thru K,, + o C, + o C, - o C - V = VIH RL = K to, ISS, <µa On All OFF Channels,, + o C, + o C, - o C - V IOZL IOZH VIN = or GND VOUT = V VIN = or GND VOUT =. All voltages referenced to device GND, % testing being implemented.. Go/No Go test with limits applied to inputs. = V + o C -. - µa + o C -. - µa = V - o C -. - µa = V + o C -. µa + o C -. µa = V - o C -. µa. For accuracy, voltage is measured differentially to. Limit is.v max.. =.V/.V, RL = k to = V/V, RL = k to V -

5 Specifications CDBMS, CDBMS, CDBMS TABLE. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (Notes, ) Propagation Delay (Note ) Address to Signal Out Channels On or Off Propagation Delay (Note ) Inhibit to Signal Out (Channel Turning On) Propagation Delay (Note ) Inhibit to Signal Out (Channel Turning Off) TPHL TPLH TPZH TPZL TPHZ TPLZ = V, VIN = or GND = = V = V, VIN = or GND = = V = V, VIN = or GND = = V NOTES:. - o C and + o C limits guaranteed, % testing being implemented.. CL = pf, RL = KΩ, Input TR, TF < ns. GROUP A SUBGROUPS TEMPERATURE MIN LIMITS MAX UNITS + o C - ns, + o C, - o C - ns + o C - ns, + o C, - o C - ns + o C - ns, + o C, - o C - ns TABLE. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD = V, VIN = or GND, - o C, + o C - µa + o C - µa = V, VIN = or GND, - o C, + o C - µa + o C - µa = V, VIN = or GND, - o C, + o C - µa + o C - µa Input Voltage Low VIL = VIS = V, = RL = K to IIS, µa On/Off Channel, + o C, + o C, - o C Input Voltage High VIH, + o C, + o C, - o C Propagation Delay Address to Signal Out (Channels On or Off) Propagation Delay Inhibit to Signal Out (Channel Turning On) Propagation Delay Inhibit to Signal Out (Channel Turning Off) TPHL TPLH TPZH TPZL TPHZ TPLZ - V + - V = V = = V,, + o C - ns = V,, + o C - ns = V = -V,, + o C - ns = V = = V,, + o C - ns = V,, + o C - ns = V = -V,, + o C - ns = V = = V,, + o C - ns = V,, + o C - ns = V = -V,, + o C - ns Input Capacitance CIN Any Address or Inhibit Input, + o C -. pf NOTES:. All voltages referenced to device GND.. The parameters listed on Table are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics.. CL = pf, RL = K, Input TR, TF < ns. -

6 Specifications CDBMS, CDBMS, CDBMS TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD = V, VIN = or GND, + o C - µa N Threshold Voltage VNTH = V, ISS = -µa, + o C V N Threshold Voltage VTN = V, ISS = -µa, + o C - ± V Delta P Threshold Voltage VTP = V, IDD = µa, + o C.. V P Threshold Voltage VTP = V, IDD = µa, + o C - ± V Delta Functional F = V, VIN = or GND = V, VIN = or GND + o C VOH > / Propagation Delay Time TPHL TPLH NOTES:. All voltages referenced to device GND.. CL = pf, RL = K, Input TR, TF < ns. VOL < / = V,,, + o C -. x + o C Limit. See Table for + o C limit.. Read and Record V ns TABLE. BURN-IN AND LIFE TEST DELTA PARAMETERS + O C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI- IDD ±.µa ON Resistance RONDEL ± % x Pre-Test Reading TABLE. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD- METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) %,, IDD, IOL, IOHA, RONDEL Interim Test (Post Burn-In) %,, IDD, IOL, IOHA, RONDEL Interim Test (Post Burn-In) %,, IDD, IOL, IOHA, RONDEL PDA (Note ) %,,, Deltas Interim Test (Post Burn-In) %,, IDD, IOL, IOHA, RONDEL PDA (Note ) %,,, Deltas Final Test %,, A, B,, Group A Sample,,,, A, B,,, Group B Subgroup B- Sample,,,, A, B,,,, Deltas Subgroups,,,,, Subgroup B- Sample,, Group D Sample,,, A, B, Subgroups, NOTE:. % Parameteric, % Functional; Cumulative for Static and. TABLE. TOTAL DOSE IRRADIATION MIL-STD- TEST READ AND RECORD CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup,, Table, Table TABLE. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND V ± -.V PART NUMBER CDBMS khz khz -

7 Specifications CDBMS, CDBMS, CDBMS TABLE. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND V ± -.V khz khz Static Burn-In Note,, -,,, - Static Burn-In Note Dynamic Burn- In Note Irradiation Note,,, -, - - -,,,,,,,,,,,, -, - PART NUMBER CDBMS Static Burn-In Note,,, -,,, -,, Static Burn-In Note Dynamic Burn- In Note Irradiation Note,,,, -, -, - - -,,,,,,,,,,,,, -, -, - PART NUMBER CDBMS Static Burn-In Note Static Burn-In Note Dynamic Burn- In Note Irradiation Note,, -, -, -,,, -,,, -, -, -,,,,,, -,,, -,,, -, NOTE:. Each pin except pin and GND will have a series resistor of K ± %, = V ±.V. Each pin except pin and GND will have a series resistor of K ± %; Group E, Subgroup, sample size is dice/wafer, failures, = V ±.V Typical Performance Characteristics SUPPLY VOLTAGE ( - ) = V SUPPLY VOLTAGE ( - ) = V CHANNEL ON RESISTANCE (RON) (Ω) AMBIENT TEMPERATURE (T A ) = + o C + o C - o C CHANNEL ON RESISTANCE (RON) (Ω) AMBIENT TEMPERATURE (T A ) = + o C + o C - o C INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE. TYPICAL CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE. TYPICAL CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) -

8 CDBMS, CDBMS, CDBMS Typical Performance Characteristics (Continued) CHANNEL ON RESISTANCE (RON) (Ω) AMBIENT TEMPERATURE (T A ) = + o C SUPPLY VOLTAGE ( - ) = V V V CHANNEL ON RESISTANCE (RON) (Ω) SUPPLY VOLTAGE ( - ) = V AMBIENT TEMPERATURE (T A ) = + o C + o C - o C INPUT SIGNAL VOLTAGE (VIS) (V) INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE. TYPICAL CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLAE (ALL TYPES) OUTPUT SIGNAL VOLTAGE (VOS) (V) SUPPLY VOLTAGE () = V = V = -V AMBIENT TEMPERATURE (T A ) = + o C LOAD RESISTANCE (RL) = kω, kω kω Ω Ω INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE. TYPICAL ON CHARACTERISTICS FOR OF CHANNELS (CDBMS) POWER DISSIPATION/PACKAGE (PD) (µw) FIGURE. TYPICAL CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) AMBIENT TEMPERATURE (T A ) = + o C ALTERNATING O AND I PATTERN LOAD CAPICATANCE (CL) = pf SUPPLY VOLTAGE () (V) V V V CL = pf TEST CIRCUIT f B/D CD A B C Ω CD Ω SWITCHING FREQUENCY (f) (khz) FIGURE. TYPICAL DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CDBMS) Ι CL POWER DISSIPATION/PACKAGE (PD) (µw) AMBIENT TEMPERATURE (T A ) = + o C ALTERNATING O AND I PATTERN LOAD CAPICATANCE (CL) = pf SUPPLY VOLTAGE () (V) V V V CL = pf TEST CIRCUIT f B/D CD A B Ω CL CD Ω Ι POWER DISSIPATION/PACKAGE (PD) (µw) AMBIENT TEMPERATURE (T A ) = + o C ALTERNATING O AND I PATTERN LOAD CAPICATANCE (CL) = pf SUPPLY VOLTAGE () (V) V V V CL = pf TEST CIRCUIT f CL Ω Ω CD Ι SWITCHING FREQUENCY (f) (khz) FIGURE. TYPICAL DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CDBMS) SWITCHING FREQUENCY (f) (khz) FIGURE. TYPICAL DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CDBMS) -

9 CDBMS, CDBMS, CDBMS = +V = +.V = +V = +V.V V V = V = V = V = V = V = -.V = -V = -V (a) (b) (c) (d) The ADDRESS (digital-control inputs) and INHIBIT logic levels are: = and =. The analog signal (through the ) may swing from to FIGURE. TYPICAL BIAS VOLTAGES -

10 CDBMS, CDBMS, CDBMS TRUTH TABLE INPUT STATES ON CHANNEL(S) CDBMS INHIBIT C B A X X X NONE CDBMS INHIBIT B A x, y x, y x, y x, y x x NONE CDBMS INHIBIT A OR B OR C ax or bx or cx ay or by or cy X NONE X = Don t Care tpzl % % % tr = ns % % % % TURN-ON TIME % % % TURN-OFF TIME tf = ns tplz FIGURE. WAVEFORM, CHANNEL BEING TURNED ON, OFF (RL = kω) % tphz tr = ns % % % TURN-OFF TIME % % tf = ns % % TURN-ON TIME tpzh FIGURE. WAVEFORM, CHANNEL BEING TURNED OFF, ON (RL = kω) CD RL OUTPUT CL CLOCK IN CL OUTPUT RL CD CLOCK IN OUTPUT RL CL CD CLOCK IN FIGURE. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT -

11 CDBMS, CDBMS, CDBMS OUTPUT RL CLOCK IN pf tphl AND tplh CD OUTPUT RL CLOCK IN pf CD tphl AND tplh OUTPUT RL pf CLOCK IN tphl AND tplh CD FIGURE. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT DIFFERENTIAL SIGNALS CD CD COMMUNICATIONS LINK DIFF AMPLIFIER/ LINE DRIVER DIFF RECEIVER DIFF MULTIPLEXING DEMULTIPLEXING FIGURE. TYPICAL TIME-DIVISION APPLICATION OF THE CDBMS -

12 CDBMS, CDBMS, CDBMS Chip Dimensions and Pad Layouts CDBMSH CDBMSH CDBMSH Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils ( - inch) METALLIZATION: Thickness: kå kå, AL. PASSIVATION:.kÅ -.kå, Silane BOND PADS:. inches X. inches MIN DIE THICKNESS:. inches -. inches All Intersil semiconductor products are manufactured, assembled and tested under ISO quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site