Design considerations of Paralleled GaN HEMT-based Half Bridge Power Stage

Transcription

1 Design considerations of Paralleled GaN HEMT-based Half Bridge Power Stage Last update: July 17, 2018 GaN Systems 1

2 Contents Paralleling design considerations Layout considerations for paralleling GaN Design example of 4x paralleled GaN power stage Experimental results GaN Systems 2

3 Paralleling design considerations What are key considerations when paralleling power switches: Design parameters Effect on paralleling Desired RDS(on) Affect static current sharing. Positive temperature co-efficient for self-balancing Gate threshold, VGS(th) Impact dynamic current sharing during turn-on and off. Lower Vth results in earlier turn-on and higher switching current/loss which creates positive feedback Trans-conductance, gm Impact dynamic current sharing during turn-on and off. Circuit design and layout Balanced circuit layout are important for dynamic current sharing and stability of the paralleling operation. This is particularly critical for high speed power switches such as GaN/SiC Tight distribution, temperature independent or positive temperature co-efficient Tight distribution, temperature independent or negative temperature co-efficient Minimize and equalize all layout parasitics to reduce circuit mismatch Thermal Affect the device temperature difference. Tj variation may cause dynamic or static current sharing issues depending on device characteristics. All paralleled devices should have similar thermal resistance and installed on same heatsink for good thermal balance. GaN Systems 3

4 R DS(on) vs T J GaN E-HEMT has positive temperature co-efficient R DS(on) Compared to SiC, strong temperature dependency of R DS(on) of GaN helps the current sharing in parallel operation GaN E-HEMT R DS(on) vs T J SiC R DS(on) vs T J NTC Region PTC Region GaN Systems 4

5 V GS(th) vs T J GaN E-HEMT has stable gate threshold over the temperature range Si/SiC MOSFET V GS(th) decreases with temperature: Hotter drive turn-on earlier positive feedback GaN E-HEMT V GS(th) is stable over T J range SiC V GS(th) decreases with T J No noticeable change from T J = 25 to 150C -24% decrease GaN Systems 5

6 Trans-conductance, g m vs T J GaN E-HEMT Trans-conductance g m decreases with temperature, good for paralleling This characteristics, together with stable V GS(th), helps with dynamic current sharing and self-balancing GaN HEMT SiC MOSFET SJ MOSFET I DS decreases at same V GS at higher T J With same V GS, I DS increase at higher T J g m = ΔI DS / ΔV GS V GS(th) V GS(th) SiC: V GS(th) drops and gm slightly increases: Hotter device tends to have higher switching current -> higher switching loss Positive feedback, potential thermal runaway if not designed properly Si: Vth decreases and gm remain constant: Slightly positive feedback with T J GaN Systems 6

7 Effect of g m on switching transient Negative feedback for self balancing in parallel: T J - g m - I D@switching - E on - T J 2x GS66508T paralleled 400V/30A turn-on waveforms with different T J I T J = 25C Eon=92uJ V GS I T J = 125C Eon=58uJ GaN Systems 7

8 Circuit layout - Low inductance of GaNPX package GaNPX package improves the paralleling performance and stability Traditional package has high source inductance that impacts paralleling performance GaNPX package has ultra low Ls compared to traditional package Top-cooled T package features symmetric dual gate pads for easier layout GaNPX T Package GS66516T (650V/25mΩ) Ansys Q3D 3D modeling of GS66516T TO-247 Package inductance Top side Bottom side G D S Ls = ~10-15nH Package Source inductance Ls=0.05nH GaN Systems 8

9 Circuit layout - advantages of GaNPX dual gate Dual gate reduces the total gate drive loop in paralleling design Easier to make symmetric gate drive layout Reduce total layout footprint area 2x TO-247 Parallel layout Q1 G D S G Q2 HEATSINK 2x GS66516T Parallel layout S G G S Q1 Q2 D D D S GaN Systems 9

10 Key design considerations for paralleling GaN Compared to other technologies: GaN Systems E-HEMT characteristic is inherently good fit for paralleling as discussed. The R DS(on) and GaN transfer characteristics provide strong negative feedback to self balance and compensate device and circuit mismatch Circuit layout is most critical to GaN: Ensure successful paralleling and optimum dynamic performance. Therefore, this presentation will focus on gate drive and circuit layout discussion for dynamic performance of paralleling GaN: The impact of circuit parasitics on paralleling was analyzed A half bridge power stage with 4x paralleled GaN 650V/160A HEMTs was designed and validated by experimental test GaN Systems 10

11 Contents Paralleling design considerations Layout considerations for paralleling GaN Design example of 4x paralleled GaN power stage Experimental results GaN Systems 11

12 Key layout parasitics Gate Drivers GaN Enhancement-mode HEMT Half Bridge Critical parasitic parameters that have high impact on GaN paralleling: C4 C5 L DR5 L DR7 L DR1 C2 C3 L DR3 L DR6 L DR8 L DR2 L DR4 L G3 R G3 L S3 L G1 R G1 L S1 R S3 R S1 Q3 Q1 L D3 L CS3 L D1 L CS1 L G4 R G4 L S4 L G2 R G2 L S2 R S4 R S2 L D4 Q4... L CS4 L D2 Q2... L CS2 L P1 L P2 C DC L G1-4 & L S1-4 : gate/source inductance Unbalanced L G /L S increases the gate ringing and risk of oscillation Equalize L G /L S using star connection and keep as low as possible Individual R G /R S is recommended to reduce gate ringing among paralleled devices L CS1-4 : Common source inductance Defined as any inductance that couples power loop switching noise (Ldi/dt) into the gate drive circuit Including the shared/common source inductance and mutual inductance between power and drive loops Feedback switching di/dt to V GS, impact gate drive stability and performance Minimize as much as possible. GaN Systems 12

13 Gate drive design for paralleled GaN For high current paralleling design, a small negative gate drive turn-off bias is recommended for lower turn-off loss and more robust gate drive. Recommend to use -3V to -5V with synchronous driving for optimum efficiency. Create bipolar gate drive from single power supply using a 6.2V Zener. Negative gate drive bias (VEE) is defined by PS1 output Vzener(6V) Use small values (1-2Ω) for distributed gate and source resistance: R3/R5 and R6/R7 Total turn-on R G_ON = R4 + R3(R5) +R6(R7). Turn off R G_OFF = R3(R5) + R6 (R7) VCC 0V C1 4.7uF C PS1 VIN ISO DC/DC GND 8 NC +VO 5 0V 4 R1 2.2K R0805 C3 4.7uF C0805 R2 1K D1 ZENER 6.2V C2 4.7u C4 4.7u VDD GD_GND VEE DRAIN PWM_IN VCC C6 0.1uF U1 VI VDD 8 7 VDDI VO+ 6 GNDI VO- EN GNDA 5 SI8271GB-IS VDD C5 1uF C7 1uF GND_GD R4 4.7 GND_GD R8 4.7K R3 1R R6 1R Q1 GS66516T R5 1R R7 1R Q2 GS66516T 0V VEE EN ISOLATION GD_GND SOURCE GaN Systems 13

14 Flux cancelling for lower inductance When two adjacent conductors are located close with opposite current direction, magnetic flux generated by two current flows will cancel each other in the region highlighted. This magnetic flux canceling effect can lower the parasitic inductance. Arrange the layout so that high-frequency current flows in opposite direction on two adjacent PCB layers GaN Systems 14

15 Flux Cancelling Design for half bridge layout S D S D Top Layer Side View Bus- Bus+ Bottom Layer D S D S high di/dt BUS+ BUS- Commutation Loop High Frequency Current alternates direction on Each Layer to provide flux canceling effect Top Layer: place GaN HEMTs Mid_L1: BUS+ -> Drain_High ; Source_Low -> BUS- Mid_L2: Source_High -> Drain_Low Mid_L3: BUS+ -> Drain_High ; Source_Low -> BUS- Mid_L4: Source_High -> Drain_Low Bottom Layer: place Gate Driver Circuit and Decoupling Caps GaN Systems 15

16 Comparison with Benchmark Gate Drivers C4 C5 L DR5 L DR6 GaN Enhancement-mode HEMT Half Bridge L G3 R G3 Q3 L D3 Commutation Loop L G4 R G4 Q4 L D4... L P1 GaN Systems Solution: only 25% L Loop of the Best Counterparts: Low inductance GaNPX package Flux cancelling PCB design L DR7 L DR8 L S3 R S3 L CS3 L S4 R S4 L CS4 C2 C3 L DR1 L DR2 L G1 R G1 Q1 L D1 L G2 R G2 Q2 L D2... C DC State-of-Arts Emode GaN HEMTs Power Module [1] L DR3 L DR4 L S1 R S1 L CS1 L S2 R S2 L CS2 0.7nH L P2 [1] F.Luo, Z.Chen, L.Xue, P.Mattavelli, D.Boroyevich, B.Hughes, Design Considerations for GaN HEMT Multichip Half- bridge Module for High-Frequency Power Converters GaN Systems 16

17 Contents Paralleling design considerations Layout considerations for paralleling GaN Design example of 4x paralleled GaN power stage Experimental results GaN Systems 17

18 4x GS66516T Paralleling Test Board Top View 650V/240A high Power stage design using discrete GaN EHEMTs DC Bus Capacitor Low Side GaN E-HEMTs 4cm 3cm High Side GaN E-HEMTs GaN Systems 18

19 4x GS66516T Paralleling Test Board Bottom View Low Side Gate Driver Decoupling Capacitors High Side Gate Driver GaN Systems 19

20 Layout of 4x paralleled GaN power stage Un-plated holes, for thermal measurement. Avoid routing electrical signals under the device. Higher HEMTs Bus+ Bus- Top Layer Lower HEMTs Bus+ Mid_L1 Bus- Bus- Bus+ Source_High-> Drain_Low Mid_L2 Gate Driver Gate Driver Bus- Bus+ Bus- Bus+ Source_High-> Drain_Low Bus+ Decoupling Capacitors Bus- Mid_L3 Mid_L4 Bottom Layer GaN Systems 20

21 Optimum Paralleling Layout for GaN HEMT (4x GS66516T) Top side with 4x GS66516T in half bridge BUS+ HV decoupling Cap Bot side with gate driver Note symmetric gate drive layout: - Utilize the dual gate on GS66516T GaNPx - Gate resistor on each gate Gate driver Gate driver Gate driver BUS- DC Link Cap Un-plated holes, for thermal measurement. Avoid routing electrical signals under the device. GaN Systems 21

22 Contents Paralleling design considerations Layout considerations for paralleling GaN Design example of 4x paralleled GaN power stage Experimental results GaN Systems 22

23 400V/240A double pulse hard Switching test waveforms DUT: 4x GS66516T in parallel; Freewheeling: 4x GS66516T in parallel Condition: V BUS =400V, I DS_ON =231A, I DS_OFF =240A, V GS =+6.8V/-5V, R G_ON =4.55ohm, R G_OFF =1.25 ohm. Freewheeling i L (C2:100A/div) V GS =-5V il(c2) L=50uH Vds_DUT(C1:100V/div) Hard switching on/off Vspike=52V Double Pulse DUT Vds_DUT(C1) On: dv/dt=19.5v/ns i OFF =240A Off: dv/dt=59.6v/ns Measurement Setup: Lecroy WaveSurfer 10M Oscilloscope, HVD3106 Differential Probe(C1), CWT-3LFB mini Rogowski Coil(C2) Experimental Waveform No-Derating Paralleling of GaN HEMTs. Hard switched up to full rated current with clean waveform. 400V/240A Hard Switching Capability with ~200V V DS Margin GaN Systems 23

24 Summary Paralleling discrete GaN is desired to achieve higher power output GaN Systems E-HEMT device characteristics are inherently fit for paralleling: Positive R DS(ON) temperature coefficient Stable gate threshold over the temperature range Negative tempco of g m Low inductance GaNPX package for minimum circuit mismatch Layout is critical for paralleling high speed GaN HEMT: Low and balanced parasitic inductance on the power and gate drive loop. Equal length of gate drive layout and optimum gate driver circuit Summary Provided practical design guide on how to parallel high speed GaN HEMT devices Showed a design layout example of 4x paralleled GaN E-HEMT half bridge power stage Hardware was built and GaN E-HEMT paralleled operation has been validated up to the rated current under hard switching test (400V/240A) GaN Systems 24