Marcel Jacomet. Electrical Engineering Department, Circuit Design Laboratory Swiss Federal Institute of Technology (ETH) CH-8092 Zurich, Switzerland

Transcription

1 FANTESTIC: Towards a Powerful Fault Analysis and Pattern Generator for Integrated Circuits Marcel Jacomet Electrical Engineering Department, Circuit Design Laboratory Swiss Federal Institute of Technology (ETH) CH-8092 Zurich, Switzerland Test Abstract According to statistical models characterizing the likelihood of physical defects inherent to the fabrication process, an algebraic approach to extract the possible defects from the specific circuit layout is proposed. Depending on their effects to the electric properties of the circuit, the physical defects are transformed into electrical faults and ranked according to their likelihood of occurrence. The analysis of some sample CMOS circuits illustrate the effect of different physical defects to circuit level faults. Based on these realistic faults, effective test patterns can be generated. 1 Introduction The progressing miniaturization capability leads to the possibility to integrate more and more complex systems on one chip. Nowadays, such very large scale integrated (VLSI) circuits consist of to 1 million transistors in one single chip. Due to such high integration densities not only the circuits functionality, but also the difficulty to test the circuit itself are augmented. Both test generation and test evaluation have become very complex, time consuming and therefore very costly. firthermore, the applicability of the stuck-at fault models has been highly disputed, and thus the effectiveness of the test pattern generation methods based on them is unclear. Most of todays existing test tools have originally been developed for TTL chips or printed circuit boards containing TTL logic. Physical or chemical mechanisms which cause faults on printed circuit boards or on TTL chips can be quite different to the ones of MOS or CMOS circuits. It is evident that an effective test synthesis for VLSI circuits has to take into account process technology dependent defect mechanisms. Consequently, fault models must be based on physical defects caused by process instabilities, contamination, and lithography imperfections occurring during the chip fabrication process. Classical approaches to test pattern generation for logical faults have assumed that physical defects can be modeled as lines in the gate level representation stuck at a specific logic value. More refined fault models like the switch level model 111 were introduced to improve the accuracy of the translation of physical defects into electrical faults. Both of these approaches are based on a gate level or a transistor level circuit description to generate a fault list. They have no relation to the geometric circuit layout which strongly influences yield and the generation of electrical faults. 2 The FANTESTIC Concept The modern trend is to design large systems and to implement them as VLSI circuits. For the successful design, integration and test of such highly complex systems, structured design and test methods have to be applied. A widely popular design concept is illustrated in Fig. l which is supported by appropriate CAD tools. The numerous design environments do not differ in their method but in the abstraction level of the CAD tools themselves. They consist of four phases, starting from the system development which is followed by the logic design. In the third phase the test pattern generation is performed, which relies on the logic circuit and which is independent of the layout. The layout design and verification is usually accomplished simultaneously to the test synthesis sometimes even by different design engineers. The described conventional design and test method CH2742-5/0000/0633$01.OO IEEE 1989 International Test Conference 633

2 specification logic implementation floor-planing Q System Design G Logic Design specification system design system simulation logic design logic simulation testability analysis floor-planing layout generation layout verification Figure 1: Conventional design and test method for VLSI circuits. Layout design and test pattern generation are usually developed in parallel. for integrated digital circuits prevents from the development of a powerful test synthesis with a high fault coverage. The main reason can be found in the absence of an informative fault analysis. By a basic change of the conventional design and test method and an expansion of the test phase itself, the preconditions for a more effective fabrication test synthesis can be reached. In contrast to conventional design and test methods, a strict hierarchical course of the different design phases has to be followed. Figure 2 illustrates the embedding of a Fault ANalysis and TEST pattern generation of Integrated Circuits concept (FANTESTIC concept) into the design and test cycle of VLSI circuits. Shown in Fig. 2, the test synthesis phase in particular does not run any more in parallel with the layout generation but proceeds sequentially and relies on a newly inserted fault analysis phase which is based on the layout. Thus the circuit layout does not only contain the structure of geometrical patterns for the chip fabrication, but also furnishes the basic information for the fault analysis phase which strongly influences test pattern generation. In the FANTESTIC concept, the fault analysis phase is based on the circuits layout, on physical defect models, and on technology specific parameters. Four main steps can be distinguished at the fault analysis phase: 0 Extraction of possible physical defects based on the circuit layout (technology dependent). 0 Physical defects to electrical fault transformation (technology dependent). defect extraction fault analysis fault classification test pattern generation fault simulation Figure 2: The impact of the FANTESTIC test concept on the VLSI chip design procedure. Algebraic approach to calculate the likelihood of the occurrence of each fault (technology independent). Supply of statistical data on the impact of different mask dependent spot defects and pinholes on faults. The fault analysis step furnishes a list of faults extracted from the layout and ranked according to their likelihood of occurrence which fulfills the requirements of a test pattern generator to produce a powerful test set. 2.1 Physical Defects in CMOS Fabrication Processes The amount of knowledge of physical, optical, or chemical mechanisms which reflect in deviations of the expected properties of the electrical behavior of the integrated circuit is responsible for the success to reveal the defects. Relying on this knowledge, it is possible to predict yield and testability, as well as to develop 634

3 effective test generation procedures. During the complex process steps for the fabrication of integrated circuits, there exist numerous factors causing physical defects leading to faulty circuits. How these weaknesses and lack of perfection arise and how they influence the circuit behavior mainly depends on the applied fabrication process and the circuits layout topology. For a few fabrication processes the literature describes causes of defects during different process steps. These defects can be classified into two groups: 0 electrical parameter shifts 0 topology deformations Defects causing electrical parameter shifts (like variations of threshold voltages etc.) usually affect larger chip areas. They can be detected by the measurement of parameters of special test circuits in between the chips on the wafer. The second group causing topological layer deformations can be divided into defects affecting large areas (global) and pinhole, point, or spot defects which have local effects. Global topology deformations, such as scratches, photolithography misalignments, line registration errors or other serious fabrication process control errors cause simultaneous numerous faults which are usually easy to detect. The most difficult defects to detect are the local topology deformations, because they are randomly distributed over the hole chip area and because their effect on the circuits behavior is usually limited to a local failure source. This paper will focus on these local topology deformations, which are mainly responsible for the high test costs due to their local and random character. The source of these local topology deformations are manifold and partially can be classified into the following categories: local surface contamination: it can lead to corrosion and parameter shifts with time dependent mechanisms. substrate inhomogeneities: caused by impurities or local inhomogeneities in the silicon substrate crystal lattice behaves like recombination or generation centers for electrons or holes. photolithography defects: dirt and dust particles can cause opaque or transparent spots on the lithography mask, which lead to additional or missing layers on the wafer. oxide defects: contamination in the field or gate oxide can cause pinholes in the isolation layers. metallization problems: electron dislocation or electro-chemical corrosion can cause defects in the metallization layer. A lot of other defects can be observed, like parameter shifts due to hot electrons, problems due to alpha particles of the package etc. The origin of defects from each of these categories involves complicated processes which sometimes are unknown. Despite the lack of basic physical or chemical knowledge which lead to all of these defects, some experimental results are available and used in this paper. 2.2 Statistical Modeling of Physical Defects In this paper) the statistical modeling of the likelihood of occurrence of physical defects will be restricted to the local topology category. The applied models have been proposed by Stapper [2,3] and are successfully used and further developed by various researchers [4,5,6]. Two basic models are distincted. The first one describes the probability of oxide defects in transistor channels and insulation layers. The second model depicts the calculation about the likelihood of photolit hography defects Modeling of Oxide Defects Defects which occur in dielectric insulation materials between different conducting layers possess very small dimensions (pinholes) compared to the geometrical layout structures. Pinholes only can induce electrical shorts where conductors of different layers cross each other or in the thin oxide of transistor channels. Thus the average number of faults X is sensitive to the overlapping area of the two involved conductors. For this reason Stapper postulated the average number of faults to be: Xozzde = A ' D oride (1) where A represents the overlapping or defect-sensitive area, and D the average defect density Modeling of Photolithography Related Defects Geometrical patterns on the substrate surface consisting of metal, poly-silicon, dielectric, and diffusion, are used for the creation of transistors, interconnections, capacitances etc. Nowadays the minimal dimensions of such patterns are only a few microns down to one micron or even less. Dirt and dust particles of similar 635

4 f I-- f Is I., Figure 3: Long conductors running in parallel are interrupted by spot defects. Spot defects causing multiple conductor interruptions are divided into multiple interruptions of single conductors. dimensions entail horizontal defects during the photolithography pattern projections to the wafer. The particles location on the masks or the wafer as well as the particles size determine the effects on the electrical behavior of the integrated circuit. The physical effects of photolithography defects can be divided into two groups: they can lead to missing layer material or can produce undesirable additional material on the chip. These photolithography related defects, which belong to the category of local topology deformations, are often called spot or point defects. They can be modeled as circles with a variable diameter 5. The defect size distribution function of spot defects used in this paper was earlier developed by Stapper [2,3] by analyzing a number of experiments: The average number of faults (produced at a layer creation process defined by mask m) can easily be calculated by the integral of the defect density function multiplied by the sensitive area. Figure 3 illustrates the calculation of the defect sensitive area marked by two dotted lines of one interrupted interconnection layer with width w. An integrated circuit layout does not only consist of one single interconnection layer but of numerous interconnections. There will be spot defects causing multiple open interconnections. Assume that many long interconnection layers ly in parallel consisting all of the same widths w and having the same space s between each other (see Fig. 3), the average number of broken interconnections can be calculated. The contribution of multiple m open faults are separated into m parts and added to the probabilities of the concerned single open interconnection faults. As it will be shown later, this simplification is justified. Thus the total average number of opens for 71 interconnection layers is n times the average nuniber for an interruption of one single interconnection Xant. Xint - = D,lz;, s[a+l]+w[2+2] +J sl+w[a+ 11 (s[i U[, + 2) - s) In the above equation there are the two constants om, and so and the three variables length I and width w of the interconnection layer as well as the space s between them. These three variables can easily be extracted from the circuit layout. As it is shown for the interruption of layers (interruption in conductors or transistor channels), similar formulas can he developed for critical horizontal cover in one layer (shorts between equal conductors), for critical vertical cover of two different layers (shorts between different conductors), or critical overlapping of an underlying layer (interruption of contacts or transistor channels). The spot defects are called critical when they induce an electrical fault Single Faults Versus Multiple Faults Fixing the miniiiial width w for conductors, the previously introduced variable U can be interpreted as 636

5 a measure of the layout density. In the investigated CMOS process, all minimal dimensions are 3pm, whereby v = 1 represents the highest possible layout density. The ratio of single faults (SF) to the sum of single and multiple faults (MF) for interruptions can be deduced from equation 2: >&, TechdqY Description electrical components - / defect models circuit extractor I Pr {SF I SF U M F} = 2. ant With v 2 1 it follows that the percentage of single faults will always be between 80% and 100%. The same result can also be obtained by considering all defect types together. Consequently defects causing multiple faults will always remain a small fractional part of the total number of faults. 3 The FANTESTIC Implementation The algebraic fault analysis therefore bases on the extraction of individual physical layout structures of integrated digital circuits. The applied analysis is a commonly usable procedure for many different fabrication processes. Changing to comparable technologies, the characterization of the physical defects to the new technology have to be adjusted. The extraction of physical defects, its transformation into electrical faults, and the algebraic calculation of their probabilities will be performed fully automaticly by a software module of the FANTESTIC tool package. Figure 4 illustrates the implementation of the FAN- TESTIC concept, which consists of the algebraic fault analysis module and the test synthesis module which is currently under development. As it can be seen in Fig. 4, the input data for the algebraic fault analysis phase is furnished by a conventional circuit extractor*, which can easily be customized for the extraction of local topology defects for any fabrication process. The circuit extractor concurrently extracts information both for local topology defect modeling and the circuit netlist on transistor level, which can also be used for design validation. These two data files are the basis for the algebraic fault analysis module. In a parsing step, local topology defects are extracted out of the furnished information from the circuit extractor. These defects subsequently are mapped into primary electrical faults, like bridges between connectors etc. The following transformation step of primary faults 'The IC design group of our laboratory uses the design software which was developed by Philips. Thus the applied circuit extractor is LOCAL [7) from this IC design package. (transistor netlist) (primary data) i Algebraic Fault Analysis. parser primary-fault extractor transformation to circuit faults - statistical fault analysis Circuit Structure -transistor netlist - ranked list - defect sources Generation - logic faults Figure 4: The relationship between the data and the two software modules, algebraic fault analysis and test pattern generation of the FANTESTIC concept. into circuit faults, like stuck-at or bridging faults is a very tedious task. Using the earlier described physical defect models, a statistical analysis of the origin of the faults, their likelihood of occurrence, as well as their probability distribution can now be performed. The resulting output of the algebraic fault analysis phase are: e e The development of a logic level circuit description starting from the transistor level netlist. A list of circuit faults ranked according to their probabilities. The faults are classified according to their electrical effects. A statistical analysis of failure sources, a fault distribution and the electrical fault manifestations, illustrated graphically. 637

6 This realistic faults, extracted from the individual circuit layout, will then be used as a basis to generate an effective set of test patterns. 3.1 Extraction of Local Topology Defects A self-aligned single metal layer p-well CMOS fabrication technology** has been chosen as an example to obtain initial results with the FANTESTIC concept. The design rules of this CMOS process lead to 36 mask combinations which can be grouped into 21 different electrical function classes (e.g. nmos transistor, metal layer, n-diffusion contact, p-well contact etc.) needed to built digital logic. A physical defect will cause an electrical fault if it manifests itself as a shift from one electrical function class into another. A careful analysis of all possible shifts leads to a technology-dependent defect-to-fault transformation function. As an example the missing interconnection (for instance a poly-silicon layer) due to a spot defect illustrated in Fig. 3 represents a shift from the electrical function class of poly-conductor t to the electrical no-function tt class. This interruption defect has now to be mapped into an electrical primary fault. 3.2 Mapping of Local Topology Defects into Primary Faults After the extraction of all potential local topology defects from the circuit layout, they are mapped into electrical primary-faults. These primary faults are a set of all basic electrical faults, with which all failures of digital circuits can be described on a transistor level. The set of these primary faults only consists of four elements: the bridge between two conductors (zeroresistance) the resistive bridge between two conductors the interruption of a conductor, transistor terminal, or channel the creation of a new transistor device For the definition of these primary faults some simplifications have to be made. For instance, bridging "3pm SACMOS process with 8 masks described in [E]. t The mask combination m.ps.m represents the electrical function class of poly-conductors. ttthe electrical no-function class is defined as the mask cornbination of =. (OD + SP. SN + -. m). faults caused by physical defects may have different conductivities. In the present SACMOS process technology [8], the resistance for metal conductors is typically 25mR/O. For poly-silicon these value is 30R/o and for n and p diffusions the conductivity is 55R/o and 200R/O, respectively. In digital applications transistors normally operate as switches. Thus in the case of a bridging fault the short resistance can be compared to a transistors on-resistance, which is one or two decades higher. In the 3pm SACMOS technology a 6pm wide Ti-channel and a 9pm p-channel transistor possess an on-resistance of 3.7KR/O and 5.9KR/o respectively. Thus, the resistance of a bridging fault between two conductors can be neglected compared with the on-resistance of a transistor. Therefore it is quite realistic to distinguish between two types of bridging faults, the zero-resistance and the resistive bridging fault. 3.3 Transformation of Primary Faults into Circuit Faults The layout-dependent primary faults have to be transformed into circuit faults. Depending on their site in the circuit, primary faults of the same type may induce an equal or a different faulty behavior of the digital circuit. Basically, the implemented primary to circuit fault transformation procedure attempts to get faults on the logic level, or at least, easy to handle faults at the transistor level. Principally, electrical effects of faults in digital circuits can be classified in three categories. 0 logic manifestation static current increase delay time increase, and 0 discharge of dynamic nodes Numerous faults show a faulty circuit behavior, which may manifest itself in more than one of the above categories. In the current FANTESTIC implementation, all primary faults with an observable logic malfunction will be transformed into a logic fault. Bridging faults, which definitely result into an undefined logic output value, will be described by a static current increase fault. Pure delay time increase and discharge faults are not considered up to know in our fault transformation procedure. Depending on its geometrical and electrical location the transformation of an interruption defect into a circuit fault can either be a conventional stuck-at fault or 638

7 2.2% defect layers standard cell design opens shorts r-shorts device total pinhole (field) 1.0% 1.O% pinhole (gate) 11.1% 11.1% missing IN missing CO niissing CE missing PS iiiissing OD missing SP missing SN 25.2% 1.0% 21.9% 1.4% 0.3% 1.8% 25.2% 1.O% 23.7% 1.4% 0.3% extra IN extra CO extra PS 0.9% 13.1% 2.5% 15.2% 13.1% 2.5% 16.0% extra OD 0.5% 1.0% 1.5% extra SP extra SN 0.3% 0.3% extra DP 2.2% ~ total I 51.6% 32.3% 15.1% 1.0% I 10 gate array design opens shorts r-shorts device 0.9% 8.5% 44.0% 0.4% 21.7% 1.4% 0.1% 1 2.4% 0.4% 7.8% 0.4% 0.1% 1.7% 66.9% 21.5% 11.6% total 0.9% 8.5% 44.0% 0.4% 23.1% 0.1% 1 2.4% 8.2% 0.4% 0.1% 1.7% 10 Table 1: The contribution of pinholes and layer defects to the weighted primary electrical faults of opens, shorts, resistive short and extru device faults measured with a standard cell and gate array design implementation are illustrated, assuming to be equal for each defect type. The abbreviations for masks in this table are as follows: metal interconnection (IN), contact oxide window (CO), contact extended to poly-silicon (CE), poly-silicon (PS), open for diffusion (OD), shallow n-type or p-type diffusion (SN,SP), deep p-type diffusion (DP). a fault turning a combinatorial circuit into a sequential behavior mode. If an open fault does not interrupt the logic output from the supply lead (open opl in Fig. 6) then a combinatorial circuit will be turned into a sequential one, otherwise the open can be modeled as a stuck-at fault (open opz in Fig. 6). The probabilities of all physical defects causing the same electrical fault will be accumulated and assigned to the appropriate fault which is then called weighted fault. 4 Experimental Results Preliminary experimental results obtained with a small digital interface circuit (900 transistors) implemented in both standard cell design and gate array technology with the same design rules (3pm) are illustrated in Table 1. The table shows the contribution of pinholes and spot defects to different electrical fault classes. Measuring the time used to extract defects, to convert them into faults and to rank them according to their probabilities in a list, it can be seen that the proposed FANTESTIC concept is quite fast (43 seconds on a VAX 8600 computer after having extracted the circuit layout for the mentioned standard cell interface circuit example of 900 transistors). It is interesting to see that the ratio of open to short faults varies in the two different implementations of the circuit. From Table 1, it can be observed that in the gate array implementation the ratio of open to short faults is as high as 2.0 to 1 whereas for the standard cell (sc) implementation this ratio is only 0.9 to 1. This observation can be explained by the lower layout densities of gate array (ga) implementations (uga < use) due to many unused vias and due to the fixed channel widths, which can never be used optimally in contrast to the variable channel widths in standard cell designs. The analysis in Fig. 5 represents the weighted faults as a function of the number of faults in a ranked fault list starting with the most likely faults. The gate array implementation needs four times as much silicon area as its corresponding standard cell design and the probability of causing a fault is 2.5 times higher. Table 2 shows the percentage of primary faults which can be mapped into the classical stuck-at fault model. The table illustrates results obtained by the two interface circuits (900 transistors) mentioned above and a programmable test controller circuit (8400 transistors) implemented in gate array technology [9]. For the respective primary to circuit fault transformation, it is assumed that an open of a transistor gate terminal can be modeled as a stuck-at-0 as well as a stuck-at-1 fault, due to the relatively large hold time of the gate capacitances. Even with this simplifica- 639

8 primary faults standard cell gate array (900 FET s) circuit faults opens shorts r-shorts total opens shorts r-shorts total stuck-at 42.3% 4.8% 47.1% 42.8% 3.0% 45.8% sequential 9.3% 9.3% 24.1% 24.1% LLSS & CLSS 22.5% 15.1% 32.2% 18.5% 11.6% 30.1% total 51.5% 32.3% 15.1% 99.0% 66.9% 21.5% 11.6% 10 gate array (8400 FET s) opens shorts r-shorts total 39.5% 3.9% 43.4% % 11.1% 36.6% 59.5% 29.4% 11.1% 10 Table 2: By the transformation of primary faults to circuit faults the contribution of each fault class to the total number of weighted faults can be shown. The fault contribution of conventional stuck-at fa,ults and logic faults requiring an initialization previous to the applying of the test patterns (combinational circuit turns to a sequential one at the presence of a fault) as well as the new large-scope short faults (LLSS and CLSS) are illustrated for a 900 transistor standard cell and gate array design example of the interface circuit as well as for a 8400 transistor gate array implementation of a programmable test controller. density distribution - 100% open faults tuning the circuit into a sequential mode is twice as high as in the two gate array implenientations than in the standard cell design. - 80% - 60% 5 Towards Test Pattern Generation relative number of faults - 40% Figure 5: Density and distribution of weighted faults as a function of the number of faults ranked in a decreasing order of their likelihood. In order to get 90% of the weighted faults only 54% of the extracted faults have to be considered for test pattern generation. tion, the classical stuck-at fault models cover less than 50% of the weighted faults. Some open faults turn a combinatorial circuit into a sequential one (see section 3.3). A small portion of the bridging faults can also be mapped into stuck-at faults, if a logic output node is shorted to a supply line. The remaining bridging faults can be mapped in the new large-scope short fault model introduced later in section 5.1. The analysis of the three circuits shows another interesting tendency. Looking at Table 2, it is evident that the percentage of faults which can be represented by the classic stuck-at fault model remains almost constant for all circuits. In contrast, the percentage of The last step in order to get a powerful test pattern set consists of the extraction of a compressed set of the most likely faults. As it can be seen from the experimental results in Fig. 5, not every extracted fault has to be processed further. In both interface circuits only approximately 69% of all faults have to be considered in order to achieve a fault coverage of approximately 95% of all weighted faults. There are even only 54% of faults to be further processed by test pattern generation tools in order to get a 90% fault coverage. 5.1 A New Large-Scope Short Fault Model The experimental results in Table 2 and previous research projects reported in the literature provide examples which demonstrate the inadequacy of classical stuck-at models and the technology dependency of fault models. In the literature [10,11,12,13], several models have been proposed to describe the unintentional connection between two nodes. This interest in bridging fault models stems from the frequent occurrences of interconnection shorts and its difficulty to model them. The bridging fault may be considered as a logical fault within the circuit which may change the logic value on a node between two discrete steps ( U and l ), or as an electrical fault which changes voltage (between OV and 5V) or current in a given interval. Due to the FANTESTIC concept, more information 640

9 a3 = 0 a2 = 0 a1 4 = 0 IKss = 2.8v 3 faulty output do = 0 Figure 6: By an example circuit, the transformation of a bridging fault to a logic large-scope short is illustrated. The faulty logic value 0 can be observed at the output of circuit D. Circuit C has an undefined logic output value, due to a to small large-scope short voltage difference AVc.lss = 0.3V 5 A&,,,. can be extracted from the circuit layout than existing bridging fault models are based on. The difference between existing bridging fault models in the literature steam from their different scope. The scope of a fault model defines both the expansion of a fault within the circuit and the amount of circuit and layout information which is used to determine the faulty behavior. For instance, no circuit information is necessary to determine that a stuck-at fault fixes a node to a particular value. By nature, bridging faults must have a greater scope than one node. The wiredlogic niodels for bridging faults determine the logic value on both nodes depending on the logic output values of the individual elements driving the bridging faults. The scope of these models is the two outputs driving the short circuit node. The new bridging fault model has a much larger scope, so it will be called large-scope short or LSS fault. Depending on differences in driving capabilities of the involved transistors and individual input voltage threshold levels of the succeeding gates, it will be determined whether a bridging fault can be modeled as a logical (LLSS) or current increase (CLSS) large-scope short. The following steps describe the derivation of a large-scope short out of a bridging fault, with an example circuit illustrated in Fig. 6: 1. A set of input vectors for the first logic stage (Block A and B) have to be selected in order to get inverse logic values at the outputs given a fault free circuit. 2. With the derived input vectors, the minimal and maximal short-circuit output voltages have to be calculated or simulated using about two or three iteration steps to get an accurate voltage value. These two values are called minimal and maximal large-scope short voltage levels (Kss). 3. The minimal and maximal logic input threshold voltages of the succeeding second stage circuits (circuit C and D) have to be derived (&h,~ and vi h, D ) * 4. One of these short-circuit voltages (xss) and one of the logic input threshold voltages from circuit C and D have to be selected, such that the voltage differences A&,, = IQ, - Vthl can be maximized. This voltage difference is defined as the large-scope short voltage difference. 5. If the large-scope short voltage difference AVi,, exceeds a minimal value AKlss (for example 0.75V), then there is a logic large-scope short (LLSS) with a valid logic value, else the voltage takes an unknown intermediate logic value and ihe fault is called a current large-scope short (CLSS). 6. If only a current large-scope short can be obtained, then the input values of the two shorted logic blocks have to be selected, such that the short-circuit path between Vdd and v,, shows a maximal fault current. A similar approach has to be performed for bridging faults within a logic circuit block. Logic lkqe-scope shorts can be detected at the logic level by applying appropriate logic values at the inputs of the shorted and the succeeding logic blocks to get the rnmimal large-scope short voltage difference Ax,,. The det ection of current large-scope shorts can be achieved by observing the increased current consumption, while the logic block input values are chosen to achieve a maximal fault current. As an example the bridging fault in circuit Fig. 6 can be transformed into a logic large-scope short 1 value for circuit D ( AVc,lss = 1.1V) with a faulty logic value 1 with the input vectors va = (O,O,o), Vb = (1) and 641

10 Vd = (Kss,O). Because AVD,~~~ = 0.3V is smaller than the LLSS voltage difference SKlss = 0.75V the bridging fault cannot be transformed into a logic largescope fault for circuit C. Due to a normally increased delay time for bridging faults, before applying the test vector the shorted node must first be initialized to the LLSS fault value. 5.2 Fault Classification The test synthesis module of the FANTESTIC concept will be based on the following three fault models: 0 conventional stuck-at fault model 0 extended stuck-at faults, requiring initialization (sequential) 0 new logic and current large-scope short fault model Faults causing an extra device are very rare (see Table l) and thus will not be considered for the test pattern generation procedure. According to these classifications, suitable algorithmic approaches are going to be implemented in a next step using some basic theorems for CMOS testing formulated in [14]. 6 Conclusions A methodology relating physical defects to the circuit level faulty behavior caused by these defects and a fast algebraic implementation to provide a realistic fault list is proposed. In conjunction with the obtained statistical data on the likelihood of each fault and the knowledge of its best observable electrical manifestation, a solid basis for an effective and powerful test pattern generation is provided. To achieve an accurate modeling of bridging faults, a new fault model, the large-scope short is developed and implemented. In contrast to other fault analysis procedures which use time consuming simulation methods to generate or induce physical defects [4,15], the proposed FANTES- TIC methodology is very fast in extracting defects and converting them to a ranked fault list. Using the implemented fault analysis further investigations concerning the design robustness in respect to fabrication defects may furnish interesting results about the layout design quality. This results could be used to change the layout implementation rules (e.g. modifying the ratio of conductor width to the space between conductors) in such a way as to raise the yield. References (11 John P. Hayes. An introduction to switch-level modeling. IEEE Design & Test, 18-24, August [2] C. H. Stapper. Modeling of integrated circuit defect sensitivities. IBM Journal of Research and Development, Vol. 27: , November [3] C. H. Stapper. Modeling of defects in integrated circuit photolithographic patterns. IBM Journal of Research and Development, Vol. 28: , July [4] Hank Walker and Stephen W. Director. VLASIC: a catastrophic fault yield simulator for integrated circuits. IEEE Transactions on Computer- Aided Design, CAD- 5: , October [5] Wojcech Maly. Modeling of lithography related yield losses for CAD of VLSI circuits. IEEE Transactions on Computer-Aided Design, Vol. CAD-4: , July [6] C. H. Stapper. Correlation analysis of particles of integrated circuit. IBM Journal of Research and Development, vol. 31: , November [7] H. van der Gaag, L. Th. G. Simons, and J. G. R. Okel. LOCAL45. Philips Research Laboratories, Eindhoven, December [8] R. Luescher and J. Solo de Zaldivar. A high density CMOS process. In IEEE Int. Solid-state Circuits Conf., pages , [9] M. Jacomet. MC103 - Kaskadierbarer und Programmierbarer 16-Bit CMOS Test Kontroller. Technical Report IFE-88/2, Swiss Federal Institute of Technology, Electronics Laboratory, March (101 Kenyon C. Y. Mei. Bridging and stuck-at faults. IEEE Transactions on Computers, C-23, No. 7: , July [ll] R. L. Wadsack. Fault modeling and logic siniulation of CMOS and MOS circuits. Bell System Technical Journal, , May - June [12] J. A. Abraham and P. Banerjee. Characterization and testing of physical failures in MOS logic circuits. IEEE Design 9 Test, 76, August [13] John Michael Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Computer Systems Laboratory, October [14] Daniel Baschiera. Mode'lisation de Pannes et Me'thodes de Test de Circuits Inte'gre' CMOS. PhD thesis, Institut national polytechnique de Grenoble, [15] F. Joel Ferguson and John P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on Computer-Aided Deaign, , November