Citation for published version (APA): Maddalena, F. (2011). Organic field-effect transistors for sensing applications Groningen: s.n.

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1 University of Groningen Organic field-effect transistors for sensing applications Maddalena, Francesco IMPORTANT NOTE: You are advised to consult the publisher's version (publisher's PDF) if you wish to cite from it. Please check the document version below. Document Version Publisher's PDF, also known as Version of record Publication date: 2011 Link to publication in University of Groningen/UMCG research database Citation for published version (APA): Maddalena, F. (2011). Organic field-effect transistors for sensing applications Groningen: s.n. Copyright Other than for strictly personal use, it is not permitted to download or to forward/distribute the text or part of it without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license (like Creative Commons). Take-down policy If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Downloaded from the University of Groningen/UMCG research database (Pure): For technical reasons the number of authors shown on this cover page is limited to 10 maximum. Download date:

2 CHAPTER 3 Chapter 3 Device Characteristics of Dual-Gate Field-Effect Transistors Abstract Dual-gate organic field-effect transistors (DG-OFETs) were fabricated by solution processing using different p-type polymer semiconductors and polymer top-dielectric. The DG-OFETs were characterized by sweeping the bottom gate bias while fixing the top gate potential, and vice versa. We demonstrate that the change in the threshold voltage of the bottom gate depends on the top gate bias with two linear relationships for two different regimes. The transition regime between both linear regimes is marked by a drop in the transconductance. The transition regime results from the fact that the charges accumulated in the conduction channel of the sweeping gate will start screening the influence of the sweeping gate potential on the conduction channel of the fixed gate. * Part of this chapter was published as: F. Maddalena, M. Spijkman, J.J. Brondijk, P. Fonteijn, F. Brouwer, J. C. Hummelen, D. M. de Leeuw, P.W.M. Blom and B. de Boer, Organic Electronics 9, 839 (2008). 33

3 DEVICE CHARACTERISTICS OF DUAL-GATE FIELD-EFFECT TRANSISTORS 3.1 Introduction In recent years, the field of organic electronics has developed quickly and the behaviour of organic devices has been thoroughly studied mainly due to the discovery of novel polymeric materials. Especially solution-processable organic semiconductors with high mobilities and air-stability allow not only a better performance of OFETs but also the possibility of processing and operating allpolymer devices under ambient conditions [1, 2]. Different structures for OFETs have been proposed, such as vertical channel thin film transistors (TFT) [3], yet the standard planar structure has remained virtually unchanged and still is the most widely used device geometry. Planar OFETs can have either a top gate or bottom gate configuration, yet processing an OFET with both top and bottom gate present enables the study of a whole new device structure. Moreover, the dual gate OFET (DG-OFET) could further improve the performance of organic TFTs, without adding a significantly higher complexity to the processing of devices. One of the main bottlenecks for the practical applications of OFETs in the electronic industry is the instability of most organic semiconductors during operation under environmental conditions and the limited control of the electrical parameters of the device. A very important issue is the control of the threshold voltage (V TH ), which becomes crucial for proper operation, low power consumption and increasing the noise margin, especially in complicated organic circuitry. The first issue is often solved either by using an environmentally stable organic semiconductor [4, 5] or by coating the device with a passivating material. The second issue is often more difficult and can be achieved, to a limited extend, by modifying the surface of the dielectric with self-assembled monolayers [6]. A dualgate organic field-effect transistor (DG-OFET) solves both problems at once: the top insulator acts as a passivating layer by protecting the semiconductor from ambient, and the top gate can be used to accurately control the threshold voltage. The use of DG-OFET devices has already been exploited to significantly improve the noise margin in organic circuitry [7]. Furthermore, the DG-OFET has the potential to expand the possibilities of what has already been achieved and thoroughly studied with common organic TFT devices. 34

4 CHAPTER 3 Figure 1. Schematic structure of the dual-gate organic field-effect transistor. Dual-gate transistors, and even triple gate FETs, have already been researched extensively in the field of inorganic, e.g. silicon, electronics [8]. Modeling and analysis of organic dual-gate transistors however has only been recently developed [9, 10, 11, 12, 13], mostly on devices with evaporated pentacene as semiconductor rather than polymer semiconductors cast from solution. Recently, a linear dependence between the threshold voltage of the bottom channel, VTH, and the applied top gate (VG,Top) was proposed and observed, with the slope of the linear fit equal to the ratio between the capacitances of both dielectric layers [11]. In this work, DG-OFETs (Figure 1) processed from solution with p-type polymeric semiconductors and polymeric top dielectrics are investigated. We demonstrate that a single linear relationship between VTH and VG,Top is incomplete for a DG-OFET with both the top and bottom channels active, since the influence of the top gate potential on the bottom channel is screened by the charge carriers in the top channel and vice versa. Furthermore, the transfer characteristics of the DG-OFET will be discussed, where a transition region can be observed when both channels are in accumulation. 35

5 DEVICE CHARACTERISTICS OF DUAL-GATE FIELD-EFFECT TRANSISTORS 3.2 Results and Discussion The fundamental principles of the operation of the DG-OFET do not differ from that of a common organic TFT. In a single gate OFET the charges are induced at the semiconductor/insulator interface forming a conducting channel. The induced charges are mostly confined in the first 2-4 nm from the interface [14], hence the conduction is dominated by this thin channel rather than by the bulk. This implies that the two channels in DG-OFETs with semiconductor layers thicker than ~15 nm will thus remain independent and will not merge. The formation of the channel, in addition to creating a conducting path between the source and drain electrodes, also screens the gate potential similar to the operation of a plate capacitor. This means that when a channel is in the accumulation regime, the gate that causes the accumulation is fully screened by the charges within the first 2-4 nm and the second channel will not feel the presence of this gate. Sweeping single gate potentials in a dual-gate device, leaving the other gate floating, will therefore give separate and independent characteristics for the two channels. The results for the single-gate measurements of a typical DG-OFET with PDTT (25 nm) as the semiconductor and polystyrene (430 nm) as top dielectric are shown in Figure 2. The figure shows the output and transfer characteristics of the top and bottom channels of the DG-OFET measured independently. The currents of both channels are of the same order of magnitude, hence the conduction in the channels is similar. The mobilities calculated from the transfer characteristics in the linear regime are also similar since the capacitances of both dielectrics are comparable. The mobilities found (for V Drain = 5 V and V Gate V TH = 20 V) are cm 2 V 1 s 1 for the bottom channel and cm 2 V 1 s 1 for the top channel. The threshold voltage of the bottom channel is 5.3 V at V Drain = 5 V and 6.0 V at V Drain = 45 V. The threshold voltage of the top channel is +3.0 V at V Drain = 5 V and +3.9 V at V Drain = 45 V. Crucial for analyzing the true properties of a dual-gate device is that a DG-OFET is obtained in which both channels exhibit similar mobilities. We also note that in Figures 2 a and 2 b the saturation of the output characteristics occurs earlier than expected: for V Gate = 40 V the source-drain bias that marks the onset of saturation is around 30 V rather than 40 V. This is explained by the fact that one gate is not connected. Consequently, this floating gate will have an effective potential which lies between the source and drain bias, depending on the leakage resistances between sourcegate and drain-gate. Hence the potential of the floating gate results in an additional electrostatic coupling. Figure 3 shows the forward and backward scans of the 36

6 CHAPTER 3 transfer characteristics of two DG-OFETs with different materials and layer thicknesses, when the bottom gate potential is swept while keeping the top gate potential constant at different top gate potentials. There is almost no hysteresis present in the scans of both of the devices. Figure 2. Device characteristics of the bottom and top channel in a DG-OFET, measured separately. a.) and c.) are the output and transfer characteristics of the bottom channel, respectively. b.) and d.) are the output and transfer characteristics of the top channel. The device is a finger FET (L/W= 20/10000) with PDTT as semiconductor (thickness 25 nm) and polystyrene as the top dielectric (thickness 430 nm). The mobilities obtained (for V Gate V TH = 20 V) are cm 2 V -1 s -1 for the bottom channel and cm 2 V -1 s -1 for the top channel. 37

7 DEVICE CHARACTERISTICS OF DUAL-GATE FIELD-EFFECT TRANSISTORS Figure 3. Forward and backward scans of the transfer curves for two DG-OFET with different capacitance ratios and materials in dual-gate mode. The devices shown are: a.) a finger transistor (L/W= 20/10000) with PDTT as semiconductor (thickness 25 nm) and polystyrene (thickness 430 nm) as the top dielectric, and b.) a finger transistor (L/W= 20/10000) with rr-p3ht as semiconductor (thickness 75 nm) and polystyrene (thickness 450 nm) as the top dielectric. 38

8 CHAPTER Threshold voltage shift in dual-gate OFETs We extract the bottom channel threshold voltage from the transfer curves shown in Figure 3. The threshold voltage is defined as the onset of strong inversion [15]. Although most organic transistors only operate in accumulation mode and show no current in inversion, the classical metal-oxide-semiconductor field-effect theory is used to extract V TH from the transfer characteristics of the transistor in accumulation mode, where the current depends quadratically on the gate voltage: I Drain (V Gate V TH ) 2. The square root of the saturation current is then plotted against the gate voltage. This curve is fitted linearly and the intercept on the V G - axis is defined as the V TH of the transistor. At the threshold voltage the amount of accumulated charges in organic semiconductor, Q G, is equal to zero and this point defines the onset of the charge accumulation. The threshold voltage, for the device depicted in fidure 3 b is plotted as a function of the top gate voltage in Figure 4 and clearly demonstrates the shift in threshold voltage. The linear relationship previously reported [10, 11, 12] is also found here, yet a more detailed analysis of the data demonstrates two linear relationships to be present. The intercept of the two linear fits is close to zero top gate bias. This double linear relationship can be readily explained from the working principle of the DG-FET having two active channels. The current in the channel is dependent on the amount of charges, Q G, which are induced by the gate potential. If one of the channels is depleted (or OFF ), screening of the field does not occur and, consequently, the other channel will depend on both gates via: Q G C2 VG, Top + C1V G, Bottom = (3.1) where C 2 is the capacitance of the layer between the channel and the top gate, C 1 the capacitance of the layer between the channel and the bottom gate, and V G,Top and V G,Bottom are the top and bottom bias, respectively. Note that C 1 or C 2 can consist of the capacitance of a dielectric layer in series with the capacitance of the semiconducting layer. In these devices, the bottom gate potential is swept while the top gate voltage is held constant. If the bottom gate voltage, is more positive than the threshold voltage V TH, no appreciable accumulation of charges in the channels is expected. The point where V G,Bottom = V TH marks the onset for charges to accumulate at the semiconductor-insulator interface. At this point no charges have accumulated and Q G = 0. Then, from rearranging Eq. 3.1, the threshold voltage, when sweeping V G,Bottom, will depend on V G,Top in the following way: 39

9 DEVICE CHARACTERISTICS OF DUAL-GATE FIELD-EFFECT TRANSISTORS C 2 V G, Bottom VTH = VG, Top = VG, Top C1 = (3.2) where is the slope of the line obtained by plotting V TH versus V G Top. As shown in Figure 4, we obtain two cases by sweeping the bottom gate bias and stepping the top gate bias at fixed values. We note that p-type semiconductors are used in these devices. Now several scenarios are possible, depending on the different regimes of screening within the DG-OFET: 1- When the top gate potential is held negative, the top channel is in the accumulation regime. However, by setting the bottom gate at sufficiently positive values we can fully deplete the top channel. This is observed in Figure 3 for bottom gate voltages larger than +20 V. Thus when the bottom gate is sufficiently positive both channels are depleted and the top channel is sensitive for both gate potentials since no charge in the bottom channel is present to screen the bottom gate. According to Eq. 3.1 sweeping V G,Bottom to less positive values will lead to the point where V G,Bottom = V TH and charges will start to accumulate in the top channel while the bottom channel will still be depleted. The accumulation of charges will occur in the top channel first due to a constant negative top gate potential is applied. Since the accumulation occurs in the top channel from Eq. 3.1 it is found that the capacitance C 1, between the bottom gate electrode and the top channel, will be equal to the capacitances of the bottom insulator (C B ) and the semiconductor layers (C S ) in series: C 1 = (1/C B + 1/C S ) 1, while the capacitance C 2, between the top gate electrode and the top channel, will simply be the capacitance of the top insulator layer (C T ): C 2 = C T. At the onset where V G,Bottom = V TH, no charge carriers have accumulated at the bottom interface (Q G = 0), and from Eq. 3.2 follows that: ( C C ) C + C C T B S = (3.3) B 2- On the other hand, if the top gate bias is held positive, for a p-type semiconductor, no accumulation of charges occurs in the top channel close to the semiconductor/dielectric interface and, consequently, no top channel is formed. The bottom channel will switch on when V G,Bottom = V TH and charges start to accumulate according to Eq Then the capacitance C 1, between the bottom gate electrode and the bottom channel is simply the S 40

10 CHAPTER 3 capacitance of the bottom insulator layer: C 1 = C B, while the capacitance C 2, between the top gate electrode and the bottom channel is equal to the capacitance of the top insulator and semiconductor layers: C 2 = (1/C T + 1/C S ) 1. Hence from Eq. 3.2: T S * = (3.4) C B C ( C + C ) T C S Figure 4. Plot of the bottom channel threshold voltage versus the top gate bias for a finger transistor (L/W = 20/10,000) with rr-p3ht (75 nm) as semiconductor and polystyrene (450 nm) as the top dielectric (see Figure 3 b). The drain-source voltage was equal to 20 V. The plot can be fitted with two linear relationships with slopes = 0.39 for linear fit 1 and * = 0.25 for linear fit 2. The intercept of the two fits indicates a transition in the slope and is positioned around top gate voltage between 10 V and 0 V, which corresponds to the threshold voltage of the single gate bottom channel 41

11 DEVICE CHARACTERISTICS OF DUAL-GATE FIELD-EFFECT TRANSISTORS The values calculated with Eq. 3.3 and 3.4 are in good agreement with the slopes extracted from the plot of V TH against V G,Top. The transition point where the slope changes from to * is the point where, due to the top gate potential, the top channel starts to accumulate charge carriers before the bottom channel. This onset of charge accumulation is around a top gate bias of approximately zero volts.. Table 1: Comparison between the calculated and * and the corresponding experimentally found linear fits for the relationship between V TH and V G Top. The bottom capacitance (C B ) is fixed by using 200 nm thermally grown SiO x at F.cm 2. Device Semiconductor/ Top dielectric PDTT( 25 nm)/ PS (375 nm) P3HT( 22 nm)/ PS ( 1250 nm) rr-p3ht( 22 nm)/ PS ( 800 nm) rr-p3ht( 25 nm)/ PS (460 nm) rr-p3ht(25 nm)/ PS (410 nm) rr-p3ht( 25 nm)/ PS (395 nm) rr-p3ht( 75 nm)/ PS ( 605 nm) rr-p3ht( 75 nm)/ PS ( 560 nm) rr-p3ht( 75 nm)/ PS ( 450 nm) MEH-PPV(86 nm)/pmma (354 nm) C S (F cm -2 ) C T (F cm -2 ) Fit 1 * Fit ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ±

12 CHAPTER 3 Table 1 summarizes the obtained -values for a series of dielectric materials, which are in good agreement with the capacitances calculated from the thickness of the layers. If the capacitance of the semiconductor, C S, is very high with respect to C T and C B, we can approximate that: * C T /C B, which is the relationship that was previously found [10, 11, 12]. We also conclude from Table 1 that for a top dielectric layer thicker than 1 µm, hence a very low value of C T, the difference between and * becomes negligible and falls within the experimental error of the measurements. The same analysis can be applied when sweeping the top gate potential at a fixed bottom gate bias. Furthermore, Figure 3 demonstrates that the drain current after the switch-on voltage, depends very strongly on the change of the bottom gate bias when the fixed top gate bias is set to values more negative than the threshold voltage. Compared to the curves of single gate devices (Figure 2) and the curves where the top gate is positive, the increase (or decrease) in current occurs at much faster rate. This increased change in current can be explained by the penetration of the unscreened field of the (positive) bottom gate. The local field in the top channel, controlled by the change in the bottom gate bias, will vary to a larger extend than that for a single gate devices since the contribution of the negative top gate field is also present, leading to a faster increase or decrease in the accumulated charges in the channel, hence a faster increase or decrease in the current. On the other hand when the top gate is fixed to values more positive than the threshold voltage it will never induce any accumulation in the channels and the change in the field in the bottom channel, since the top channel will not reach accumulation, will be the same as in a single gate device Transition region and charge screening in dual-gate OFETs In addition, from the transfer curves in Figure 3, a flattening can be observed around the point where the bottom gate bias is zero and the top gate bias is negative. This feature is depicted more clearly by replotting the data in Figure 5 as a decrease of the differential of the current against the bottom gate bias, δi D /δv G. For the replotted curves at a negative top gate bias, the differential δi D /δv G starts to decrease around a bottom gate bias of zero Volts and continues to decrease until a bottom gate bias of 15 V. This feature of the DG-OFET transfer curves marks the transition region. This feature is similar to the transfer characteristics of an OFET with a doped semiconductor, where there is a field-effect conductive channel at the 43

13 DEVICE CHARACTERISTICS OF DUAL-GATE FIELD-EFFECT TRANSISTORS interface and a bulk current resulting from dopant density present in the semiconductor [16]. Despite the similarities in transfer characteristics, the system here analyzed is not significantly doped, since no intentional dopants were added and the measurements were performed in high vacuum and dark, so the second channel arises from a second interface field-effect channel and not from bulk conduction. The transition region in the transfer curves is present only when the top Figure 5. Transconductance δi D /δv G of the transfer characteristics shown in Figure 3 a. For bottom gate bias between 0 and 15 V, a clear decrease in the transconductance is observed for a fixed negative top gate bias. channel is accumulating charge carriers, and is caused by the screening of the bottom gate potential by the charges accumulating in the bottom channel. When a negative top gate bias and a positive bottom gate bias are applied, there will be no accumulation in the bottom channel; hence no screening of the bottom gate and the top channel will depend on both gate potentials. Sweeping the bottom gate bias from high positive values towards less positive values will lead to accumulation in the top channel. As explained above, this happens when V G, Bottom = V TH, the point where the sum of the fields influencing the top channel, which depend on the gate 44

14 CHAPTER 3 potentials and the capacitances of the layers between the gates and the channel, will start accumulating charges. Current will then start to flow between the source and the drain electrodes. Keeping the top gate bias constant, the current will increase according to the change in bottom gate bias and will depend on the capacitance of the layers between the top channel and the bottom gate (C S and C B ). The bottom channel will be insensitive for the top gate potential since the charges accumulated in the top channel screen the top gate potential. However, when a negative V G,Bottom bias is reached for V G,Bottom > V TH, the bottom channel will start to accumulate charge carriers and switch on. These charges will partially screen the influence of the bottom gate potential on the top channel, causing a decrease in the transconductance of the top channel. This is marked by the transition region where the bottom channel depends on the bottom gate only and the top channel will depend on both gates. Hence we can observe, experimentally, the screening of the gate potential by the accumulated charges, confirming the theoretical models described in literature [14]. Eventually when V G,Bottom is negative and sufficiently large, the charges accumulated in the bottom channel will completely screen the influence of the bottom gate potential on the top channel and the change in overall drain current will depend only on the change of the current of the bottom channel. The current in the top channel will not be modified since V G,Top is held constant. If the top gate bias is positive, no accumulation in the top channel is feasible; hence no transition region will appear since the device operation will depend on the bottom channel only. The bottom channel-only dependence for very negative V G,Bottom is clearly visible from Figure 3 and Figure 5 where for both positive and negative V G,Top, the change in the current and its differential converges for V G,Bottom < 15 V. We note that the considerations stated above hold only for a DG-OFET for two working channels of comparable conductance, i.e., the mobility in one channel is within two orders of magnitude of the other channel. If only one channel is active or if one of the channel is far worse performing than the other (for example a difference in mobilities of four orders of magnitude), then the presence of the transition region in the transfer characteristics of the DG-OFET will disappear, and only one -factor for the relationship between V TH and V G,Top will be found. Obviously, when only one channel is active and influenced by the gates, the presence of the second channel is negligible. 45

15 DEVICE CHARACTERISTICS OF DUAL-GATE FIELD-EFFECT TRANSISTORS 3.3 Conclusions In conclusion, we have demonstrated that the dependence of the bottom threshold voltage on the top gate bias presents two linear relationships depending on which channel of the DG-OFET is switching on first. Furthermore, a decrease in transconductance marks a transition region caused by the screening of the second channel that switches on. Figure 6. Summary of the device operation of the DG-OFET with a p-type semiconductor. The cases depicted are for a device where the bottom gate is swept and the top gate is held constant as seen in figure 3. The semi-transparent arrows in the cartoons represent the penetration of the electric field. a.) Both gate biases are positive, no charge is accumulated in the semiconductor. The electric field from both gate electrodes penetrates through the film. b.) The top gate bias is negative but no accumulation occurs, since the strongly positive bottom gate bias causes depletion throughout the semiconductor. c.) The top gate bias is negative and accumulation occurs in the semiconductor at the top insulatorsemiconductor interface. The accumulation depends also on the positive bottom gate bias, since the electric field penetrates through the semiconductor. d.) Both gate biases are negative, but the bottom gate bias close to zero bias. The field from the bottom gate is only partially screened by the accumulated charges and still can influence the accumulation at the top insulator-semiconductor interface. This partial screening can be detected as a drop in transconductance (Figure 5). e.) The top gate bias is positive and the bottom gate bias is negative. Accumulation occurs at the bottom insulator-semiconductor interface and depends also on the top gate bias. f.) Both gate biases are negative. Accumulation occurs at both insulator-semiconductor interfaces. Since both gate potentials are screened by the respective accumulated charges at the interfaces, each channel depends only on its respective gate bias. 46

16 CHAPTER 3 We demonstrate that the change in the threshold voltage depends on the top gate bias with two linear relationships for two different regimes. If one of the gate potentials is positive and the channel is in depletion, while the other channel is in accumulation, then both gate potentials will influence the active channel. If both channels are in accumulation, the gate potentials are screened by the accumulated charge carriers closest to that gate and both channels operate individually: no mutual influences are observed. For a dual-gate OFET with its top channel in accumulation, we demonstrate a drop in the transconductance when the bottom gate potential becomes negative. This transition regime between both linear regimes is marked by a drop in the transconductance, where the bottom channel depends on the bottom gate only and the top channel will depend on both gates. The transition regime results from the fact that the charges accumulated in the bottom channel will start to screen the influence of the bottom gate potential on the top channel and the change in overall drain current will depend only on the change of the current of the bottom channel. The transition region in the transconductance is a direct experimental observation of the screening of the gate potential caused by the accumulated charge at the semiconductor-insulator interface by the gate bias. A summary of the device operation of the DG-OFET is depicted in Figure 6. References 1 H. Rost, J. Ficker, J.S. Alonso, L. Leenders and I. McCulloch, Synth. Met. 145, 83 (2004). 2 G.H. Gelinck, A.W. Marsman, F.J. Touwslager, S. Setayesh, D.M. de Leeuw, R.C.G. Naber and P.W.M. Blom, Appl. Phys. Lett. 87, (2005). 3 N. Stutzmann, R.H. Friend and H. Sirringhaus, Science 299, 1881 (2003). 4 T. D. Anthopoulos, G. C. Anyfantis, G. C. Papavassiliou and D. M. de Leeuw, Appl. Phys. Lett. 90, (2007). 5 A. J. J. M. van Breemen, P. T. Herwig, C. H. T. Chlon, J. Sweelssen, H. F. M. Schoo, E. M. Benito, D. M. de Leeuw, C. Tanase, J. Wildeman and P. W. M. Blom, Adv. Funct. Mater. 15, 872 (2005). 47

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