A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC

Transcription

1 Microelectronics Journal 37 (06) A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC Wanjun Chen *, Bo Zhang, Zhaoji Li Center of IC Design, University of Electronic Science and Technology of China, Chengdu, Sichuan , People s Republic of China Received 15 July 05; received in revised form 19 September 05; accepted 22 September 05 Available online 14 November 05 Abstract In this paper, a novel double RESURF LDMOS with multiple rings in non-uniform drift region is proposed and successfully fabricated. The proposed device maximizes the benefits of the double RESURF technique by optimizes key process and device geometrical parameters in order to achieve the lowest on-resistance with the desired breakdown voltage. In addition, a versatile JFET device is firstly developed. The JFET device cannot only be used as the current detector, but also be used as the internal power supply for SPIC. Besides, it is compatible with Bipolar-CMOS technology, without any additional processes required. q 05 Elsevier Ltd. All rights reserved. Keywords: RESURF LDMOS; SPIC; Current detector; JFET; Power supply 1. Introduction Smart power IC (SPIC) combines the power device with CMOS logic and/or bipolar analog circuits on one chip are gaining more and more attentions, such as motor control, electronic ballasts, and switched mode power supplies. The integration of discrete elements promises to provide improved performance, increased functionality, enhanced reliability and compact solutions [1 3]. The work on the SPIC switch presented in this paper has been brought about by the needs of a new generation of power supplies. A schematic connection of the SPIC is shown in Fig. 1. A 700 V power MOSFET, oscillator, current limit and thermal shutdown circuit, and so on, are integrated onto a monolithic device. The lateral double-diffusion MOS (LDMOS) transistor is considered as the device of choice when a high voltage power device is integrated monolithically with low voltage Bipolar- CMOS devices for SPIC. The Reduced SURface Field (RESURF) technique is the most widely used method for designing high breakdown voltage, low specific on resistance MOS device. However, the device reported herein is a novel * Corresponding author. Tel.: C ; fax: C address: cwjzcz@yahoo.com.cn (W. Chen) /$ - see front matter q 05 Elsevier Ltd. All rights reserved. doi: /j.mejo double RESURF LDMOS fabricated using the optimum P-type multiple rings realized by implantation of impurity dopants through a mask having a sequence of opening and subsequent annealing. The widths and spacing between rings are optimized to achieve high voltage and the N-well drift region and the P-type multiple rings need to be fully depleted to achieve double RESURF theory [4 8]. SPIC s designing is always a difficult challenge. SPICs, especially those for high voltage operating environment, high voltage and large current are often encountered. The protecting circuits are, therefore, of importance. Some structures are proposed to sense the power MOSFET current or voltage, but these embodiments will make up a substantial total area and/or bring a trouble in layout [1,9 11]. In this paper, a versatile JFET device is firstly developed. The JFET device cannot only be used as the current detector, but also be used as the internal power supply for SPIC. Furthermore, the layout of the SPIC can be realized in one metal layer. When power MOSFET is in off state, the JFET device provides a convenient power source for control circuit and the like, eliminating the need for a bias winding and associated circuit. Despite the voltage of up to 700 V at the drain, JFET conduction channels pinch-off and keep the voltage at JFET tap from exceeding approximately 10 to 100 V. When the power MOSFET is in the on state, the JFET device can be used to sense the drain current. This connecting is therefore useful in the application where current limiting or similar functions are important. 转载

2 W. Chen et al. / Microelectronics Journal 37 (06) BYPASS + BYPASS PIN UNDER-VOLTAGE REGULATOR 5.8 V DRAIN AUTO- RESTART COUNTER RESET CURRENT LIMIT STATE MACHINE V ILIMIT CURRENT LIMIT COMPARATOR + JITTER CLOCK THERMAL SHUTDOWN DC MAX OSCILLATOR CONTROL CIRCUIT Fig. 1. A schematic connection of SPIC V LDMOS structure The proposed LDMOS structure shown in Fig. 2 is realized using a modified Bipolar-CMOS process in TSUPREM4 [12] and then imported into MEDICI [13] for device simulations. In this structure, the P-type multiple rings are inserted in the top of the N-well drift region. The widths and spacings between the rings are varied resulting in a lower drift region doping concentration near the source and a higher doping concentration near the drain to optimize the trade-off between the specific on resistance and the breakdown voltage. In addition, the double field plates are used in drain and source terminal to reduce the electric field peak and enhance the breakdown voltage. The desired trade-off between breakdown voltage and the specific on resistance is obtained by varying drift region charge and P-type rings for the process used. Fig. 3 shows that the device breakdown voltage (BV) is highly dependent on the N-well dose in the drift region and it has a clear optimum. The specific on resistance is decreased with increasing the N-well dose. Breakdown voltage as function of P-type rings dose for different N-well dose are shown in Fig. 4. As can be seen, for a fixed N-well dose, P-type dose has an optimum, BV R on_spt n-well dose (*10 12 cm -2 ) Fig. 3. Simulation the breakdown and specific on resistance as function of the N-well dose. R on_sp (mohm.cm 2 ) e12 cm e12 cm e12 cm P type rings dose (*10 12 cm -2 ) Fig. 2. The structure of the proposed double RESURF LDMOS and simulated potential contours at breakdown with optimum drift region dose. Fig. 4. Simulation the breakdown for different N-well dose as function of the P-top dose.

3 576 W. Chen et al. / Microelectronics Journal 37 (06) Experiment Simulation Drift Length (um) Fig. 5. Experimental and simulation results for different drift region length. resistivity U cm. At the beginning of the fabrication process, the wafer undergoes an implantation of phosphorous ions for the drift region. The doses, 1.4!10 12 is used for the drift region. The choice of doses is based on diffusion trials and extensive process and device simulations. The eight P-type rings are realized by a masked implantation of boron dose of 9.5!10 12 cm K2 at 40 kev in the drift region which dose is 1.4!10 12 cm K2. In order to smear out the dopants, total thermal budget is determined by taking into account all the high temperature process steps following the rings implant and subsequent annealing. Fig. 5 shows the comparison of breakdown voltage sensitivity on the variations of the drift length between experimental and simulation results. It can be seen from the figure that measured results are lower about 100 V than simulation results. Like the simulation results, measured values of breakdown voltage are increased with increasing drift region length. Fig. 6 shows the output characteristic curve of the device. 3. Versatile JFET device used as power supply and current detector Fig. 6. The measured output characteristic curve (IDSZ ma/div, VDSZ5 V/div, VGSZ0.5 V/div). which depends on the different N-well dose. With the increase of N-well dose, the P-type rings range over which breakdown voltage is more 700 V squeezes progressively, so a controllable and tight P-type rings process should be adopted. High N-well dose leads to low on resistance that is desirable for high voltage devices. However, in double RESURF this comes at the expense of a narrow range of rings doses that may pose a limitation on the manufacturability of the devices. Since the main objective from utilizing double RESURF is to minimize the on-resistance while maximizing the breakdown voltage, it is therefore important for the device and process designers to decide on the appropriate N-well and P-type rings conditions based on their process sensitivity, tolerance, stability, and robustness. In order to reduce the cost, the device is realized by using single crystal diffusion technology to form the drift region. The staring wafer is a!100o oriented, P-type wafer, of A versatile JFET device is used as internal power supply and current detector for SPIC. The new JFET device has been simply realized by using the N C implantation in the N-well to form the JFET tap as shown in Fig. 7. It is should be pointed out that the N C implantation region is located near a perimeter boundary of the N-well region. In this embodiment, the new JFET tap is laterally separated from the device power MOSFET channel areas to avoid interfering with normal device operation. In this new JFET, the gate of JFET device (P-sub) is connected to GND, the drain of JFET device is connected to the drain pin of the power MOSFET and the source of JFET device (JFET TAP) is connected to the 5.8 V regulator circuit and current limit circuit. A typical 5.8 V regulator is shown in Fig. 8. The 5.8 V regulator charges the bypass capacitor connected to the BYPASS pin to 5.8 V by drawing a current from the JFET device, whenever the power MOSFET is off. The BYPASS pin is the internal supply voltage node for the SPIC. Extremely low power consumption of the internal circuit allows SPIC to operate continuously from current it takes from the drain pin. In Fig. 8, When the M2 is off and M1 is on, the V sense is low, the JFET cannot pinch off, and so the JFET device charges (a) power MOSFET JFET DEVICE GATE (b) V drain V sense n+ n+ DRAIN H n-well D D JFET TAP GATE p-sub Fig. 7. The structure of the proposed JFET device (a) The layout of the JFET device; (b) The cross-section of the JFET device along with the D D section.

4 W. Chen et al. / Microelectronics Journal 37 (06) Drain V sense JFET Device M1 bypass capacitor BYPASS PIN R1 R2 M2 Fig. 11. Simulation potential contours and depletion layer at JFET pinch off. Fig. 8. A schematic 5.8 V regulator circuit. Drain 80 Gate JFET Device Charge Current (ua) H=10 um H=16 um I I sense limit - + Fig. 12. A schematic current limit circuit Resistance (kohm) Fig. 9. The charge current as a function with resistance at HZ10 mm and HZ 16 mm. the bypass capacitor. Because the doping concentrations of the N-well is decided by power MOSFET, the value of the charge current can be varied by change the width of the JFET device (H) and the resistance value (R1). The charge currents as a function of R1 value at different width value (H) are shown in Fig. 9. While the voltage of the bypass capacitor is 5.8 V, the M2 is turn on and then pull the M1 in off state. Because this time, the total resistance is approximately equal to (R1CR2), the voltage of V sense will increase, which will reduce the conduction width of the JFET device. If the V sense is so high that the JFET will pinch off, which keep the voltage at JFET tap (V sense) from 10 to 100 V. Fig. 10 shows the V sense along with the V drain in different value of H. it can be seen from the Fig. 10, the V sence becomes almost same as V drain at the beginning because the JFET device dose not pinch off. While the V drain is high, the V sense is stable because the JFET device pinches off as shown in Fig. 11. The current limit comparator is connected to the drain pin of the power MOSFET. When the power MOSFET is in on state, the JFET and the power MOSFET are parallel connection as shown in Fig. 12, so a part of drain current flows through the current limit comparator, which can be used to sense the drain current. Fig. 13 shows the detector current versus that of the drain current. It is clear that the drain current of power MOSFET is in one to one correspondence with that of the detector. The JFET device is connected to the current comparator, the detector current (I sense ) can be transmitted to V sense (V) V Drain (V) H=16 um H=10 um H=4 um Fig. 10. The voltage at JFET tap versus the voltage of the power MOSFET drain. I sense (ua) I Drain (ma) Fig. 13. The current of the detector versus that of power MOSFET drain.

5 578 W. Chen et al. / Microelectronics Journal 37 (06) compare with the I limit and output a signal to protect/not to protect the power MOSFET. 4. Conclusions A novel double RESURF LDMOS is proposed and successfully fabrication. The key feature of the proposed LDMOS is that the device is realized by using the high energy implantation to form the N-well drift region and the P-type multiple rings are inserted in the top of the N-well drift region to optimize the trade-off between the specific on resistance and the breakdown voltage. In addition, a versatile JFET device is firstly developed. When power MOSFET is in off state, the JFET device provides a convenient power source for control circuit and the like, eliminating the need for a bias winding and associated circuit. When the power MOSFET is in the on state, the JFET device can be used as a detector to sense the drain current. Furthermore, it is compatible with Bipolar-CMOS technology, without any additional processes required. Acknowledgements This work is supported by a major project of NSFC (No ). References [1] Lei Han, Xing-ning Ye, Xing-bi Chen, Integrated high-voltage detector in 600V SPIC by using FFLR, IEEE 01 International Conference on Solid-State and Integrated-Circuit Technology Proceedings (ICSICT), October, vol. 1, 01, pp [2] A.M. Lokhandwala, S.K. Mazumder, Discrete validation of a smart power ASIC (SPIC) for a distributed power system, Power Electronics Specialists Conference, 04, PESC 04, 04 IEEE 35th Annual, 25 June, vol. 5, 04, pp [3] Chen Xing-bi, Fan Xue-feng, Optimum VLD makes SPIC better and cheaper, IEEE 01 International Conference on Solid-State and Integrated-Circuit Technology Proceedings (ICSICT), October, vol. 1, 01, pp [4] Jie wu, Jian Fang, Bo Zhang, Zhaoji Li, A nobel double RESURF LDMOS with multiple rings in non-uniform drift region, IEEE 04 International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), October 04, pp [5] Zia Hossain, Mohamed Imam, Joe Fulton, Masami Tanaka, Double-resurf 700 V N-channel LDMOS with best-in-class on-resistance, International Symposium on Power Semiconductor Devices & ICs (ISPSD 02), 02, pp [6] S. Hardikar, M.M. De Souza, Y.Z. Xu, T.J. Pease, E.M. Sankara Narayanan, A novel double RESURF LDMOS for HVIC s, Microelectronics Journal (04) [7] Adriaan W. Ludikhuize, A review of RESURF technology, International Symposium on Power Semiconductor Devices & ICs (ISPSD 00), 00, pp [8] Steve Merchant, Arbitrary lateral diffusion profiles, IEEE Transcactions on Electron Devices 42 (12) (1995) [9] Yan Han, Jiahua Chen, Jian Liang, Summary of HV power IC s protecting circuit design, IEEE 01 International Conference on Solid-State and Integrated-Circuit Technology Proceedings (ICSICT), October, vol. 1, 01, pp [10] Norihito Tokura, Tsuyoshi Yamamoto, Kunihiko Hara, On-chip new current sensing technology with high accuracy using field effect resistance for intelligent power MOSFETs, International Symposium on Power Semiconductor Devices & ICs, (ISPSD 1992), 1992, pp [11] T. Terashima, M. Yoshizawa, M. Fukunaga, G. Majumdar, Structure of 600 V IC and a new voltage sensing device, International Symposium on Power Semiconductor Devices & ICs (ISPSD 1993), 1993, pp [12] TSUPREM4 User Manual, Avant! Corportion, [13] MEDICI User Manual, Avant! Corporation, 1998.