A Tunable Body Biasing Scheme for Ultra-Low Power and High Speed CMOS Designs

Transcription

1 1 A Tunable Body Biasing Scheme for Ultra-Low Power and High Speed CMOS Designs Jabulani Nyathi, Member, IEEE Brent Bero, Student, IEEE and Ryan McKinlay Student, IEEE Abstract Interest in VLSI subthreshold design has recently increased due to the emergence of systems that require ultralow power operation. Further more the ever increasing leakage currents, now used to drive logic make subthreshold design an interesting prospect. Subthreshold sacrifices speed for power creating a clear divide between designing for high speed and ultra-low power. It might be beneficial to allow circuits designed for subthreshold operation to become operable at above threshold voltages (super-threshold), depending on processing needs. In this paper among other things; the feasibility of optimizing device sizes for both subthreshold and above threshold operations is considered. Three widely publicized body biasing techniques are examined and compared to a newly proposed tunable body biasing scheme. The comparison is in terms of power and energy dissipation as well as speed. A number of logic styles are simulated to draw conclusions on what logic style in conjunction with what body biasing scheme offer improved performance. The tunable body biasing scheme offers the ability to operate circuits in either the subthreshold region for ultra-low power, at above threshold voltages for high speed or at voltages that offer optimal speed-power operation (2 V t for example). Device sizing for circuits to span all the regions of operation is examined. The tunable body biasing approach leads to increased operating frequencies particularly in subthreshold operation and shows no performance degradation at voltages above threshold, hence bridging of the speed-power gap. Post layout simulations of circuits ranging from simple to more complex ones enable for effective evaluation of optimal device sizing and identifying the optimal power-speed operational region. Simulations have been performed at a modest 18 nm technology node and ring oscillator circuits show optimal operating regions ranging from.5 to.7 V. An 8-bit linear feedback shift register using the tunable body biasing scheme serves as a design example and expends 4.24 joules per second at super-threshold while dissipating 2.34 nj per second at subthreshold voltages. The linear feedback shift register also shows optimal operating regions ranging from.5 to 1.1 V. Index Terms Ultra-low power, Subthreshold, Body Biasing, High-Speed, LFSR I. INTRODUCTION INTEREST in subthreshold design has increased because of the emergence of systems that require ultra-low power. A subthreshold approach sacrifices speed for power, utilizing leakage currents to drive logic gates [1]. Some of the prime candidates of subthreshold design approach include wearable devices, implantable medical technology, and minute sensors (motes). These devices do not necessarily require fast operation and are therefore suited to the ultra-low power schemes. The emergence of subthreshold circuits is a direct consequence of increasing leakage currents in super-threshold operation. As technologies scale deeper into the nanometer range, leakage power becomes more prominent. Considerable work on limiting leakage currents has been done for superthreshold (above threshold) circuits [2], [3], [4]. Techniques to limit leakage currents at above threshold voltages include: use of multiple threshold CMOS (MTCMOS) devices in a design. This technique uses both high and low threshold devices within a design with the high threshold devices intended to suppress leakages while the low threshold devices lead to high performance when the circuit is active. The technique is described in detail in [5], [6], [7], [2]. The variable threshold CMOS (VTCMOS) is another technique in which a selfsubstrate bias circuit is used to control the bulk voltage of the devices. Low threshold bulk voltages are achieved when the circuit is in active mode while high threshold voltages are attained in the OFF state [6], [7], [2]. Stacking devices within logic gates also reduces leakage currents and this is based on the fact that two devices in their OFF state will leak less current compared to a single OFF device owing to the self reverse biasing effects [2]. Transistor stacking as a method to reduce leakage currents is further enhanced by the insertion of leakage control transistors in the stack (the LECTOR technique) reported in [8]. This is not an exhaustive list of leakage current control techniques. The ever increasing leakage power dissipation is reduced by using these techniques and high-speed operations can be maintained. Subthreshold design shows a distinct separation between designing for ultralow power and high speed. This paper presents an approach that permits a design to operate in both subthreshold and at above threshold voltages. In Section II the transistor leakage currents are examined by simulating both pmos and nmos devices and comparing ON and OFF currents. In addition changes in bulk voltages that lead to increased leakages are analyzed. Section III presents body biasing techniques and introduces the tunable body biasing scheme showing how it enables devices to operate effectively in both subthreshold and super-threshold voltages. In Section IV logic styles using the different body biasing techniques and the associated performance gains are examined. The reduction of power supply voltages undoubtedly leads to degradation of noise margins and this is discussed in Section V. In Section VI the subject of device sizing for optimal operation in both subthreshold and above threshold is presented. Control circuits designed to provide appropriate voltages to the devices bulk terminals are presented in Section VII and a description of the metrics used to evaluate design performance appear in Section VIII. To demonstrate the viability of the tunable body biasing scheme a design example is presented in Section IX with the power, energy, speed and energy-delay product detailed. Some concluding

2 2 remarks appear in Section X. 1.E+ 1.E-1 1.E-2 II. BULK CMOS SUBTHRESHOLD CURRENTS MOS transistor operation in both subthreshold and full V DD are well documented. Device leakage currents have been extensively studied primarily with a view of identifying leakage current sources and being able to keep these currents at a minimum [2], [3], [5], [6]. The focus on leakage currents is beginning to shift from this view of minimization to actually using these currents to drive logic [1], [9], [1], [11]. Digital circuits tend to simplify transistor operation, allowing devices to be viewed as switches. When the devices are operated at power supply voltages exceeding the threshold voltages they already exhibit some ill-effects. They do not operate as ideal switches and these effects cannot be viewed differently in subthreshold. In fact the problems are more pronounced in the subthreshold voltages since these leakage currents are relied upon to drive logic. The leakage currents that are expected to drive logic are present in the devices OFF state. There is therefore a need to minimize the OFF state leakages in order to preserve the ultra-low power benefits. There are a number of variables that influence device response and in this study the bulk terminal voltage is one of the variables whose effects will be analyzed. Varying the bulk terminals would provide further insights into device response to changes at the gate and drain/source terminals. The standard configuration has the bulk of the nmos tied to the ground terminal, while that of the pmos is tied to the power supply voltage (V DD ) for an inverter. This prevents forward biasing the source/drain-to-bulk p/n + junctions. If the bulk terminal of the nmos device is raised above ground and the power supply voltage is below threshold, there is a noticeable increase of the drain current. Similarly, lowering the bulk voltage of the pmos device leads to increased drain current. The bulk voltage (V B ) allows the p/n + junction to be forward biased thus allowing current flow from the bulk into the source/drain regions. Figure 1 compares the drain currents of a device whose bulk is raised (nmos) to that of a device whose bulk terminal is at logic. With increasing gate-to-source voltage and the bulk voltage at 6 mv (18 nm technology) the drain current increases by at least an order of magnitude particularly at voltages below the threshold. Above the threshold voltage the drain current is dominated by the saturation current and is thus comparable to the drain current when the bulk is at ground for nmos and V DD for pmos. Bulk voltage manipulation leading to increased leakage currents in the subthreshold region could lead to increased switching speeds while potentially dissipating less power. The increase in the drain-to-source current (I DS ) based on this configuration is seen across all technology nodes. Simulations performed at 35-, 25-, 18- and 9-nm show this trend. The pmos yields similar increases in current when its bulk is tied to ground instead of the standard configuration (bulk tied to V DD ). The ability to increase subthreshold currents in this manner calls for the examination of the OFF current (I OF F ) with the modified bulk potential. The devices Device Drain Current (A) 1.E-3 1.E-4 1.E-5 1.E-6 1.E-7 1.E-8 1.E-9 1.E-1 1.E-11 1.E-12 Region of Interest I DS with V B = 6 mv I DS with V B = mv Two Orders of Magnitude V tn Gate-to-Source Voltage (V) One Order of Magnitude Fig. 1. nmos with V B = V, compared to a configuration with V B = 6 mv. do not effectively turn OFF and would thus dissipate power even when there is no useful work being performed. Figure 2 compares the OFF current of a device (nmos) whose bulk is at ground to that of a device whose bulk is biased at V DD. The traces of Figure 2 were obtained by keeping the nmos transistor s gate voltage at V while the drain-tosource voltage (V DS ) gets increased from to V DD and the resultant leakage currents recorded. It is apparent from this figure that for bulk biasing to become a tenable technique in subthreshold operation there should be a way to reduce the OFF current when there are no computations being performed. It is likely that some of the circuit level methods used to reduce leakage currents in high speed circuits can be employed here, however it seems more appropriate to revert to the standard biasing (nmos bulk at ground and pmos bulk at V DD ) when the circuit is in its OFF state. Dynamic nodes will be affected the most particularly those whose states must remain at logic 1. Despite this observation it is important to note that these currents can be kept in the pico-ampere range as a result the leakage power is not alarmingly high. Another configuration that increases the subthreshold currents requires that the bulk of each transistor be tied to its gate, the subthreshold dynamic threshold voltage (Sub-DTMOS) presented in [1]. Details of this dynamic threshold configuration are given in the next section. III. BODY BIASING TECHNIQUES Most designs of the subthreshold regime rely on body biasing to ensure fast switching coupled with effectively turning off the devices when idle. There exists a number of body biasing schemes with the most commonly used being the Dynamic Threshold Voltage MOSFET (DTMOS) [12] and the swapped body biasing (SBB) scheme [13]. The DTMOS configuration is such that the bulk terminals of the p- and n-type devices are connected to the input signals of the circuit. This has the effect of forward biasing junctions as the input switches from high to low or vise versa. The transistors effectively turn off when the power supply voltage exceeds the zero bias threshold voltage. The DTMOS is strictly for subthreshold operations. It is not scalable to the superthreshold region and is thus limited to low-speed applications.

3 3 6 I_off with Vb=Vdd I_off with Vb= 5 4 I off (na) V DS with V GS= (mv) Fig. 2. nmos OFF currents comparing device with bulk tied to ground and one with bulk tied to V DD. The pmos behaves the same as the nmos, showing increased OFF current when its bulk voltage is tied to ground and significantly less current when the bulk is tied to V DD. These observations have led to several body biasing schemes some of which include (i) swapped body biasing (SBB), (ii) dynamic threshold CMOS (DTMOS), and (iii) adaptive body biasing (ABB) just to name a few. V in V DD Vout (a) Conventional CMOS Inverter V in V DD (b) DTCMOS Inverter Vout V in V DD (c) Swapped Body Biasing Inverter Fig. 3. Configuration of three different body biasing schemes 3(a) shows a conventional CMOS inverter, 3(b) is the dynamic threshold CMOS (DTMOS) and 3(c) the swapped body biasing scheme (SBB). Additionally, DTMOS requires partitioned wells or specialized processes such as Silicon on Insulator because the circuits that do not share input signals cannot share a common substrate connection or well. DTMOS switches faster than static CMOS (Figure 3(a)) at voltages below the zero bias threshold voltage (V t ). In the case of the SBB technique, the bulk of the nmos devices are tied to the power supply voltage V DD while those of the pmos devices are tied to ground, hence swapped body biasing compared to the conventional configuration. Swapping the bulk terminals provides increased drive currents in the subthreshold operation from an exponential current increase, but degrades output node voltages when V DD is greater than the zero bias threshold voltage. Thus, this technique eliminates high speed circuits by requiring subthreshold supply voltages. DTMOS and SBB are comparable in terms of switching speed. Figure 3 shows inverter circuit schematics for conventional CMOS, DTMOS and SBB configurations. The conventional CMOS inverter shown in Figure 3(a) allows for operation in both subthreshold and at above threshold power supply voltages, its major drawback is that it does not switch fast. To improve on the conventional inverter switch- Vout Fig. 4. Subthreshold operation of conventional CMOS, DTMOS and SBB inverter circuits. ing in subthreshold the DTMOS and swapped body biasing schemes of Figure 3(b) and Figure 3(c) were introduced. Figure 4 shows traces of the inverter circuit response to an input signal under the three biasing schemes of Figure 4. The SBB scheme allows the pmos devices well to be connected to ground while the bulks of the nmos devices are connected to the power supply voltage (V DD ). Simulations show that swapped body biasing has diminishing returns past the threshold voltage as a result the technique has been used at low power supply voltages for energy efficient designs. The dynamic threshold CMOS circuit has the bulk of the transistor tied to its gate allowing the threshold voltage of the device to change dynamically with the gate input voltage. Increasing the power supply voltage to above threshold with this configuration in effect leads to the device turning OFF. Simulations show this approach providing higher currents than the default CMOS configuration when operating in the subthreshold region. An adaptive body biasing scheme that selects between operation in the subthreshold region and above threshold is proposed in this paper. The scheme offers significant performance improvements over a range of power supply voltages (V DD =.5 V t through V DD = 1.8 V ) for a 18 nm TSMC process. This offers an option of having tunable circuits that can operate in the ultra-low power range and also offer high speed at voltages above threshold. The approach is termed tunable body biasing (TBB) scheme. Figure 5 shows the configuration of the bulk terminals depending on the region of operation. The application space for systems using circuits that could offer ultra-low power, high-speed or an optimal speed-power trade-off is yet to be explored. Microprocessors, microcontrollers and a host of system on chip (SoC) designs would benefit from such tunable digital design. Controlling the bulk terminals of CMOS devices offers improved performance. In this paper circuits whose bulk terminals are controlled depending on the region of operation are explored and the performance gains achieved under such configurations reported. Controlling the devices bulk terminals is done primarily to increase speed at subthreshold, but also to provide the capability to operate at full V DD using the same circuits and

4 4 V DD V DD GND V in V BP_Control Vt VDD V t V BN P_Control Vout V BN_Control Select Fig. 6. The 2:1 multiplexer for generating the bulk control signals. Fig. 5. Tunable body biasing inverter circuit. TABLE I TUNABLE BODY BIASING SCHEME S BULK CONTROL VOLTAGES and their propagation delays compared. Given the fact that most the configurations offer limited operation (i.e. provide improved performance for a prescribed region), a body biasing technique that offers improved performance in both subthreshold and above threshold regions is proposed. V DD pmos Device s V B nmos Device s V B GND < V DD V t GND V DD V DD > V t V DD V Vt V t IV. DIFFERENT LOGIC FAMILIES IN SUBTHRESHOLD maintaining the performance gains. To span the subthreshold and super-threshold regions of operation the proposed tunable body biasing (TBB) approach is used. The pmos bulks are driven by either ground (GND) in subthreshold or V DD - V t in super-threshold, while nmos bulks are driven by V DD in subthreshold or V t in super-threshold. V t denotes the n-type device threshold voltage when the device s bulk and source are at ground. The TBB bulk control voltages are summarized in Table I and they allow for fluent operation at both subthreshold and super-threshold operating voltages. Ideally the design offers ultra-low power when operating in subthreshold, high-speed when the power supply is higher than the threshold voltage as well as an optimal range with a good speed-power trade-off. In this manner, supply voltage can be used to control performance aspects of systems, allowing high-speed and low-power modes with minimal architectural modifications. All these operating regions are considered based on devices optimized for either subthreshold or superthreshold operation. Inverter simulations have been relied upon to evaluate the tunable body biasing scheme under various input conditions. To analyze the behavior of a more complex system, an 8-bit linear feedback shift register (LFSR) has been studied. Operating frequencies and energy dissipation in the various regions of operation using the different body biasing techniques are compared. The V BPControl and V BNControl signals are generated based on the desired region of operation i.e. subthreshold or super-threshold. A simple 2:1 multiplexer has been used to enable for selection of the region of operation. In the following different logic families operating in subthreshold using these different configurations are presented To the best of our knowledge no work has been presented that analyzes different logic families under the different body biasing schemes described above. It would be ideal to have some reference regarding performance gains or lack of performance gains that result from using these biasing techniques and this is an attempt to make available such knowledge. In addition a biasing scheme that would permit a design to function in both subthreshold voltages and in super-threshold voltages is shown to perform comparably to other schemes in subthreshold voltages. An analysis of different logic styles is essential in the subthreshold region as this could provide a designer with a meaningful choice depending on what the design calls for: speed, power, reliability (based on noise margins), or a good compromise between high speed and ultra-low power. The study provides some insights on different logic style performance in the subthreshold region. Normally analysis of an inverter operation and its performance are deemed sufficient to enable for reasonable performance estimations for any other logic gate. In this study it is deemed necessary to analyze the different logic gates (NOR, NAND, XNOR, XOR etc) under different logic families such as static CMOS, pseudonmos, Domino logic, and pass transistor logic. Static CMOS with standard body biasing (nmos devices bulk at ground and pmos devices bulk terminals at V DD ) is considered as reference. Admittedly there are more logic families than discussed here, but these are the most representative ones and results obtained can easily be extended to other logic families. It would also be important to ensure that the work covers the effects of parametric variations (environmental as well as process variations) at these low voltages and an interested reader is referred to [1].

5 5 AVERAGE SWITCHING DELAY (ns) Transmission Gate Inverter Two Input NAND Two Input NOR Two Input XOR 5 TRADITIONAL SBB TBB DTMOS Static CMOS at Vdd = Vthn with varying Body Biasing Fig. 7. Static CMOS delay under different biasing conditions (Conventional, SBB, TBB and DTMOS). A. Static CMOS Delay Under Different Body Biasing Techniques Before examining the different logic style performance attributes under subthreshold voltages, it is instructive to present performance evaluations of static CMOS under different body biasing schemes. The different configurations are simulated and propagation delays along with rise and fall times recorded. The propagation delay simulation results appear in the bar chart displayed in Figure 7 and they confirm the findings on individual device simulations of Figures 1 and 2, showing that swapped body biasing leads to shorter propagation delays. The shorter propagation delays imply increased power dissipation, but still the speed benefits out-weigh the negative impact on power dissipation. An SBB configured NAND gate based ring oscillator is 6 times faster than a standard biased one and dissipates.522 nw/cycle. The ring oscillator with standard biased NAND gates dissipates.643 nw/cycle. These values indicate overall performance gains under conditions where the activity factor α is 1. Propagation delays of Figure 7 are those of static CMOS transmission gate, inverter, NAND2 NOR2 and a two input XOR under the different body biasing conditions. As expected the propagation delay of subthreshold circuits increases as the logic becomes more complex; series p-type and n-type transistors take longer to charge and discharge nodes. Also, the overall relationships in terms of propagation delay between logic gates are consistent throughout the different body biasing techniques. The tunable body biasing (TBB) scheme is a result of the observation that in subthreshold swapping the bulk connections yields improved delays while above threshold swapping the bulk terminal connection degrades the delays significantly. In order to successfully bridge the speed-power gap the bulk terminals have to be controlled such that the V B(N/P )control signals of Figure 5 reflect these findings. SBB and TBB outperform the traditional body biasing technique by approximately a factor of six-to-ten in terms of propagation delay. DTMOS, SBB and TBB techniques are the same configuration in subthreshold voltages and all show significant propagation delay reduction compared to that of the standard CMOS configuration. It is an accepted fact that circuits operating in the subthreshold region run at significantly low frequencies since the target metric is ultra-low power. With a Fig. 8. The conventional inverter and the TBB inverter show desired operation at above threshold voltages while the other schemes fail. power supply voltage as low as 5 % of the nominal threshold voltage the recorded frequencies are in the range of 2 khz to 5 KHz. It is the intention in this work to explore the possibilities of bridging the speed-power gap between ultralow power circuits/systems and that of high speed systems. A more direct way of achieving such performance gains is to increase the power supply voltage to as close to the threshold voltage as possible. At 75 % of the threshold voltage the speed is improved significantly (achieving 8X the frequencies recorded at.5 V t ). These simulation results show that the traditional biasing scheme has significant delays on logic gates compared to the other configurations. DTMOS, SBB and TBB all have comparable delays as already stated however DTMOS and SBB are only good for power supply voltages below threshold. If operation has to span the entire power supply voltage scale from V to V DD, it is better to use the TBB approach. Figure 8 shows traces of the differently biased inverters, clearly showing that the DTMOS and SBB circuits fail at voltages above V t while the conventional Inverter circuit spans both the subthreshold and super-threshold regions, but has significantly large delays in the subthreshold region. The TBB circuit spans both regions of operation just like the conventionally configured CMOS circuit but it has significantly improved switching speed at both the subthreshold and superthreshold regions. In the following delay characteristics of different logic styles configured in the traditional manner are presented and the findings compared to the results of the same logic gates using the swapped body biasing scheme, dynamic threshold CMOS and tunable body biasing schemes. B. Logic Family Gate Delays Under the Various Biasing Schemes Research on subthreshold circuit operation has focused on device sizing, the ultra-low power gains and most importantly the best configuration (i.e. how to bias the bulk terminals for best results) and very little attention has been paid to the influence of logic style on performance in this regime. In

6 6 AVERAGE SWITCHING DELAY (ns) Traditional DTMOS SBB CMOS NAND2 Pseudo-nMOS NAND2 Domino NAND2 Fig. 9. Comparison of propagation delays of a two input NAND gate in different logic styles under different biasing techniques (Conventional, SBB, TBB and DTMOS). addition no analysis of fan-in and fan-out effects on delays has been performed hence circuit operability in this regime is not well documented. Noise Margins analysis at these ultralow supply voltages also need to be examined. Extensive post layout simulations at the 18 nm technology node have been performed for static CMOS, pseudo nmos, Domino and pass transistor logic styles. Of interest are the signal propagation delays and Figure 9 shows a comparison of a two input NAND gate s propagation delays under the different logic styles and biasing schemes. The simulations have been performed only at subthreshold voltages with power supply voltages ranging from.5 V t to.75 V t. Circuit behavior is such that the propagation delays improve with increasing power supply voltage irrespective of biasing scheme or logic style. The simulation results depicted in Figure 9 are those obtained with a power supply voltage of.75 V t. Simulations on inverters, NAND, NOR, XOR and XNOR gates have been performed but only the propagation delays of the NAND gate are shown since all the other gates show similar performance patterns. The tunable body biasing scheme is not represented in this figure because in subthreshold voltages the TBB is the same configuration at the SBB. It is apparent from the graph that Domino Logic has significantly longer delays and static CMOS is the better of the three logic styles under any of the bias conditions. To give a better sense of the numerical values representing these delays a summary of the results is shown on Table II. The values are those of a NAND gate subjected to the various body biasing schemes and designed in static CMOS, pseudo nmos and Domino logic styles. The most complex gate simulated in this exercise is the XOR gate. The XOR gate has a large difference between a CMOS XOR and a pass transistor XOR based of device count and a simple evaluation of the propagation delays in any logic style favors the design with fewer devices. The results obtained from simulating the XOR have been excluded since it is a little more involved to ensure fair comparison. The propagation delays can be improved by selecting a power supply voltage that is closer to the device designated threshold voltage when the bulk is tied to V DD for pmos and tied to ground for the nmos device. These delays favor the static CMOS implementation despite the reduction in TABLE II NAND PROPAGATION DELAYS FOR DIFFERENT LOGIC STYLES AT A POWER SUPPLY VOLTAGE OF.75 V t, ALL VALUES IN NANO-SECONDS (NS). Logic Style CMOS SBB TBB DTMOS Conventional CMOS Pseudo nmos Domino loading capacitance offered by the pseudo nmos design style. Swapping the bulk terminal connections also offers some improvement in terms of propagation delay. The only major drawback with swapped body biasing is that the devices conduct significant amounts of currents even when they are expected to be in their OFF states. The tunable body biasing scheme offers a way to reduce the OFF state currents and would thus ensure further reduction in power dissipation. Reduction of the OFF currents in the TBB scheme is achieved by detecting the input voltage level and forcing the bulk voltage (V B ) to any of the two states that either forward biases the p/n + junction for more current or places V B at logic to reduce leakages. V. NOISE MARGINS A subject of importance as power supply voltages are scaled further into subthreshold is that of Noise Margins. At such small voltages it is possible that a slight change at the input might be misinterpreted by the circuit resulting in an incorrect output. The voltage levels that define the three regions of a digital circuit namely logic, the undefined region and logic 1 are examined. Simulations of an inverter under the three body biasing schemes that have been studied with conventional CMOS used as a reference point are recorded. This exercise has been extended to examine a NAND gate s noise margins. In determining these regions a stair step input to the inverter or NAND gate is defined, with each segment of the stair step remaining at a defined voltage level for some duration. Figure 1 represents the described input signal and the corresponding output. This representation of the input allows for better observation of the circuit response to each defined voltage level (the stair). The circuit response to the input can be analyzed using a ramp as an input, but the start of the transition region becomes less distinct with such an input. The power supply voltage is at mv and from Figure 1 it can be determined the regions at which the output voltage reaches steady state and the transition region is clear. It has been determined that the logic is valid for an input range of -175 mv while a logic 1 is valid for the mv range with the uncertain region occupying the mv range. The nmos bulk terminal is at the ground terminal and that of the pmos at V DD for these simulations. When the bulk terminals connections are controlled (SBB or TBB) the ranges are as follows: Logic is defined in the range -2 mv, Logic 1 is in the mv range and the uncertain region occupies the mv range. Tunable and swapped body biasing schemes have somewhat reduced Noise Margins due to the fact that the inverter remains in a crowbarred state much longer (in the case of the SBB configured

7 7 Fig. 1. Inverter input and output signals showing how noise margins are determined. Traditionally Biased Vdd = mv Vih = 2 mv Vil = 175 mv Vss = mv Tunable Body Biased Vdd = mv Vih = 225 mv Vil = 2 mv Vss = mv Fig. 11. Noise margins (the noise margin high and noise margin low can be inferred from this graph. inverter). Figure 11 summarizes these results. The analysis has been performed only on the static CMOS logic style since it is a foregone conclusion that the pseudo nmos logic style degrades noise margins considerably. The conventional CMOS configuration definitely offers better Noise Margins. The tunable swapped body biasing scheme gives improved propagation delays but has poor Noise Margins. VI. DEVICE SIZING FOR TUNABLE OPERATION A challenge in designing circuits to operate in both the super-threshold and subthreshold regions is determining optimal device sizing. The devices optimally sized to provide symmetric switching in subthreshold must operate in superthreshold with minimal deviation in providing the rise time that is equal to the fall time for a given load. There have been two major contributors towards the study of optimal device sizing for subthreshold designs. In [14] it is suggested that when sizing devices for minimum energy in the subthreshold region, minimum device sizes are best. The analysis of [14] focuses on a reduction of switched capacitance, leakage current, and minimum operating voltage. Using minimum device sizes reduces all of the above parameters and provides an ultralow energy optimization for subthreshold. There are penalties in terms of decreased switching speed and increased energydelay product. Minimum-sized gates do not exhibit symmetric switching in the subthreshold region because of the differences in mobility of the pmos and nmos devices. Results reported in [14] show 5 percent energy savings. A process level approach presented in [15] recommends eliminating halo and retrograde doping while designing the device with high-to-low doping profiles to improve subthreshold operation. In doing so, the devices are no longer optimized for super-threshold operation because of increased drain-induced barrier lowering and body punchthrough. Neither [14] nor [15] consider operating logic gates optimized for subthreshold in the super-threshold region. This would be ideal as it would allow for the same integrated circuit to be used as a high-speed device or low power device when necessary. This study attempts to bridge the ultra-low power-speed gap, enabling designs intended for subthreshold operations to be usable at power supply voltages above threshold and at high speed. It is therefore of great interest to optimize devices such that they can operate in both regions. At the very least, it is prudent to be aware of the trade-offs made when sizing logic circuits in the subthreshold region then operating with the same circuits in the superthreshold region or vice versa. Inverters are initially used to examine optimal device sizing at either region of operation. The inverter circuits are designed for symmetric switching and this is achieved by simply equating the drain currents at both subthreshold and above threshold power supply voltages. The conventional (traditional) inverter whose devices are configured such that the pmos bulk terminal is at V DD while that of the nmos is at ground is used as reference. The inverter designed for symmetric switching at 1.8 V, gives a W p to W n ratio of 3.5:1. The second inverter has the bulk terminals controlled to be at certain voltage levels depending on the desired region of operation (ultra-low power, optimal powerspeed trade-off or high speed). This is considered to be a tunable approach since it offers such flexibility based on the power supply voltage and the bulk terminal control voltage. Symmetric switching for the TBB design at a power supply voltage of mv is achieved with devices sized to give a W p to W n ratio of approximately 1.7:1 for a fan-out-of four (FO4) loading. It must be noted that there exists many data points of the W p : W n ratios. Where necessary for improved drive current the device widths can be made appropriately large and the bulk terminal voltages controlled to yield the increased current and allow for symmetric switching. Any deviations from the expected values should be negligibly small. Figure 12 Shows a linear relationship between the W p : W n for equal values of the drain currents (I dsn = I dsp ) when V gs = V ds = V DD /2 The optimized traditional inverter s average propagation delay (T pavg ) is 128 ps at 1.8 V. If the traditional inverter has a power supply voltage of mv, T pavg is three orders of magnitude slower (123.7 ns) and shows very little deviation in terms of symmetric switching. The tunable inverter switches an order of magnitude faster than the traditional inverter in subthreshold and 2 % faster in super-threshold. T pavg for the tunable inverter is 16.5 ps at super-threshold and 11.6 ns at subthreshold. Thus, the same device gives switching speed gains at both subthreshold and super-threshold. The

8 8 6 5 TABLE III ACHIEVING SYMMETRIC SWITCHING IN SUBTHRESHOLD AND ABOVE THRESHOLD VOLTAGES WITH SAME CIRCUITRY. W (n/p) (µm) pmos Width nmos Width V DD Ideal Inverter V t TBB Inverter V t % Variation 1.8 V 9 mv 9 mv. % 1. V 5 mv 498 mv.4 % mv mv mv 5.6 % mv 94.5 mv 18.6 mv 13.4 % Vdd SubVt_b Vdd SubVt_b I D(n/p) (na) Fig. 12. Device widths yield symmetric switching when configured to deliver equal I ds. pmos Bulk nmos Bulk Vss Vss SubVt SubVt Fig. 14. MOS bulk control circuits. Super-threshold: pbulk = V DD V t Fig. 13. Voltage transfer characteristics of an inverter sized for symmetric switching at above threshold and showing capability to switch optimally at subthreshold. voltage transfer characteristic (VTC) curves of the traditional inverter are presented to provide a sense of the deviation under different power supply voltages. From Figure 13 the inverter threshold (V th ) at each power supply voltage (1.8 V, 1. V, mv and mv) as well as the deviation from the expected value of V DD /2 can be determined. Results in Table III indicate a 5.6 % deviation at subthreshold. Thus, operating at either region has minimal effect on the 5 % switching point. Operating further into the subthreshold region shows a 13.4 % deviation at V t /2. These results show promise in that the inverter can be sized approximately the same in both regions for symmetric switching and maintain an acceptable deviation at the 5 % switching point. Devices optimally sized for symmetric switching in the subthreshold region show similar deviations in super-threshold leading to a conclusion that circuits optimized for ultra-low power can be used to design for high-speed. Also circuits designed for high-speed can be used to design for ultra-low power. This substantiates the approach taken in [11] where standard cell libraries are used to design circuits for subthreshold operations with minimal modification. VII. BULK TERMINAL CONTROL CIRCUITS The capability to control the nmos and pmos device bulk terminals offers some increase in drive current and Fig. 15. Sub-threshold: pbulk = V Bulk Control Waveform with varying V DD for a pmos Device. simple circuits to enable controlling the bulk CMOS wells are presented. The bulk terminals must be controlled appropriately depending on whether the circuit is intended to operate in ultra-low power, high-speed or at an optimal point where the power-speed trade-off is achieved. Bulk control circuits are designed using pass transistor logic and relying on the properties of this logic style i.e. capability to pass good/poor 1s and s. To select the appropriate voltage, multiplexers are used and a select signal is introduced enabling a user to select the desired region of operation. Circuit schematics and simulation waveforms are presented in Figures 14 and 15 respectively. This approach uses two transistors per MOS bulk control circuit. Note that bulk control circuits are biased using the traditional approach. The bulk control circuits are scalable from one technology node to another. The bulk voltage level required will be determined primarily by the power supply voltage level and the designated threshold voltage of the technology node. In both Figures 14 and 15 the signals labeled SubV t and SubV t b are the control signals that enable for selection of the bulk voltage connection. Figure 15 shows traces for a power supply voltage that is initially set to mv then changed to mv. Since these are subthreshold values the bulks of the pmos devices

9 9 are shown to remain at V. When the power supply voltage is changed to 1 V and then to 1.8 V the bulk control voltage changes from V to a voltage level that will always be V DD V t. The nmos devices bulks are driven to V DD in subthreshold and V t when operating in super-threshold. VIII. PERFORMANCE METRICS Section VI presented optimal device sizing to enable circuits to operate at different power supply voltages. As a result propagation delay and inverter threshold voltages were the metrics to pursue. The TBB approach forward biases the bulk terminals of the devices thereby increasing leakage currents. This is the desired effect particularly when the circuit is performing useful computations. The increased switching speed gained might affect energy dissipation adversely especially when the devices are expected to be OFF. There is a significant static current component under these conditions. It becomes important to determine how much additional power and energy is dissipated to achieve these speed gains. Authors of [16] question the validity of energy as a quality metric because it can be made arbitrarily low by reducing the supply voltage. Thus, subthreshold operation appears very attractive in terms of energy. It is argued that EDP is a more relevant metric because it combines a measure of speed and energy. Energy as a metric is not discarded in this study and analysis of the optimal region is based on the energy-delay trade-off as well as the overall EDP. Through a series of experiments, an optimal supply voltage region is determined. This provides the ability to identify an optimal region of operation which saves considerable power while allowing medium speed. To provide a meaningful basis for comparison, delay versus energy, and EDP are analyzed for both traditionally biased and TBB inverters as well as an eight-bit linear feedback shift register (LFSR). The results for inverter comparisons are presented first while those comparing the TBB and the conventional LFSRs appear in the next section. TBB circuits favor highly active circuits like clock networks and data path circuits where idle periods are minimal, thus maximizing the ratio of utilized leakage current to wasted leakage current. Figure 16 plots the delay and energy against the power supply voltages, thereby showing the trade-offs of these metrics as the power supply voltages span the subthreshold and above threshold values for a traditional inverter. Figure 17 shows the energy-delay-product (EDP) plotted against increasing power supply voltage. An inverter using the tunable body biasing technique shows similar trends to those depicted in Figures 16 and 17. There exists a range of power supply voltages (.5 to.7 V) where energy is low and the delay is not terribly low. In this range of voltages a tunable inverter operates 3 times faster than the traditional inverter with a 6 % smaller EDP at the cost of 28 % more energy. By examining delay, energy, and EDP metrics across the range of possible supply voltages as shown in Figures 16 and 17, a designer can choose how much speed they are willing to sacrifice in order to save energy. The body biasing scheme shows a negligible effect on the optimal region of operation. Having established appropriate device sizing for optimal operation in both subthreshold and super-threshold it is in- Propagation Delay ( ns ) Fig. 16. inverter. Energy Delay Product ( ns*fj ) Fig Propagation Delay Energy Dissipation Supply Voltage ( V ) Delay and energy versus power supply voltages for a traditional Traditional Energy Delay Product TBB Energy-Delay Product Supply Voltage ( V ) EDP for a traditional and tunable inverter. structive that a more complex circuit be analyzed under the proposed body biasing scheme. IX. LINEAR FEEDBACK SHIFT REGISTER AS A DESIGN EXAMPLE A linear feedback shift register (LFSR) has been selected as a design example for several reasons; a few of which are outlined below. The authors have been involved in the study of wave-pipelined schemes and are interested in applying this clocking technique to sub-systems with feedback paths [17]. Linear feedback shift registers have such paths and are under consideration as design examples as a result it became natural to use an example design in which there already is some familiarity. Another compelling reason is that LFSRs are such essential components in the design of VLSI chip built-in-self-test (BIST) structures, they also have found widespread use in direct sequence spread spectrum, encryption/decryption, pseudo-random number generators and scrambler/de-scrambler. The LFSR enables for pseudo-random number generation making it an essential circuit in attempts to perform exhaustive and random test approaches. A working LFSR circuit implemented using the tunable body biasing scheme could prove invaluable. The LFSR studied in this work is an 8-bit Fibonacci implementation with four taps. The chosen Fibonacci implementation has logic gates in its feedback path and these logic gates cause performance degradation with an increase in the number Energy Dissipation ( fj )

10 1 D Q 1 Q1 D D D Q Q n 1 2 Q Qn 1 2 Qn Qn 1 clock Energy Delay Product ( ns*fj ) 1 1 TBB Energy-delay Product Traditional Energy-delay Product EDP of TBB outperforms Traditional at ALL operating regions, significantly in super-threshold 1 Fig. 18. Fibonacci LFSR block diagram. of stages. Use of the Fibonacci implementation offers a means to study the effectiveness of the wave-pipelining scheme in reducing delays associated with feedback paths. The wavepipelined linear feedback shift register has been designed to be flexible enabling the user to to perform initialization within a single clock cycle, chose the length of the sequence, select taps, and disable the clock. The design uses D-type flip-flops in the forward path. The flip-flops are clocked on both the rising and falling edges of the clock to enable the propagation of data within a stage. Figure 18 shows a general Fibonacci LFSR block diagram with feedback in parallel. The interested reader is referred to [18] for details on LFSR design. In this study the interest is in evaluating the tunable body biasing scheme for energy and power dissipation along with the ability to have the circuits span both the subthreshold and super-threshold regions of operation. Results obtained using the TBB scheme are compared to those of the same circuits with conventional configuration. In the subthreshold region of operation the TBB LFSR operates 3.8 times faster than the traditional LFSR with a 33 % smaller EDP at the cost of 2.5 times more energy. The frequency of the TBB LFSR in subthreshold is 4.35 MHz and when the power supply voltage is increased to 1.8 V, the frequency increases to 1.67 GHz. These numbers represent 5.66 times and 1.17 times respectively in performance improvement over the conventionally configured LFSR. The simulation results indicate that an optimal region of operation exists between.5 and 1.1 V. Figure 19 shows the energydelay-product plotted against the power supply voltage for both the conventional and TBB linear feedback shift registers. The TBB LFSR outperforms the conventional LFSR at all points of the voltage axis, however the significant difference in performance is in the subthreshold region. To further underscore the benefits of the tunable body biasing scheme a plot showing energy dissipation and the corresponding clock frequencies is shown in Figure 2. The energy dissipated at the highest frequency and that dissipated at the slowest frequencies ate annotated on the figure. The data displayed offers a clear picture of the design s energy and clock frequency at any given point along the voltage axis. The proposition of a tunable body biasing approach has its drawbacks, for an example the increased OFF currents. Emphasis has been placed on the overall energy dissipation of devices and the energy-delay product. These metrics have shown that TBB can provide a low-energy approach. In spite of this, it is important to know what impact idle circuits have on static current and power dissipation. With idle circuits, the activity factor is Supply Voltage ( V ) Fig. 19. Energy-Delay-Product plotted against power supply voltage for both conventional and TBB 8-bit LFSRs. Clock Period ( ns ) Delay vs. Energy Dissipation Tradeoff for TBB LFSR 3.9 MHz with.6 fj/cycle TBB Delay TBB Energy Dissipation MHz with 13 fj/cycle 1.1 GHz with 3.85 nj/cycle Supply Voltage ( V ) Fig. 2. Plot of energy dissipation with V DD spanning all regions of operation. low, presumably zero. To limit static power, most designers put devices into sleep mode during extended periods of inactivity. In order to determine how much more leakage currents are increased with the TBB approach an inverter at the subthreshold and super-threshold regions is examined and results compared to those of a traditionally biased inverter. Total current for both approaches (conventionally biased and tunable circuits) at super-threshold and subthreshold regions of operation have been calculated in order to assess the impact of the static current. The traditionally biased circuit at peak performance in subthreshold dissipates an average of 193 pw per cycle. The static power constitutes.1 % of the total power under these conditions. When operating at 1.8 V the total power is 39.6 µw per cycle and the static power is negligible. The TBB circuit at peak performance in subthreshold dissipates an average of 1.43 nw per cycle and the static power contributes 25.2 % towards this value. When operating at 1.8 V the peak power per cycle for the TBB is 34.9 µw and.34 % of this is the static dissipation. From these values, it can be determined that static current contributes significantly in the TBB approach at subthreshold operation. Reducing these currents when the circuits are idle can be achieved by reverting to the conventional configuration in idle state. The bulk control signals V BN control and V BP control are tied to ground and V DD respectively when in idle state Energy Dissipation ( fj )