COGNITIVE RADIO (CR) [1] is the latest contender for

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1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY A Compact and Low Power 5 10 GHz Quadrature Local Oscillator for Cognitive Radio Applications Jianhua Lu, Ning-Yi Wang, and Mau-Chung Frank Chang, Fellow, IEEE Abstract This paper presents the design and implementation of a compact and low power quadrature local oscillator (LO) for creating GHz signal initially from a differentially tuned LC-VCO and then converting it to the desired 5 10 GHz with continuous frequency coverage. To accomplish such purpose, a 4-stage differential injection-locked ring oscillator (ILRO) is used subsequentlytothelatch-baseddivider to generate quadrature output phases without restricting 50% duty cycle from input signals as those of conventional divide-by-2 approaches. When implemented in a 65 nm general purpose CMOS IC technology, the integrated quadrature-phased LO consumes 22 ma of current at a 1 V supply and is able to exhibit the worst-case phase noise of dbc/hz at 1 MHz offset across the entire 5 10 GHz band for intended cognitive radio applications. Index Terms CMOS, cognitive radio, frequency extension, injection-locked ring oscillator, LC-VCO, quadrature phase local oscillator. Fig MHz 10 GHz Cognitive Radio LO Architecture. I. INTRODUCTION COGNITIVE RADIO (CR) [1] is the latest contender for more efficient spatial and temporal spectrum usage across a broad frequency range, which spans from 50 MHz to 10 GHz. In the foreseeable future, the widely used heterodyne radio architecture is more practical, in terms of its power and cost effectiveness, than sampling directly to the entire band by using power hungry high speed A/D converters. Since primary functions of the CR RF transceiver, including the spectrum sensing, reception and transmission, may operate independently at different channel frequencies, multiple local oscillators (LOs) are generally needed for a system-on-chip (SoC) solution. In addition to general LO requirements of low phase noise/spurs, quadrature output signals with 50% duty cycle, the design of LO for CR applications specifically requires silicon area compactness and low power consumption. In traditional quadrature LO designs for broadband applications, its constituent LC-VCO core often requires large silicon area, owing to the need of large on-chip passive inductor and capacitor arrays, which are indispensable for obtaining sufficiently low phase noise. It is therefore essential to find a compact circuit solution possibly with a single-lc-tank to cover the entire CR band. Manuscript received August 31, 2011; revised November 18, 2011; accepted December 18, Date of publication February 16, 2012; date of current version April 25, This paper was approved by Guest Editor Georg Boeck. J. Lu, N.-Y. Wang, and M.-C. F. Chang are with the University of California, Los Angeles, CA USA. J. Lu is also with the Peregrine Semiconductor Corporation, San Diego, CA USA ( Jack_Lu@ieee.org). N.-Y.WangisalsowiththeBroadcom,Irvine,CA92617USA. Digital Object Identifier /JSSC Fig. 2. Concept of frequency extension (k, l, n, m are integers). It is commonly accepted once an oscillator has larger than 100% frequency tuning ratio (FTR, defined as in this paper), all quadrature signals with frequencies lower than are then obtainable by cascading multiple divide-by-2 circuits as needed. Accordingly, the required LO frequency range to cover the entire CR band from 50 MHz to 10 GHz can be condensed to 5 10 GHz, as illustrated in Fig. 1. Prior publications have reported greater than 100% FTR from a single-lc-tank VCO at lower frequencies [2]. However, the FTR of LC-VCOs is highly dependent on the technology and its devices. In fact,suchhighftr % is not commonly achievable with deep-scaled CMOS technologies at high operation frequencies. The reliable RF products today use either multiple VCOs or dual-vco designs with subsequent frequency extension circuits to cover the desired octave frequency tuning range over the process, voltage and temperature (PVT) variations. The basic principle for frequency extension is to multiply or divide VCO frequencies by variable integers or fractions, as shown in Fig. 2, with primary approaches such as the programmable quadrature Miller feedback divider or the latch-based divider. The former may introduce higher spur levels caused by unwanted mixer sidebands [3]. The latter is usually preferred due to its lower output spurs but cannot generate quadrature phased output signals with 50% duty cycle when its division ratio involves an odd number. As a result, power hungry Duty Cycle Correction (DCC) circuits [14] or quadrature generators must be added to complete the frequency extension requirement /$ IEEE

2 1132 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012 Fig. 3. edges. (a) Divider-by-2 circuit and (b) quadrature phases generated from input To alleviate such shortcomings, we here present a compact and energy-efficient 5 10 GHz quadrature LO enabled by a novel frequency extension solution that takes the full advantage of the natural characteristic of differential injection-locked ring oscillator (ILRO) for producing the desired quadrature outputs with precise 50% duty cycle. Section II addresses detailed issues in relevance to existing quadrature generation approaches and offers differential ILRO as a superior solution for both performance and area/power consumption. Section III describes LO architecture and relevant circuit schematics. Section IV presents test results from an implemented LO in 65 nm CMOS. Finally in Section V, we summarize the overall development work. II. DIFFERENTIAL ILRO AS QUADRATURE SIGNAL GENERATOR The design of an LO with adequate frequency extension must first ensure the generation of quadrature output signal with 50% duty cycle. Otherwise, the quadrature phase mismatch can impair the image rejection and the non-50% duty cycle can intensify even order LO harmonic mixing in a broadband cognitive radio system. To counter such issues, several types of quadrature generation approaches were suggested in the past, including the following. 1) Quadrature oscillators with multiple LC-tanks, which however are inherently large in size. Its subsequent frequency extension circuit, a Miller feedback divider with single side band mixer (SSBM), has issues of high spur level and non-50% duty cycle [3], [4]. 2) Poly-phase filters (PPF), which has significant signal attenuation for wideband applications. The quadrature outputs are severely asymmetric when the input becomes squarewave rather than sinusoidal. Power hungry amplitude limiters are also needed to restore the quadrature output to the same level. 3) Divide-by-2circuit is generally good for compact circuit design, but would introduce two major challenges: a) since it performs frequency division, all preceding stages, i.e., VCO and frequency extension circuit, must operate at twice-higher frequency than intended. Or as an alternative, a frequency doubler must be inserted before the divide-by-2. In either case, it will lead to higher power consumption; b) As shown in Fig. 3, it mandates input signals to maintain 50% duty cycle and any deviation from it will lead to output phase mismatch according to (1), (1) Fig. 4. Conceptual diagram of the proposed differential ILRO. 4) An Injection Locked Ring Oscillator (ILRO) was proposed to generate quadrature outputs [5]. Since the signal was injected through a parallel differential pair directly to the oscillator output, it would adversely affect the output duty cycle and quadrature matching when the input duty cycle deviates from 50%. To alleviate disadvantages from these existing approaches, we here propose to use a non-spur source-injected differential ILRO scheme to generate 50% duty cycle quadrature outputs, without requiring the input signal to be precisely on 50% duty cycle [6]. Fig. 4 shows the conceptual diagram of the proposed ILRO. It consists of two identical stages (Stage-I and Stage-Q) that generate 90 and 180 phase shifts respectively at the oscillation frequency. Each stage possesses a differential amplifier and extra buffer(s) as needed. Differential input voltage signals ( and ) are converted into currents ( and ) before being injected to the common nodes of the differential pairs in Stage-I and Q, respectively. Under locked condition, the ILRO exhibits phase noise of a driven circuit rather than an autonomous one because the close-in phase noise is suppressed by the locking bandwidth, as explained in [7]. Therefore, in an LO design, the overall phase noise is typically dominated by the VCO instead of the ILRO. As a part of LO frequency extension circuit, the proposed ILRO holds the following superior characteristics: 1) Output Duty Cycle Is Retained at 50% Regardless of Input Duty Cycle: As analyzed in Appendix A, for a periodic pulse wave, it is the even order harmonics (especially the second order harmonic) in a bandwidth-limited system that causes the duty cycle to deviate from the 50% duty cycle. Assuming negligible mismatch between each end, the differential ILRO has equal rising and falling time when it is free running. Consequently, the output differential output signal has 50% duty cycle and there are only odd order harmonics in its frequency content, such as,etc. As illustrated by Fig. 5, the differential pair of the injection stage functions as an RF mixer, switched by the differential oscillation signals. Under the locked condition, the injection frequency is two times the oscillation frequency. Therefore, all of its harmonics are thus equivalent to even order harmonics as far as the oscillation signal is concerned, i.e.,, etc. After the mixing, they are all converted to odd order harmonics, and there will be insignificant even order harmonic components that could survive at the

3 LU et al.: QUADRATURE LOCAL OSCILLATOR FOR COGNITIVE RADIO APPLICATIONS 1133 Fig. 7. DC offset caused by non-50% duty cycle in differential signal. Fig. 5. Harmonic contents of the ILRO under locked condition. Fig. 8. Quadrature phase mismatch versus compensation current added to Stage-I. Fig. 6. Output quadrature phase mismatch versus input duty cycle. output. Consequently, the output duty cycle is well retained at 50%. In this regard, this ILRO differs from the one proposed in [5], which injects input signal directly to output through a parallel differential pair and the duty cycle of the output signal would be affected directly by its input duty cycle. 2) Quadrature Output Phase Mismatch Is a Very Weak Function of Input Duty Cycle: Provided device mismatch is not considered, the output quadrature mismatch is zero when the injection signal has 50% duty cycle. When the duty cycle deviates from 50%, it degrades the quadrature matching, but only to a limited extent. This is fundamentally different from a typical divide-by-2 circuit. Fig. 6 shows the simulated phase mismatches versus the input signal duty cycle in both quadrature generation approaches. As it indicates, ILRO s phase mismatch is substantially lower than that of divide-by-2 when input duty cycle deviates from 50%. Fig. 6 also shows that larger injection power also results larger quadrature mismatch, which will be explained shortly. The latch in the divider is a digital circuit, which relies on the input clock to force transitions between two clearly defined logic states: passing and latching. The divide-by-2 s output transitions follow the correspondent input clock s transitions with a fixed propagation delay, as depicted in Fig. 3. Therefore, the output phases are directly correlated to the input duty cycle. On the other side, the ILRO is an oscillator that does not require strong injection power. The phase delay of the injection stages changes with the both frequency and amplitude of the injection signal until their frequency locks, as explained in [7]. The even order harmonics in the injection signals are supposedly the main contributor to the phase mismatch. However they are firstly converted to higher order harmonics in the oscillation Fig. 9. Fig. 10. (a) Topology and (b) Waveforms of a divider-by-3 circuit. Architecture of 5 10 GHz quadrature LO. loop by the mixing effect, and then attenuated significantly by the filtering effect of the ring oscillator loop. Therefore, their contribution to phase mismatch is substantially reduced. Another main contributor of the quadrature mismatch is the bias current difference between Stage-I and Q, which is caused by non-50% duty cycle in the injection current and, as illustrated in Fig. 7. The DC bias current offset in turn affects the delay of Stage-I and Stage-Q, causing quadrature phase mismatch. Since the DC offset also increases proportionally with injection power, larger injection power results worse quadrature mismatch, as also shown in Fig. 6. Accordingly, a small adjustment to the bias current of one injection stage can mitigate the phase mismatch effectively. Fig. 8 shows the phase mismatch versus the bias current adjustment in simulation. In practice, since the output duty

4 1134 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012 Fig. 11. The LC-VCO and buffer. cycle is known and deterministic for a specific LOdivider design, it is straightforward to find the optimum bias current. An example of schematic implementation is also shown for the conceptual design in Fig. 4. The compensation current can be set by configuring the size of transistor Mc. However, the test chip presented in this work does not have this feature since it was not understood at the time of the tape-out. 3) Frequency Doubler Can be Embedded Without Cost: Under the locking condition, the output frequency would only be one half of the input frequency, which is similar as that of a divide-by-2 operation. However in the LO frequency extension circuit, the preceding programmable divider often provides two signals that can be combined by a logic gate to obtain a doubled frequency. Take the divider-by-3 in Fig. 9 as an example: both and have 33% duty cycle, and they can double the input frequency through logic OR operation. In the proposed ILRO, such a logic gate can be embedded into bias circuits without consuming additional current, which simplifies the design and saves power. In summary, using source-injected ILRO for generating quadrature phase outputs can greatly simplify the LO frequency extension circuit design by eliminating power hungry DDC circuits and frequency doublers. Further details on circuit designs will be discussed in the next section. III. LO CIRCUIT DESIGN The 5 10 GHz LO design starts with designing the LC-VCO whose tuning range is required to cover 13.3 to 20 GHz (50% FTR). As shown in Fig. 10, divide-by-2 and divide-by-3 circuits are employed in parallel after the LC-VCO to produce GHz and GHz respectively. Since the LC-VCO s output has 50% duty cycle, the divide-by-2 circuit inherently provides quadrature signals with a 50% duty cycle, while the divide-by-3 circuit would require the source-injected differential ILRO in subsequence to achieve the same. Under such a design, the ILRO is also relaxed to cover only 25% of the FTR and there is no further need of power hungry DDC or explicit frequency doubler, which renders the structure very simple and efficient. The building block designs will be described as follows. A. VCO and Buffer Fig. 11 shows the schematic of the LC-VCO. The negative transconductance is provided by an nmos cross-coupled pair. A tail resistor is chosen as the current source because of its low flicker noise. The supply voltage for the cross-coupled pair is 0.65 V and is separated from the general 1 V supply that is shared with other circuit blocks. The resonator consists of a differential inductor ( nh), a pair of AC coupled accumulation mode varactors and a switchable capacitor bank that contains seven pairs of accumulation mode varactors. The quality factor of the resonator is about 8 at 20 GHz, and it is mainly limited by the varactors. Achieving wide VCO tuning range is one of the major challenges of LO design. The VCO oscillation frequency is estimated by,where all component values are taken single-ended for consistency. represents the total parasitic capacitance for all of the passive and active devices. As can be seen, wide tuning range comes from large ratio. The accumulation mode varactor exhibits minimum capacitance in strong depletion mode when its source-gate voltage is sufficiently positive. It reaches maximum capacitance in deep accumulation mode when is sufficient negative. In today s deep sub-micron CMOS technology, the supply voltage is generally

5 LU et al.: QUADRATURE LOCAL OSCILLATOR FOR COGNITIVE RADIO APPLICATIONS 1135 Fig. 13. NMOS varactor capacitance and Vsg versus tuning voltage. Fig. 12. DC Voltage transfer curve of the Vtune converter. around 1 V. With the single-ended tuning scheme, one terminal of the varactor is connected to the port and the other to a fixed bias voltage (typically half of the supply). The absolute value of is less than half of the supply, which is usually insufficient to reach the maximum or minimum limit of the varactor capacitance. With a differential tuning scheme, both terminals are tuned simultaneously in opposite directions. The absolute value of can be as large as the supply voltage. One of the challenges with the differential tuning scheme is the generation of the differential voltages. Differential PLL charge pumps and loop filters are avoided because of their cost overhead. Voltage converters with Op-amps exhibit significant output noise that will adversely affect the VCO phase noise. We propose a new voltage converter to generate the complementary voltage of [8]. Its topology resembles an inverter except that there are two resistors in series with the drains of both transistors. The resistors take away voltage headroom from both pmos and nmos and force them to operate mostly in the triode mode. Large W/L ratios for both transistors are needed (100 nforpmosand40 n for nmos in this design) to minimize their turn-on resistance in the triode mode and reduce their out noise. Small resistor contributes less noise; however it will consume more current. In this design the resistor value is set to 1 KOhm, which does not affect the VCO phase noise significantly. As shown in Fig. 12, the resulting curve is flat in the middle where both nmos and pmos are in triode mode, and it is sharper when is either low or high where either nmos or pmos is in the subthreshold mode. With such characteristic, this voltage converter is able to extend the linear region of the varactor s C V curve. Fig. 13 compares the C V curves of the same varactor with both differential and single-ended tuning schemes. The differential scheme has a of 4.9, 30% larger than that of the single-ended scheme. Even in the presence of the parasitic capacitance that decreases the tuning range, simulation shows that the overall FTR of the VCO is increased by 7 8% by using the differential approach over its single-ended counterpart. The VCO buffer uses positive feedback to boost the output swing. The drain signal of one end is AC-coupled to the source of a common-gate stage, which enhances the output swing. With the same bias current, the single-ended output swing of the buffer loaded by subsequent circuits is increased from 0.14 V to 0.2 V by the feedback at 20 GHz, a 3 db improvement. B. Frequency Dividers and Multiplexers Figs. 3 and 9 illustrate the circuit structure of divide-by-2 and 3. The latch, multiplexer and AND gate used in the frequency extension circuit are all designed with current mode logic (CML), as shown in Fig. 14. Each of them possesses 250 load resistors and consumes about 1.4 ma of current under a 1 V supply voltage. The AND gate is designed to achieve the same input loading and propagation delay for A and B. Due to its differential nature, the CML circuit does not suffer unbalanced rising and falling edges as a single-ended circuit does. C. Injection-Locked Ring Oscillator Fig. 15 shows the schematic of the differential ILRO. It has four stages. The load resistor of each stage is about 250 Ohm and the load capacitors are also switched in conjunction with VCO s sub-band selection. This effectively reduces the required locking range for each band. Both nmos and pmos OR gates for frequency doubling are embedded into the bias current sources. As illustrated in the figure, nmos OR gate takes and from divide-by-3 circuit and convert them to current,andthepmosorgateworkswith and instead and enables to be differential to,which is important to keep a good quadrature phase matching. The pmos OR gate consumes an extra 0.8 ma overhead current. Note that the OR function does not change the duty cycle in this case. IV. MEASUREMENT RESULTS A prototype quadrature-phased LO has been implemented in 65 nm CMOS. As shown in Fig. 16, it contains a 5 10 GHz quadrature LO (Fig. 9), a divide-by-4 and a differential to singleended buffer for both I and Q channels. The VCO and buffer

6 1136 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012 Fig. 14. Schematics of (a) Latch, (b) Multiplexer, and (c) AND gate. Fig. 15. Schematic of the differential ILRO.

7 LU et al.: QUADRATURE LOCAL OSCILLATOR FOR COGNITIVE RADIO APPLICATIONS 1137 Fig. 16. Die photo of the prototype. TABLE I CURRENT CONSUMPTION OF EACH LO BLOCK occupy a total area of um, and the frequency extension circuit, including divide-by-2 and 3, ILRO and multiplexers, occupies um. Table I summarizes the current consumption of each block under a 1 V supply. Fig. 17(a) shows the output phase noise profile when ILRO is locked at the 6.44 GHz ( GHz) and (b) shows the spectrum content. The spectrum has a noise floor of dbc and contains only higher order harmonics but no visible spurs. As discussed in [9], the divide-by-4 circuit in the test driver may improve signal to spur ratio by 18 db, therefore theoretically any spur below dbc might have been buried under the noise floor. However, unlike fraction mode injection-locking frequency dividers/multipliers (ILFD/Ms) and SSBM that have issues with spurs [3], integer mode ILRO (or ILFD) does not, because there is no mechanism to generate frequency components other than harmonics. Therefore, we believe this ILRO is free of spurs. Note that the spectrum does not have relationship with the duty cycle of the ILRO because of the divide-by-4 circuit in the test driver. The duty cycle could not be measured from this test chip. Fig. 18 plots the LO frequency coverage and phase noise at both 100 KHz and 1 MHz offset frequencies. Each line segment on the chart represents a VCO band with V tuning voltage. The VCO actually covers GHz (a 52% FTR), with the absolute frequencies higher than simulation results; and the LO consequently covers GHz with the frequency extension. In general, at the same VCO frequency, the divide-by-3 path generally exhibits less phase noise than the divide-by-2 path due to higher division ratio. It also confirms that the locked ILRO contributes less noise than the VCO. Since the phase noise is referred to the LO output instead of the chip final Fig. 17. (a) Phase noise profile and (b) spectrum measured when GHz. Fig. 18. Phase noise versus LO frequency. output, 12 db has been added to account for the effects from divide-by-4 circuit embedded in the test driver. Fig. 19 plots the measured LO quadrature mismatch from one sample, which is about 2 and 2 4 for the divide-by-2 path and the divide-by-3 path respectively. They are acceptable by most today s RF systems with quadrature calibration functions in the demodulation [10]. Table II compares this work with other state-of-the-arts that produced wide tuning range quadrature LOs up to 10 GHz. This work achieves 3 9 db better phase noise, the lowest power consumption and at least 50% saving in the die area. V. CONCLUSION This paper presents a compact and low power quadrature LO with continuous 5 10 GHz frequency coverage. It achieves

8 1138 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012 TABLE II COMPARISONS WITH THE STATE-OF-THE-ARTS Fig. 20. Pulse signal with duty cycle. more efficient in power consumption, by using only integer frequency dividers and ILRO. Fig. 19. Quadrature mismatches versus LO frequency. APPENDIX worst-case phase noise of dbc/sqrt(hz) at 1 MHz offset frequency. When implemented in 65 nm CMOS, it occupies less than 0.11 mm silicon area and consumes at most 22 ma of current under 1 V power supply. The design is well-suited for cognitive radio applications. This work has two main contributions to the wideband LO design. First, it proposes an internal tuning voltage converter that enables a differential tuning scheme for the accumulation mode varactors. It maximizes the ratio of varactors and improves the overall FTR to more than 50% for a single LC-VCO operating around 20 GHz. Second, it discovers and fully utilizes unique characteristics of the source-injected differential ILRO for generating quadrature phases: both output 50% duty cycle and quadrature matching can be well maintained even with the input signal s duty cycle deviating from 50%. Consequently, LO frequency extension circuit can be made simpler in architecture and The LO duty cycle issue is mostly tackled in the time domain, e.g., by adjusting DC offsets or changing signal slopes [14]. This section first points out the relationship between the duty cycle and even order harmonics of a periodic pulse signal. It leads to frequency domain approaches for the duty cycle correction, whicharesimpleandmoreefficient than the time domain counterpart. For waveform shown in Fig. 20, its Fourier series can be expressed as where,and. Therefore, the amplitude of the nth harmonic is From (A.2), we can make the following observations: (A.1) (A.2)

9 LU et al.: QUADRATURE LOCAL OSCILLATOR FOR COGNITIVE RADIO APPLICATIONS 1139 Fig. 21. versus duty cycle. 1) When %.This means when the duty cycle is 50%, there is no even order harmonics. 2) Let s define the ratio between the second order and fundamental tones as (A.3) Fig. 21 plots the versus duty cycle. We find that their relationship is continuous and monotonic. In a source-injected ILRO, the 4th order harmonic and above are generally suppressed significantly in the delay stages. Therefore, with the above observations, we can conclude that it is the even order harmonics (especially the 2nd order harmonic) that deviate the duty cycle from 50%. This induces a new approach, suppressing or removing the second order harmonic to correct the duty cycle. can be used as an indicator to guide the design for duty cycle correction. For example, the input duty cycle is 40%, suggesting db according to Fig. 21. In order to achieve at better than 49% duty cycle ( db), the system needs to suppress the 2nd order harmonic by another 25 db. In this work, the even order harmonics are suppressed by injection stage s mixing effect, which is more effective than that of a filtering effect. Compared with time domain approaches, frequency domain analysis is more efficient in tackling the duty cycle issue, which is particularly useful in understanding the ILRO of this work. [7] S.Verma,H.R.Rategh,andT.H.Lee, Aunified model for injectionlocked frequency dividers, IEEE J. Solid-State Circuits, vol. 38, no. 6, pp , Jun [8] J. Lu, N. Wang, and M. F. Chang, GHz LC-VCO in 65 nm CMOS technology for wideband applications, Electron. Lett., vol. 47, no. 6, pp , Mar. 17, [9] A. Ismail and A. A. Abidi, A 3.1- to 8.2-GHz zero-if receiver and direct frequency synthesizer in m SiGe BiCMOS for mode-2 MB-OFDM UWB communication, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp , Dec [10] Q. Gu, RF System Design of Transceivers for Wireless Communications. New York: Springer, 2005, pp [11] S. Rong and H. C. Luong, A 0.05-to-10 GHz 19-to-22 GHz and 38-to-44 GHz SDR frequency synthesizer in 0.13 mcmos, in Proc. IEEE ISSCC Dig. Technical Papers, 2011, pp [12] B. Razavi, Multi-decade carrier generation for cognitive radios, in Proc. IEEE Symp. VLSI Circuits, Jun. 2009, pp [13] P. Nuzzo, K. Vengattaramanem, M. Ingels, V. Giannini, M. Steyaert, and J. Craninckx, A GHz dual-vco software-defined frequency synthesizer in 45 nm digital CMOS, in Proc. IEEE RFIC Symp. Dig., Jun. 2009, pp [14] W.J.DallyandJ.W.Poulton, Digital Systems Engineering. Cambridge, U.K.: Cambridge Univ. Press, 1998, p Jianhua Lu (M 10) received the B.S. and M.S. degree from Southeast University, Nanjing, China, in 1998 and 2000, respectively, and the Ph.D. degree from University of California at Los Angeles (UCLA) in 2011, all in electrical engineering. He was with the Institute of RF-& OE-ICs of Southeast University as Research Assistant from 2000 to 2002, Conexant System, San Diego, CA, from 2004 to 2008 and NXP Semiconductors, San Diego,CA,from2008to2011asanRFICdesign engineer. He is currently with Peregrine Semiconductor, San Diego, CA. His research interests include high frequency and wide bandwidth integrated circuits in CMOS, bipolar and SOI. Ning-Yi Wang received the B.S., M.S., and Ph.D. degrees in electrical engineering from University of California at Los Angeles (UCLA) in 2003, 2007, and 2011, respectively. He is currently with Broadcom Corporation, Irvine, CA. His research interests include V-band low noise and low power receiver frontend design, and high-speed, high resolution digital-to-analog converter design. ACKNOWLEDGMENT The authors are grateful to the excellent foundry wafer fabrication of TSMC and the gift support of Wintek Corporation. REFERENCES [1] J. Mitola, Cognitive radio for flexible mobile multimedia communications, in Proc. IEEE Int. Mobile Multimedia Conf., Nov. 1999, pp [2] A.D.Berny,A.M.Niknejad,andR.G.Meyer, A1.8-GHzLC VCO with 1.3-GHz tuning range and digital amplitude calibration, IEEE J. Solid-State Circuits, vol. 40, no. 4, pp , Apr [3] Y. Ito, H. Sugawara, K. Okada, and K. Masu, A 0.98 to 6.6 GHz tunable wideband VCO in 180 nm CMOS technology for reconfigurable radio transceiver, in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2006, pp [4] D. Guermandi, P. Tortori, E. Franchi, and A. Gnudi, A GHz continuously tunable quadrature VCO, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp , Dec [5] P. Kinget, R. Melville, D. Long, and V. Gopinathan, An injectionlocking scheme for precision quadrature generation, IEEE J. Solid- State Circuits, vol. 37, no. 7, pp , Jul [6] J. Lu, N. Wang, and M. F. Chang, A single-lc-tank 5 10 GHz quadrature local oscillator for cognitive radio applications, in IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2011, pp Mau-Chung Frank Chang (M 79 SM 94 F 96) received the B.S. degree in physics from National Taiwan University, Taipei, Taiwan, in 1972, the M.S. degree in material science from National Tsing Hua University, Hsinchu, Taiwan, in 1974, and the Ph.D. degree in electrical engineering from National Chiao Tung University, Hsinchu, Taiwan, in He is the Wintek Endowed Chair and Distinguished Professor of Electrical Engineering and the Chairman of the Electrical Engineering Department, University of California at Los Angeles (UCLA). Before joining UCLA, he was the Assistant Director and Department Manager of the High Speed Electronics Laboratory at Rockwell Science Center ( ), Thousand Oaks, California. In this tenure, he developed and transferred the AlGaAs GaAs Heterojunction Bipolar Transistor (HBT) and BiFET (Planar HBT/MESFET) integrated circuit technologies from the research laboratory to the production line (now Conexant Systems and Skyworks). The HBT/BiFET productions have grown into multi-billion dollar businesses and dominated the cell phone power amplifiers and front-end module markets (currently exceeding one billion units/year). Throughout his career, his research has primarily focused on the development of high-speed semiconductor devices and integrated circuits for RF and mixed-signal communication and imaging system applications. He was the principal investigator

10 1140 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012 at Rockwell in leading DARPA s ultra-high-speed development for direct conversion transceiver (DCT) and digital radar receivers (DRR) systems. He was the inventor of the multiband, reconfigurable RF-Interconnects, based on FDMA and CDMA multiple access algorithms, for ChipMulti-Processor (CMP) inter-core communications and inter-chip CPU-to-Memory communications. He also pioneered the development of world s first multi-gigabit/sec ADC, DAC and DDS in both GaAs HBTs and Si CMOS technologies; the first 60 GHz radio transceiver front-end based on transformer-folded-cascode (Origami) high-linearity circuit topology; and the low phase noise CMOS VCO with Digitally Controlled on-chip Artificial Dielectric (DiCAD). He was also the first to demonstrate CMOS oscillators in the Terahertz frequency spectrum (1.3 THz) and the first to demonstrate a CMOS active imager at the sub-mm-wave spectra based on a Time-Encoded Digital Regenerative Receiver. He was also the founder of an RF design company G-Plus (now SST Communications) to commercialize WiFi 11 b/g/a/n power amplifiers, front-end modules and CMOS transceivers. Dr. Chang was elected to the U.S. National Academy of Engineering in 2008 for the development and commercialization of GaAs power amplifiers and integrated circuits. He was also elected as a Fellow of IEEE in 1996 and received IEEE David Sarnoff Award in 2006 for developing and commercializing HBT power amplifiers for modern wireless communication systems. He was the recipient of 2008 Pan Wen Yuan Foundation Award and 2009 CESASC Career Achievement Award for his fundamental contributions in developing AlGaAs GaAs heterojunction bipolar transistors. His recent paper CMP Network-on-Chip Overlaid with Multiband RF-Interconnect was selected for the Best Paper Award in 2008 IEEE International Symposium on High-Performance Computer Architecture (HPCA). He received Rockwell s Leonardo Da Vinci Award (Engineer of the Year) in 1992; National Chiao Tung University s Distinguished Alumnus Award in 1997; and National Tsing Hua University s Distinguished Engineering Alumnus Award in 2002.