A -Band CMOS Transmitter With IF-Envelope Feed-Forward Pre-Distortion and Injection-Locked Frequency-Tripling Synthesizer

Transcription

1 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 12, DECEMBER A -Band CMOS Transmitter With IF-Envelope Feed-Forward Pre-Distortion and Injection-Locked Frequency-Tripling Synthesizer Adrian Tang, David Murphy, Frank Hsiao, Gabriel Virbila, Yen-Hsiang Wang, Student Member, IEEE, Hao Wu, Yanghyo Kim, and Mau-Chung Frank Chang, Fellow, IEEE Abstract A -band CMOS transmitter is presented with an integrated injection-locked frequency-tripling synthesizer, digital control, and an on-chip antenna. It employs an IF feed-forward pre-distortion scheme, which improves gain compression of the transmitter to provide an overall higher linearity gain profile, allowing reduced power back-off for higher peak-to-average modulation schemes. The integrated -band transmitter consumes 347 mw and occupies m of silicon area. The proposed transmitter delivers 0.4 dbm of effective isotropic radiated power with a saturated power on-chip of at least 12.2 dbm. The transmitter has a peak power-added efficiency (PAE) of 4.8% with power delivered to the antenna and a peak PAE of 0.31% when considering radiated power. Index Terms -band transmitter, digital-controlled millimeter wave, feed-forward linearization, on-chip antenna. I. INTRODUCTION R ECENT advances in silicon technology have enabled the possibility of CMOS-based gigabit/second rate millimeter-wave transceivers beyond the 100-GHz frequency range [1] [3] While digital and mixed-signal techniques to support gigabit/second communications are quite mature, the design of RF front-ends beyond -band is a relatively new topic. Design of power amplifiers (PAs) that deliver enough output power to maintain the required link signal-to-noise ratio (SNR) is challenging, especially at frequencies approaching 150 GHz as the available device gain is low. One difficult challenge of CMOS millimeter-wave transmitters operating beyond 50 GHz is that amplifier compression is quite soft [4]. This means that the gain begins to compress at signal levels far below saturation. Power-amplifier compression directly contributes to the transmitter s overall AM AM characteristic, a major source of error-vector magnitude (EVM) degrada- Manuscript received July 07, 2012; revised September 18, 2012; accepted September 27, Date of publication November 19, 2012; date of current version December 13, This paper is an expanded paper from the IEEE MTT-S International Microwave Symposium, Montreal, QC, Canada, June 17 22, A. Tang was with the Department of Electrical Engineering, University of California at Los Angeles (UCLA), Los Angeles, CA USA. He is now with the Jet Propulsion Laboratory (JPL), Pasadena, CA USA. D. Murphy is with the Broadcom Corporation, Irvine, CA USA. F.Hsiao,G.Virbila,Y.-H.Wang,H.Wu,Y.Kim,andM.-C.F.Changare with the Department of Electrical Engineering, University of California at Los Angeles (UCLA), Los Angeles, CA USA. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TMTT Fig. 1. (a) Typical gain compression profile for a CMOS millimeter-wave PA as bias current is increased. (b) Proposed compression profile showing intentionally removed gain at small-signal levels and dynamic biasing. tion and lowered bit-error-rate performance, especially when modulations with high peak-to-average ratios are used. While digital-pre-distortion (DPD) is common at lower frequencies, the high symbol rate and wide channel bandwidth of gigabit/second millimeter-wave communication makes implementation increasingly difficult due to the need for wideband matching and high-speed digital-to-analog converters (DACs). The local oscillator (LO) remains another critical source of error vector magnitude (EVM) degradation in gigabit/second communications where the integrated phase across relatively wide channels leads to large rotations of the signaling constellation. While the carrier frequency is quite high, the available reference frequencies from crystal oscillators remain quite low, leading to large phase multiplication factors, making the design of low phase-noise frequency synthesizers challenging beyond -band ranges. II. DYNAMIC BIASING IN CMOS PAS Fig. 1(a) shows the gain compression profile for a typical CMOS millimeter-wave PA as the static dc bias current is increased. While the saturated power does increase as the dc bias current is raised, the back-off point where the compression begins remains almost constant, and limits the linearity improvement that can be achieved. Instead of adjusting the bias to a fixed value, we propose to construct the transmitter with the compression profile that is shown in Fig. 1(b). By intentionally removing some of the small-signal gain and then adjusting the bias dynamically based on the signal s power envelope, the linear range of the PA can be artificially increased, allowing operation to occur closer to the saturated power level. Previously, this dynamic bias behavior was achieved using the architecture shown in Fig. 2 [5]. In this scheme, an envelope detector is used at the output of the PA and a dynamic bias /$ IEEE

2 4130 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 12, DECEMBER 2012 Fig. 2. Dynamic biasing approach from [2] where an envelope detector is used at the PA output to produce a dynamic bias signal. Fig. 3. Block diagram of the proposed IF feed-forward dynamic biasing millimeter-wave transmitter chain showing feed-forward pre-distortion block. signal is derived from the detector output to compensate for the amplifier compression. While this approach performs well at the industrial scientific medical (ISM) 60-GHz band application in [2] with a 1-GHz channel, the limited time constant of the feedback loop makes it difficult to achieve large bandwidths at -band, and also makes the feedback stabilization more difficult, as -band PAs typically have a larger number of stages. We propose to instead employ a feed-forward architecture to overcome the difficulties associated with placing a feedback loop around the PA. III. PROPOSED TRANSMITTER CHAIN Fig. 3 shows the block diagram of the millimeter-wave transmitter chain and integrated frequency synthesizer with the proposed feed-forward pre-distortion scheme. In this architecture, the IF signal can be fed in from an external source or the transmitter can be used for direct conversion double-sideband (DSB) modulations. In this transmitter, a five-stage PA brings the transmitted signal up to full power 12 dbm for transmission by the antenna. The first four stages of the PA are controlled by calibration DACs, which can set the bias current level of each stage. Each DAC is a simple resistor-to-resistor (R2R) configuration with 8 bits of resolution. Since the DACs only provide dc control levels, the dynamic performance (signal-to-noise plus distortion ratio) is not critical and the RC time constants can be made large to save power. Additionally since the PA s sensitivity to the static bias is limited, the DACs do not require a high degree of static matching, and thus integrated and differential nonlinearity beyond 4 5 least significant bits (LSBs) can be tolerated. The IF feed-forward pre-distortion block first takes the magnitude of the IF signal using an envelope detector, then adjusts the detector s output with gain and offset properties to provide the dynamic biasing signal to the output stage of the PA. It also contains two DACs, one for the offset adjustment and the other for the gain adjustment. While in this prototype architecture we use a single DSB IF to make testing easier, it is readily adaptable to quadrature IF architectures [in-phase/quadrature (IQ)] by having two pre-distortion blocks for I and Q channel and then summing the resulting signals. Fig. 4 contains the IF feed-forward pre-distortion circuit used to cancel the soft compression of the PA. The circuit first employs an envelope detector composed of Q1 and Q2 and loaded by current mirror Q4 Q5 to extract the envelope of the IF signal. Device Q3 is controlled by the Gain DAC and steals a percentage of the current away from the current mirror to provide gain control of the envelope signal. Since the output of the current mirror is single ended, the dc common mode (CM) cannot be extracted by conventional differential approaches, and using an RC filter would require large capacitor area for the time constants involved. Instead we use the replica circuit shown on the right of Fig. 4 that has a dc voltage tracked by the op-amp. The output stage of the op-amp is duplicated by Q6 and Q7, which sets the dc voltage at the output of the pre-distortion block. The dc voltage is selected from the offset DAC by providing the tracking reference voltage to the opamp. When the IF input signal is small, the added offset voltage is much larger than the envelope detector output, and thus the offset DAC dominates the shaping of the PA compression at low output powers. When the IF swing is large, the envelope detector output is much larger than the offset and thus the gain DAC dominates the shaping of the PA compression at high power levels. This allows two degrees of freedom to tune the shape of the PA s compression. The envelope detection circuit and its replica must be symmetric in layout to obtain the necessary matching. As the pre-distortion block is digitally programmable over a wide range of gains and offsets, its own path linearity has a little impact on the final optimized transmitter linearity. Also, as the gain stage in the pre-distortion block is implemented as a current mirror, as opposed to a voltage mode amplifier, the distortion levels remain low at the cost of some power consumption. Fig. 5 shows the schematic of the transmitter mixer and the millimeter-wave PA in which all stages are transformer coupled. The compensation signal for the fifth stage of the PA and DAC generated bias voltages on stages 1 4 are fed through the center-tap of the winding connected to the input of each stage. This allows modulation of the bias without disturbing the differential-mode RF signals. Also shown are the internal structure of the R2R DACs, and all RF device dimensions in micrometers. All RF devices have 65-nm channel lengths. Transformer-based coupling also offers the advantage that the stages are not dc coupled, making the transmitter inherently stable close to dc. The

3 TANG et al.: -BAND CMOS TRANSMITTER 4131 Fig. 4. Schematic diagram of the pre-distortion block showing dc replica circuit and calibration DACs. Fig. 5. RF mixer and PA schematic showing transformer coupling for RF connections and center-tap coupling for IF feed-forward signal connections and DAC bias voltage connections. Fig. 7. Cascaded divider PLL for -band requiring three different injection locked dividers (A, B, C) in cascade to provide a low enough frequency input to the CML programmable divider. and impedance matching. The resistivity of the silicon is approximately 10 cm based on foundry models. While the authors are unable to measure the radiated pattern, the simulated directivity of the antenna is 6 dbi including feed-line and substrate losses. Fig. 6. On-chip half-wave patch antenna and dimensions. Impedance matching balun is also shown. LO input of the mixer is also transformer coupled and the CM voltage on the LO port of the mixer is programmable via an additional R2R DAC. The transmitter antenna is implemented as a half-wave patch antenna placed directly over the substrate, asshowninfig.6,andcoupledtothepausinganon-chip balun, which provides differential to single-ended conversion IV. FREQUENCY MULTIPLIED SYNTHESIZERS The -band (42 48 GHz) phase-locked loop (PLL) previously presented in [6] for 60-GHz applications uses an injection-locked divider and injection-locked output buffer in conjunction with a current-mode logic (CML) programmable frequency divider. Tuning for the divider, an injection-locked buffer and a primary voltage-controlled oscillator (VCO) are controlled by digitally controlled artificial dielectric (DiCAD) elements [7]. While this architecture delivers excellent performance at GHz, it becomes problematic as the frequency is increased up to -band since the maximum input frequency of the CML-based programmable divider is limited to 25 GHz at most in 65-nm CMOS technology. As shown in Fig. 7, using a regular cascade of injection-locked frequency dividers (ILFDs) for -band would require at least three ILFD stages to divide the -band carrier signal down to a frequency that the CML can readily accept 25 GHz. Such a high count of slave oscillators could potentially limit the tuning range of the synthesizer and create difficulty ensuring that the frequency alignment was sufficient to maintain the locked condition. The large process variation

4 4132 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 12, DECEMBER 2012 Fig. 8. (a) Direct harmonic tripling with a millimeter-wave amplifier. (b) ILFT with an oscillator. associated with deep-sub-micrometer CMOS technology will further exacerbate the frequency alignment. An additional difficulty is that varactors provide very low- beyond 100 GHz, causing a considerable reduction in oscillator swing and potentially creating difficulties in achieving VCO startup. For this reason, high-frequency oscillators beyond -band(110ghz) typically offer very narrow tuning ranges of only 1% 2%. One common technique to overcome the challenges of frequency synthesis above 100 GHz is that of frequency multiplication. In frequency multiplication, a low-frequency synthesizer is first used to generate a stable carrier, and then the frequency is multiplied through manipulation of harmonics generated by introducing a nonlinear element. One of the most practiced frequency multiplier approaches is the direct harmonic tripler shown in Fig. 8(a). In this approach, a lower frequency millimeter-wave signal (48 GHz) is fed into a nonlinear element denoted as the 3X unit in the block diagram. The output of this block is tuned to the third harmonic, allowing extraction of the high-frequency (144 GHz) tone. The key challenge to this approach is that the generated harmonics will be at much lower voltage swings as the fundamental to harmonic conversion is quite lossy (on the order of db in the -band range). To alleviate this problem, a PA often called an LO amplifier is used to restore signal swing. While this technique is straightforward, it has the major disadvantages of large area and high power consumption as the transmitter now needs two PAs, one in the transmit chain and another in the LO chain. Alternatively, the architecture in Fig. 8(b) commonly called sub-harmonic injection locking or injection-locked frequency tripling (ILFT), proposed in [8] and recently demonstrated with excellent results at -bandin[9],usesanoscillatoroperating at three times the input frequency. The third harmonic generated in the nonlinear 3X block will injection lock the oscillator to restore the signal swing. This has the major advantage of being able to restore the voltage swing in only one stage without the associated power consumption of an additional millimeter-wave amplifier. One limitation, however, is that the injection-locked approach provides less tuning range because the locked oscillator range is relatively small, as mentioned earlier. While this is very problematic for highly channelized applica- Fig. 9. Block diagram of the proposed -band frequency synthesizer. tions such as 60-GHz communication systems, we target wideband gigabit/second single-channel communications at -band, and therefore can escape by requiring only a fixed LO. The synthesizer architecture for the proposed transmitter is showninfig.9.the architecture first uses the original -band (42 48 GHz) PLL with a 50-MHz reference and a single ILFD used to divide the carrier from 48 to 24 GHz to provide a lowfrequency input for the programmable CML divider. An injection-locked buffer is inserted between the VCO and divider and used to drive the input of a -band ILFT. Frequency alignment of the buffer is relatively easy as the frequency is identical to the VCO making the passives and devices used in both oscillators quite similar. For the -band application, the -band PLL will nominally run at GHz. The buffer drives an ILFT containing a nonlinear amplifier, which generates a large third harmonic at GHz used to injection lock an oscillator (also running at GHz). The ILFT restores signal swing and also filters out the lower GHz fundamental tone. Finally, the ILFT output is provided by a small singlestage output amplifier used to boost the LO power and isolate the oscillator s tank from the low mixer impedance. While the proposed frequency synthesizer still contains many injection-locked stages, it removes one level of injection locking versus the original cascaded divider architecture. Additionally, since the high-frequency -band components are not directly inside the synthesizer s feedback loop, the associated narrow locking range and limited output swing have little effect on the PLL s locking conditions. Since the original PLL can tune from 42 to 48 GHz, the generated third harmonic can sweep 3X this wide range ( GHz), relaxing the frequency alignment at -band. The synthesizer will lock provided the -band oscillator s free-running frequency is within this range. The only critical alignment at -band is the frequency of the output LO boosting amplifier must be well aligned with the -band oscillator s locking range to provide useful output swing necessary to drive the transmit mixer.

5 TANG et al.: -BAND CMOS TRANSMITTER 4133 Fig. 10. (a) Proposed harmonic tripler circuit with complementary diode connected devices Q1 and Q3 to improve harmonic generation. (b) Simulated output voltage spectrum with and without Q1 and Q3. V. -BAND INJECTION-LOCKED FREQUENCY TRIPLER Previously in [9], a common emitter stage using an SiGe HBT device was employed to provide the nonlinearity required to generate odd harmonics. Unlike bipolar devices, CMOS common source stages exhibit very soft-voltage waveform clipping, providing limited harmonic generation. For this reason, the harmonic generation circuit shown in Fig. 10(a) is used in the proposed -band synthesizer. The employed tripler circuit contains complementary diode connected devices Q1 and Q3 to help create waveform clipping at both the lower and upper half of the voltage swing and further increase generation of third-order harmonic distortion components. Fig. 10(b) shows the simulated spectrum at the output with and without Q1 and Q3 present. Through the added nonlinearity of Q1 and Q3, the third harmonic output voltage is increased by 11.4 db in simulation. Note that the input is from an oscillator-based buffer so the input swing approaches twice the supply voltage, causing Q3 to clamp when. Series device Q1 artificially increases the perceived of device Q2 causing distortion at the bottom of each cycle. While the output power level is small, it is still sufficient to injection lock the following -band oscillator stage. The injection-locking range of an oscillator can be described by,where is the injected current, is the oscillator current, is the center frequency, and is the quality factor of the oscillator tank. To ensure locking of the proposed -band synthesizer, we control the oscillator current with a small R2R 8-bit DAC, as shown in Fig. 11. This allows the current to be calibrated for maximum locking range while still ensuring correct startup occurs. The oscillator tank is transformer coupled to provide output to the LO booster amplifier. A second DAC provides CM control of the LO booster output via the center tap of an output transformer to provide the correct dc levels for the input port of the mixer. Note the -band oscillator contains no varactor or tuning capacitors, as their inclusion would degrade voltage swing and possibly influence oscillator startup. Also note the tuning range of the -band PLL s third harmonic ( GHz) is much wider than the actual lock range of the ILFT ( GHz measured). Fig band ILFT section of proposed synthesizer showing oscillator, control DAC for, LO booster, and DAC for CM adjustment. Fig. 12. Probe-based test chip for power measurement containing -band millimeter-wave power amplifier and -band oscillator. VI. MEASUREMENTS First, to verify the output power of the transmitter chain, a standalone chip was constructed with the millimeter-wave PA driven by the oscillator from the ILFT, as shown in Fig. 12. Since the input of the CMOS millimeter-wave PA is a voltage mode port and not matched to 50, this approach makes power testing straightforward for probe testing. An on-chip thru-line wasusedinconjunctionwitha -band source from VDI Inc., Charlottesville, VA, a PM4 power meter also from VDI Inc., and WR-6.5 probes from Cascade Microtech, Beaverton, OR, to first estimate the insertion loss of the probes and test setup. This process is illustrated in Fig. 13 and relies on two simple

6 4134 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 12, DECEMBER 2012 Fig. 13. Test setup calibration at -band for power measurement. assumptions: that test setup is symmetric, and that the insertion loss of the on-chip thru line is negligible. Since the probes and waveguide sections are identical and the thru ine is only 100 m in length, these assumptions should be valid. Once the power calibration is completed, the power from the PA can be directly measured with the Erickson meter, as shown in Fig. 14. We also show the output from the test chip on a spectrum analyzer with a -band mixer (also from VDI Inc.). Note that the output levels on the spectrum analyzer are not correctly calibrated since we are unsure of the mixer conversion loss/gain. Only the PM4 reading is valid. The spectrum analyzer is only used to confirm the power being measured is in the 145-GHz range. With the calibrated insertion loss of 4.14 db, the reading of mw (8.06 dbm) can be used to compute the actual PA output of 12.2 dbm. One uncertainty is that the oscillator output may not be completely saturating the PA, thus this test ensures that the saturated power is at least 12.2 dbm, but in fact, it may be higher. Also note that only a ground signal ground (GSG) probe was available to probe our GS pads. The calibration procedure should still take this mismatch into account, as the setup was symmetric. The reported frequency from the spectrum analyzer is GHz, 2 GHz higher than where the oscillator operates within the ILFT of the transmitter chip. The LO booster is constructed from larger devices than the first stage of the PA so the oscillator in the test-chip experiences less capacitive loading, which accounts for the frequency shift. Fig. 15 shows a die photograph of the proposed transmitter implemented in 65-nm CMOS indicating the location of key blocks. The transmitter chip is wire bonded to a printed circuit board (PCB) with the antenna surface facing in the upward direction. The PCB provides dc connectivity for supply and bias, USART connectivity for controlling the calibration DACs from a PC, and connectivity to provide the IF signal into the transmitter. In a radiation-based measurement using the same PM4 power meter as in the probe testing combined with a standard -band gain horn antenna from VDI Inc., we measured a saturated effective isotropic radiated power (EIRP) of 0.4 dbm using the calculated path loss for a distance of 5.0 cm from the chip surface and the known gain of the horn. Using the entire chip power consumption of 347 mw provides a PAE of 0.31%. Using the same setup with the same PM4 power meter, the input power at the IF of the transmitter is swept and the transmitter gain is computed at each step based on the measured EIRP and calculated path loss. Fig. 16 demonstrates the effect of changing the offset setting of the pre-distortion block on the Fig. 14. Power measurement of the standalone power testing chip containing the -band millimeter-wave PA. Fig. 15. Die photograph of the proposed millimeter-wave transmitter showing the location of key blocks and the on-chip antenna. overall gain compression while the gain setting is held at 50% of full scale. As expected, the offset setting drastically affects the small-signal gain, while having limited effect on the large-signal gains.

7 TANG et al.: -BAND CMOS TRANSMITTER 4135 Fig. 16. Radiated output power and gain compression of the proposed transmitter as the pre-distortion offset control is varied. Fig. 18. Optimized gain compression compared with a static dc bias showing a 6.5 db improvement in P1 compression point. Fig. 19. Measured carrier phase noise at transmitter chain output. Fig. 17. Radiated output power and gain compression of the proposed transmitter as the pre-distortion gain control is varied. Fig. 17 demonstrates the effect of changing the pre-distortion block s gain setting on the overall gain compression while the offset setting is held at 50% of full scale (500 mv). Also as expected, the pre-distortion gain setting has little influence on the small-signal gain (as there is not enough signal swing at the IF to affect the pre-distortion block s output voltage). The pre-distortion gain setting, however, has a large influence on the large-signal gain of the transmitter, although it is unable to change the saturated power level, slightly reducing the overall PAE. By first setting the pre-distortion offset to 850 mv and then setting the gain to zero, we can effectively bias the PA statically at 850 mv. We then compare that with optimized predistortion gain and offset settings in Fig. 18. Through the use of the proposed IF feed-forward pre-distortion scheme, we see that the P1 db point has been improved by 6.5 db. Finally, although we cannot directly access the frequency synthesizer in our design from the outside, we can measure the phase noise at the transmitter output when a large dc voltage is applied to the IF. While the transmit chain will contribute noise to the measurement, this should be far below the phase noise of the synthesizer at small frequency offsets around the carrier. Using the same WR-6.5 probes and VDI Inc. mixer as before, we directly measure the phase noise on the spectrum analyzer and plot the results in Fig. 19. In the phase-noise measurement, we see that the in-band noise is actually dominant over the noise of the injection-locked oscillator, indicating that the charge pump or phase detector noise sources may dominate in the lower -band PLL. Similar results were reported in [6], which uses a variant of the -band PLL in this study. The overall phase noise is comparable to other PLLs providing carriers in similar frequency ranges [10], [11]. VII. SUMMARY The proposed IF-envelope feed-forward pre-distortion transmitter is realized to improve the transmitter gain compression and increase the P1 compression point by 6.5 db when implemented in a 65-nm CMOS technology. The transmitter is also integrated with an injection-locked frequency-tripler-based synthesizer providing 82.5-dBc/Hz phase noise at 1-MHz frequency offset, which is suitable for wideband gigabit/second

8 4136 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 12, DECEMBER 2012 communication. Also demonstrated is a digital technique for calibration of high-frequency millimeter-wave front-ends using 8-bit DACs to adjust bias currents for optimization of stage gain. The proposed transmitter offers 15 GHz of bandwidth centered between GHz, with a saturated output power of 12.2 dbm measured, and saturated EIRP of 0.4 dbm. The entire transmitter consumes 347 mw of dc power and occupies 1800 m 1500 m of silicon area including an integrated patch antenna. When power delivered to the antenna is considered, a peak PAE of 4.8% is achieved and when EIRP is considered, the peak PAE is 0.31%. ACKNOWLEDGMENT The authors would like to acknowledge TSMC, Hsinchu, Taiwan, for their excellent 65-nm foundry support, as well as Dr. Z. Xu, HRL Laboratories, Malibu, CA, and Prof. Qun Gu, University of Florida, Gainesville, for several excellent technical discussions. Adrian Tang received the Ph.D. degree in electrical engineering from the University of California at Los Angeles (UCLA). He is currently a Postdoctoral Scholar with the NASA Jet Propulsion Laboratory, Pasadena, CA, where he is involved with working with 680-GHz imaging radars. He has coauthored over 30 papers on RF, millimeter-wave imaging, and communication systems in CMOS technology. Dr. Tang was the recipient of the 2012 Ph.D. Distinguished Ph.D. Dissertation Award of the UCLA Henry Samueli School of Engineering and the Broadcom University Research Award. David Murphy received the B.E. and M.Eng.Sc. degrees from the University College Cork, Ireland, in 2004 and 2006, respectively, and the Ph.D. degree in electrical engineering from the University of California at Los Angeles (UCLA), in He is currently a Senior Staff Scientist with the Broadcom Corporation, Irvine, CA. REFERENCES [1] N. Deferm and P. Reynaert, A 120 GHz 10 Gb/s phase-modulating transmitter in 65 nm LP CMOS, in IEEE Int. Solid-State Circuits Conf., Feb. 2011, pp [2] L. Zhou, C.-C. Wang, Z. Chen, and P. Heydari, A -band CMOS receiver chipset for millimeter-wave radiometer systems, IEEE J. Solid- State Circuits, vol. 46, no. 2, pp , Feb [3] Y.-A.Li,M.-H.Hung,S.-J.Huang,andJ.Lee, Afullyintegrated 77 GHz FMCW radar system in 65 nm CMOS, in IEEE Int. Solid-State Circuits Conf., Feb. 2010, pp [4] J.Y.-C.Liu,A.Tang,N.-Y.Wang,Q.J.Gu,R.Berenguer,H.-H.Hsieh, C. Jou, and M.-C. F. Chang, A -band self-healing power amplifier with adaptive feedback bias control in 65 nm CMOS, in IEEE RFIC Symp., Jun. 2011, pp [5] J.Y.C.Liu,Q.J.Gu,A.Tang,N.-Y.Wang,andM.C.Chang, A 60 GHz tunable output profile power amplifier in 65 nm CMOS, IEEE Microw. Wireless Compon. Lett., vol.21, no. 7, pp , Jul [6] D. Murphy, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, Z. Xu, A. Tang, F. Wang, and M.-C. F. Chang, A low phase noise, wideband and compact CMOS PLL for use in a heterodyne c transceiver, IEEE J. Solid-State Circuits, vol. 46, no. 7, pp , Jul [7] T. LaRocca, S. W. Tam, D. Huang, Q. Gu,W.Hant,andM.F.Chang, Millimeter-Wave CMOS digital controlled artificial dielectric differential mode transmission lines for reconfigurable ICs, in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2008, pp [8] S.-W.Tam,E.Socher,A.Wong,Y.Wang,L.D.Vu,andM.-C.F. Chang, Simultaneous sub-harmonic injection-locked mm-wave frequency generators for multi-band communications in CMOS, in IEEE RFIC Symp., Jun. 2008, pp [9] Z. Chen, C. Wang, and P. Heydari, -band frequency synthesis using a -band PLL and two different frequency triplers, in IEEE RFIC Symp., Jun. 2011, pp [10] K.H.TsaiandS.I.Liu, A43.7mW96GHzPLLin65nmCMOS, in IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp [11] Z. Xu, Q. Gu, Y. Wu, H. Jian, F. Wang, and F. Chang, An integrated frequency synthesizer for GHz satellite communication in 65 nm CMOS, in IEEE RFIC Symp., May 2010, pp [12] A.Tang,D.Murphy,F.Hsiao,Q.Gu,Z.Xu,G.Virbila,Y.H.Wang,H. Wu,L.Nan,Y.Wu,andF.Chang, ACMOS GHz0.4dBm EIRP TX with 5.1 db P1 db extension using envelope feed-forward compensation, in IEEEMTT-SInt.Microw.Symp.Dig., Jun. 2012, pp [13] A. Tang, D. Murphy,G.Virbila,F.Hsiao,S.-W.Tam,H.-T.Yu,Y. Kim, A. Wong, A. Wong, Y.-C. Wu, and M.-C. F. Chang, -band frequency synthesis using a -band PLL and frequency tripler in 65 nm CMOS technology, in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012, pp Frank Hsiao is currently working toward the Ph.D. degree at the University of California, Los Angeles (UCLA). His research is focused on high-speed baseband signal processing, very large scale integration (VLSI), and mixed-signal integrated circuits design. Gabriel Virbila is currently working toward the M.S. degree at the University of California at Los Angeles (UCLA). Yen-Hsiang Wang (S 10) was born in Taipei, Taiwan, on February 16, He received the B.S. degree in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, in 2008, the M.S. degree in electrical engineering from the University of California at Los Angeles (UCLA), in 2011, and is currently working toward the Ph.D. degree at UCLA. His research focuses on the design of high-performance and low-power ADCs. Hao Wu is currently working toward the Ph.D. degree at the University of California at Los Angeles (UCLA). His research concerns CMOS millimeter-wave circuit design for communication systems at 60 GHz and beyond.

9 TANG et al.: -BAND CMOS TRANSMITTER 4137 Yanghyo Kim is currently working toward the M.S. degree at the University of California at Los Angeles (UCLA). Mau-Chung Frank Chang (F 96) is currently the Wintek Endowed Chair and Distinguished Professor of Electrical Engineering and the Chairman of the Electrical Engineering Department, University of California at Los Angeles (UCLA). Prior to joining UCLA, he was the Assistant Director and Department Manager of the High Speed Electronics Laboratory, Rockwell Science Center ( ), Thousand Oaks, CA. During his tenure, he developed and transferred the Al GaAs/GaAs heterojunction bipolar transistor (HBT) and BiFET (planar HBT/MESFET) integrated-circuit technologies from the research laboratory to the production line (now Conexant Systems and Skyworks Solutions). The HBT/BiFET productions have grown into multibillion-dollar businesses and dominated the cell-phone PA and front-end module markets (currently exceeding one billion units/year). Throughout his career, his research has primarily focused on the development of high-speed semiconductor devices and integrated circuits for RF and mixed-signal communication and imaging system applications. He was the Principal Investigator with the Rockwell Science Center, where he lead the Defense Advanced Research Project (DARPA) s ultrahigh-speed ADC/DAC development for direct conversion transceiver (DCT) and digital radar receiver (DRR) systems. He invented the multiband reconfigurable RF interconnects based on FDMA and CDMA multiple access algorithms, for chip multiprocessor (CMP) inter-core communications and inter-chip CPU-to-memory communications. He also pioneered the development of the world s first multigigabit/multiseccond ADC, DAC, and DDS in both GaAs HBT and Si CMOS technologies, the first 60-GHz radio transceiver front-end based on transformer-folded-cascode (Origami) high-linearity circuit topology, and the low phase-noise CMOS VCO F.O.M. dbc/hz with digitally controlled on-chip artificial dielectric (DiCAD). Dr. Chang was elected to the U.S. National Academy of Engineering in 2008 for the development and commercialization of GaAs PAs and integrated circuits. He was the recipient of the 2006 IEEE David Sarnoff Award for the development and commercialization of HBT PAs for modern wireless communication systems.