0 Operation principle of power semiconductors

Transcription

1 0 Operation principle of power semiconductors 0 Operation principle of power semiconductors 0.1 Basic switching processes Apart from a few special applications, power semiconductors are mainly used in switching applications. This leads to some basic principles and operation modes which apply to all power electronics circuitries. The most important goal of all efforts in developing the product range of power semiconductors and their applications in circuits is to reach minimum power losses. Limit conditions for the ideal switch are characterized as follows: ideal switch - On-state: v s = 0; - < i s < - Off-state: i s = 0; - < v s < - Switching behaviour: no conversion of energy during active turn-on/ turn-off The application of such ideal switches and, consequently, the use of power semiconductors is therefore subject to restrictive switching conditions. Switches in inductive circuits (impressed current) A switch applied in an inductive circuit (Fig. 0.1) can actively be turned on, i.e. it can be turned on at any time. There is no power loss under the condition of infinite switching time, since the bias voltage may drop directly over the line inductance. If the circuit is live, turn-off is not possible without conversion of energy, since the energy stored in L has to be converted. For this reason, turn-off of the switch without any energy conversion is only possible if i s = 0. This is also called passive turn-off, since the switching moment is dependent on the current flow in the circuit. A switch that is running under these switching conditions is called zero-current-switch (ZCS). vs L i s - On-state: v s = 0; - < i s < - Off-state: i s = 0; - < v s < - Switching behaviour: active turn-on at v s > 0 passive turn-off at i s = 0 Figure 0.1 Switch in an inductive circuit 1

2 0 Operation principle of power semiconductors Switch between capacitive nodes (impressed voltage) Nondissipative turn-on of a switch under a impressed voltage is only possible if v s = 0. This is called passive turn-on, since the voltage waveform and, thus, the zero crossing is determined by the outer circuit. Active turn-off, however, will be possible at any time. Switches running under those switching conditions are called zero-voltage-switches (ZVS). i s us - On-state: v s = 0; - < i s < - Off-state: i s = 0; - < v s < - Switching behaviour: active turn-off at i s > 0 passive turn-on at v s = 0 Figure 0.2 Switch between capacitive nodes Figure 0.3 shows current and voltage waveforms during the basic switching processes described above. The use of real power semiconductors as switches will lead to the following conditions. Before active turn-on, the current-transferring semiconductor is under positive voltage. Voltage may drop, if, triggered by the controller, the current increases by a certain rate given by the turnon mechanism of the power semiconductor. This turn-on mechanism together with the series inductance is limiting the current rise and voltage distribution within the circuit between power semiconductor and inductance. Turn-on power losses of the given power semiconductor are diminished to a minimum value by increase of inductance. During passive turn-off of a live power semiconductor carrying current in positive direction, current drops to zero due to the voltage polarity of the outer circuit. Current is conducted back as reverse current by the charge carriers still stored in the semiconductor until the semiconductor has recovered its blocking capability to take up the negative circuit voltage. Active turn-off of a live power semiconductor will, first of all, produce a voltage rise in positive direction triggered by the controller. Then, the effective parallel capacitance will take over the current flow given by the turn-off mechanism of the power semiconductor. The energy loss caused by the turn-off procedure is reduced by the increase of capacitance for the given power semiconductor. A passively switched power semiconductor is under negative voltage before turn-on. If this voltage changes polarity due to processes in the outer circuit, the power semiconductor will take up current in positive direction, which will lead to turn-on overvoltage in case of impressed current rise. 2

3 0 Operation principle of power semiconductors Switching Process Waveform Equivalent Circuit i S active ON Vq V S i S V S d is dt > 0 ; dv S dt < 0 V q V q > 0 i S i S passive OFF V S d i S < 0 dt ; dv S dt < 0 V S V q V q V q < 0 V S active OFF i S V S i S d i S < 0 dt ; dv S > 0 dt i q V S passive ON i q i S i S d i S > 0 dt ; dv S > 0 dt V S i q Basic Switching Processes Figure 0.3 Basic switching processes Every power electronic system works according to two basic function principles: firstly, turn-on and turn-off of connection leads between energy exchanging circuitries by means of one switch each - called cyclic switching of single switches and secondly, alternating switching of two switches each, alternating current- and voltagecarrying - called commutation. Both basic principles may be integrated into one circuit and the circuit split into several different operation modes. 3

4 0 Operation principle of power semiconductors 0.2 Operation principle of power semiconductors The operation principle of power semiconductors is clearly defined in the previously explained active and passive switching procedures during cyclic switching of single switches and inductive or capacitive commutation. Figure 0.4 shows a summary of the relationships between current and voltage during the different possible switching procedures. Hard switching (HS, Figure 0.7) Hard turn-on is characterized by an almost total v K voltage drop over the current-carrying switch S 1 at a current commutation time t K causing considerable power loss peaks within the power semiconductor. Commutation inductance is at its minimum value at that moment, i.e. the turned on semiconductor determines the current increase. Current commutation is terminated by passive turn-off of switch S 2. Commutation and switching time are almost identical. In case of hard turn-off, voltage over S 1 increases up to a value exceeding voltage v K while current continues flowing. Only then current commutation is started by passive turn-on of S 2. The commutation capacitance is very low, so that the voltage increase is mainly determined by the features of the power semiconductor. Therefore, switching and commutation time are almost the same and there are very high power loss peaks within the switch. Soft switching (ZCS, ZVS, Figures 0.8 and 0.9) In the case of soft turn-on of a zero-current-switch the switch voltage will drop relatively fast to the forward voltage drop value, if L K has been dimensioned sufficiently. Thus, power losses in the switches are almost avoidable during current commutation. Current increase is determined by the commutation inductance L K. Current commutation is terminated by passive turn-off of S 2, which will cause an increase of the commutation time t K compared to the switching time t S. Active turn-off of S 1 will initialize soft turn-off of a zero-voltage-switch. The decreasing switch current commutates to the capacitance C K and initializes the voltage commutation process. C K is bigger than C Kmin, which has considerable influence on the voltage increase rate. Power losses will be reduced by the delayed voltage increase at the switch. Resonant switching (ZCRS, ZVRS, Figures 0.10 and 0.11) We are talking about resonant turn-on, if a zero-current-switch is turned on at that moment when current i L almost drops to zero. Switching losses are still reduced compared to soft switching. Since the switch cannot actively determine the time of zero-current crossing, the controllability is slightly restricted. On the other hand, we are talking about resonant turn-off of a zero-voltage-switch, if the commutation voltage almost drops to zero during the turn-off process. Once again, switching losses are reduced compared to soft turn-off of the zero-voltage-switch accepting the loss of one control possibility. Neutral switching (NS, Figure 0.12) If the switch voltage as well as the switch current are zero at the moment of switching, this is called neutral switching. This is mostly the case with the application of diodes. 4

5 0 Operation principle of power semiconductors ON OFF V V E V E V HS Hard Switching HS V V V E E V ZCS Soft Switching ZVS V V E V E V ZCRS Resonant Switching ZVRS i S E E V V V S NS Neutral Switching V NS Figure 0.4 Switching procedures (v K = driving commutation voltage, i L = load current) 5

6 0 Operation principle of power semiconductors 0.3 Power electronic switches A power electronic switch integrates a combination of power electronic components or power semiconductors and a driver for the actively switchable power semiconductors. The internal functional correlations and interactions of this integrated system determine several characteristics of the switch. Figure 0.5 shows the power electronic switch system with its interfaces to the external electric circuitry (normally high potential) and to the control unit (information processing, auxiliary power supply). The necessary potential separation is supported by optical or inductive transmitters. The possible combinations of power semiconductors differing from each other by switch current and voltage direction are shown in Figure 0.6. Galvanic Isolation Driver Power Semiconductor Devices (e.g. MOSFETs; IGBTs; Diodes) Control Unit GI1 L INT A L EXT External Snubbers C INT C EXT Power Supply GI2 L INT B L EXT Internal Parasitics Figure 0.5 Power electronic switch system On the one hand, the parameters of a complete switch result from the switching behaviour of the semiconductor which, by design of the semiconductor chips, has to be adapted to the operation mode of the whole switch. On the other hand, the driver unit is responsible for all main parameters of the switch and takes charge the most important protectional functions. 6

7 0 Operation principle of power semiconductors v S i S current-unidirectional current-bidirectional voltage-unidirectional (foward blocking) DR AGTO DR DR voltage-bidirectional ( foward and reverse blocking) DR SGTO DR DR DR SGTO DR DR DR DR DR SGTO = symmetrical GTO AGTO = asymmetrical GTO Figure 0.6 Possible combinations of power semiconductors Basic types of power electronic switches Due to the operational principles of power semiconductors, which are mainly responsible for the dominant characteristics of the circuits, power electronic switches may be split up into the following basic types. The main current and voltage directions result from individual circuit requirements. Hard switch (HS, Figure 0.7) Except for the theoretical case of pure ohmic load, a single switch with hard turn-on and turn-off switching behaviour can be used only together with a neutrally switchable power semiconductor in a commutation circuit with a minimum passive energy store (C Kmin ; L Kmin ). Compared to the neutral switch which does not have any control possibility, the hard switch may be equipped with two control possibilites, namely individually adjustable turn-on and turn-off. Figure 0.7 shows the possible switch configurations. As for the symmetrical switch arrangements, only one alternating current-carrying switch will operate acitvely with two control possibilities while the other one switches neutrally. 7

8 0 Operation principle of power semiconductors V K S 1 S 2 i L = V K S 1 S 2 i L V K S 1 S 2 i L V K i L = S 1 S 2 Figure 0.7 HS commutation circuits Zero-current-switch (ZCS, Figure 0.8) Power semiconductors in zero-current-switches are turned on actively and turned off passively. Accepting the loss of one control possibility compared to HS, active switching may proceed with considerably decreased power losses due to sufficient series inductance. Figure 0.8 shows the possible switch configurations of a ZCS in an equivalent commutation circuit, which are also applicable in circuits with cyclic switching without commutation. Such circuits are characterized by continuous inductive commutation processes, i.e. active turn-on is followed by passive turnoff. L K 2 L K2 V K S 1 i L V K i L S 1 L K2 S 2 L K2 S 2 L K2 S 1 V K i L L K2 S 2 Figure 0.8 ZCS commutation circuits 8

9 0 Operation principle of power semiconductors Zero-voltage-switch (ZVS, Figure 0.9) Zero-voltage-switches are designed in such a way that they may be turned off actively and turned on passively when the switch voltage drops to zero. Active turn-off may just cause very low losses, if the parallel capacitance has been chosen high enough. Compared to HS a decrease of power losses is possible by accepting the loss of control possibility. Figure 0.9 shows the possible switching arrangements of zero-voltage-switches in capacitive commutation circuits. However, zero-voltage-switches may also be applied in circuits without commutation, where active turn-off and passive turn-on of the same switch are alternating. V K C K 2 i L S 1 V K C K 2 i L S 1 C K 2 C S K 2 S 2 2 V K C K 2 i L S 1 C K 2 S 2 Figure 0.9 ZVS commutation circuits Zero-current-resonant-switch (ZCRS, Figure 0.10) If a zero-current-switch is controlled in such a way that active turn-on is started exactly when current is at zero-crossing, there will be no current commutation. Consequently, even if there is a minimum commutation inductance, the power losses are lower than in zero-current-switches; they are just caused by the still necessary change in charge of the junction capacitances of the power semiconductors. The further power loss reduction compared to ZCS demands, at the same time, another loss of controllability, since the turn-on moment is not controllable, but is triggered by the zero-current-crossing given by the outer circuitry. Energy flow can only be controlled indirectly with ZCRS, either conducting or rejecting several current cycles. V K S 1 i L S 2 Figure 0.10 ZCRS commutation circuit 9

10 0 Operation principle of power semiconductors Zero-voltage-resonant-switch (ZVRS, Figure 0.11) This basic type of switch is a borderline case of the ZVS. If a ZVS actively turns off exactly at zero-crossing of the applied commutation alternating voltage, the increasing switch voltage will trigger the current commutation process. Even in the case of minimum commutation capacitance power losses are reduced, however at the expense of active controllability. Indirect control is also possible with the ZVRS, if several commutation voltage cycles are connected through or rejected. S 1 V K i L = S 2 Figure 0.11 ZVRS commutation circuit Neutral switch (NS, Figure 0.12) A commutation process is finished by neutral turn-on or turn-off of a neutral switch. In this case current and voltage drop to zero. Generally, a diode already includes these features. A neutral switch with actively switchable power semiconductors owes this special features to a special driver circuit. S 1 S 1 V K i L V K i L = S 2 S 2 Figure 0.12 NS commutation circuits Figure 0.13 shows a summary of all basic types of power electronic switches. The blank squares are modifications of the basic types, which are required in almost all applications. If the resonant conditions in a circuit working with soft or resonant switches are broken, the switches will have to cope with hard switching apart from their original features (modified ZVS = MZVS; modified ZCS = MZCS), in order to keep up operation of the whole system (see also chapter 3.8). Mostly, the switches are operated in this deviating mode only for a very short time. In the case of hard active turn-off of a ZVS or hard active turn-on of a ZCS, the switches are operated as ZVHS and ZCHS, respectively. 10

11 0 Operation principle of power semiconductors OFF ON hard soft L K in Series Resonant i L = 0 neutral V S = 0 hard HS MZCS ZVHS soft C K in Parallel MZVS ZVS resonant V K = 0 ZVRS neutral i S = 0 ZCHS ZCS ZCRS NS Figure 0.13 Power electronic switches 11

12 1 Basics 1 Basics 1.1 Application fields and today s application limits of IGBT and MOSFET power modules V [V] SCR-DISCS IGBT-Modules GTO/IGCT- DISCS 10 3 Power MOSFET- Modules I [A] Figure 1.1 Application fields of the latest power semiconductors As shown in Figure 1.1, a variety of circuitries in power electronics can be produced today with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors), which were introduced into the market one by one in the mid 80 s. Compared to other switchable power semiconductors, such as conventional GTO-thyristors, these types of transistors have a number of application advantages, such as active turn-off even in case of short-circuit, operation without snubbers, simple control unit, short switching times and, therefore, relatively low switching losses. The production of MOSFETs and IGBTs is comparatively simple and favourable and can easily be managed by today s technologies in microelectronics. It was mainly due to the rapid development of IGBTs and power MOSFETs that power electronics continued open up new markets, and that their fields of application increased tremendously at the same time. Bipolar high-voltage power transistors that were still very common a few years ago, have been almost completely replaced by IGBTs. 13

13 1 Basics Most applications for currents of some 10A use transistors with silicon chips that are integrated in potential-free power modules. These modules contain one or several transistor systems, diodes adapted to the transistors (free-wheeling diodes) and, if required, passive components and intelligence, see chapter Despite the disadvantage of one-side cooling, power modules are maintaining their hold in highpower electronics against the meanwhile also available disc-cells with IGBTs and diodes, which are able to dissipate about 30 % more of the heat losses by two-side cooling. This is mainly due to integrated, tested isolation of the chips to the heatsink, possible combinations of different components in one module and low costs due to batch production, apart from their easy assembly. IGBT-modules especially, are going through a permanently successful process of market penetration accompanied by increased efficiency, withstanding the new and further development of other - competitive - power semiconductors. Today IGBT-modules are produced managing a forward blocking voltage of 6.5 kv, 4.5 kv, 3.3 kv and 2.5 kv, e.g. 3.3 kv/2.4 ka [192], [196]. IGBT converters (multi-level-switch and IGBTs in series connection) for the MW-range up to more than 6 kv supply voltage can already be produced now. MOSFETs, on the other hand, are being developed for even higher frequency applications; also in the high current range more than 500 khz can be produced with the corresponding wirings and assembly topologies. Apart from the small power application range, for which chip-on-chip solutions are gaining more and more importance, IGBT and MOSFETmodules are the basic components for the integration of complete electronic and also mechatronic systems in future. 1.2 Power MOSFET and IGBT Different structures and functional principles In the following descriptions we restrict ourselves to n-channel-enhancement power MOSFETs and IGBTs (enhancement transistors), representing the majority of transistors used in power modules. If a positive control voltage is applied, a conducting channel with electrons as charge carriers (majority carriers) is generated within the existing p-conducting silicon. Without applying a control voltage, these components would block (self-blocking). Other designs, which will not be dealt with any further in this chapter, are p-channelenhancement transistors (induction of a positively charged channel within p-silicon by applying negative control voltage/self-blocking) and n- and p-channel depletion types (depletion transistors), which turn on without applied control voltage (self-conducting). In these transistors, the control voltage generates a space charge zone that cuts off the channel and interrupts the main current flow. In most applications the vertical structures shown in Figure 1.2 and Figure 1.4 are used, where gate and source (MOSFET) or emitter (IGBT) are located on top of the chip, whereas the chip bottom serves as drain (MOSFET) or collector connection. The load current is conducted vertically through the chip outside the channel. The power MOSFETs and IGBTs shown in the sections have a planar gate structure, i.e. a lateral (horizontal) conductive channel is generated in case of on-state. The planar gate, which has been further developed to the double-implanted gate in modern highdensity transistors, is the dominating gate structure for power MOSFETs and IGBTs still today. 14

14 1 Basics However, recently developed transistors have a trench-gate-structure, with the gates integrated vertically to the structure. During on-state, a vertical channel is generated on both sides of the gate. These and other new developments not dealt with any further in this chapter will be discussed in chapter The lateral MOSFET- and IGBT-structures taken over from microelectronics also have their drain- or collector layer allocated on their chip surface as n+-(mosfet) or p+-well. Load current is conducted horizontally through the chip. Since the n-zone can be isolated to the ICsubstrate by an oxide layer, several isolated MOSFETs or IGBTs may be integrated together with other structures on one chip. Due to the fact that lateral transistors are only able to generate a current density of about 30 % of that in vertical structures and, thus, require more space on the assembly, they are used preferably in complex, monolithic circuits. The structural design of the power MOSFET (Figure 1.2) as well as the IGBT (Figure 1.4) consists of a silicon-micro-cellular structure of up to 820,000 cells per cm 2 (latest high-tech 60 V-MOSFETs) or about 100,000 cells per cm 2 (high-voltage-igbts) distributed over a chip surface of cm 2. The cell-sections show the analogue structure of the MOSFET and IGBT control zones. The n - -zone has to take up the space charge zone during off-state and accommodates p-charged wells with a low marginal (p - ) and a high central (p + ) doping. These wells also include n + -silicon-layers which are connected to the aluminium- metallized source (MOSFET) or emitter (IGBT) electrode. A control zone (gate) consisting, for example, of n + -polysilicon is embedded in a thin isolation layer of SiO 2 above the n + -areas. By applying a sufficient positive control voltage between gate and source (MOSFET) or emitter (IGBT), an inversion layer (n-conducting channel) is generated in the p-area below the gate. Electrons may be conducted from source or emitter to the n - -drift-area via this channel. In contrast to the identical structure of MOSFET and IGBT including the n - -zone, there are differences regarding the third electrode, which will determine all further functions. 15

15 1 Basics Power-MOSFET [277] Source B A Gate Source D Drain SiO 2 Al p d p p - n + p + Gate G S D Source Drain Gate G n - - n - n + n + B A Drain a) - - b) S Source A-B: wide of elementary cell d: length of channel Figure 1.2 Power-MOSFET (SIPMOS Siemens) a) MOSFET-cell with charge flow during on-state b) Common switch symbols Figure 1.2 explains the structure and function of a vertical n-channel-enhancement power- MOSFET with planar gate structure. The MOSFET s layer structure described above results from epitaxial, implantation and diffusion processes on a substrate of n + -conductive silicon material with a drain contact on its reverse side. The electrons flowing in the electrical voltage field between drain and source are attracted by the drain connection, thus absorbing the space charge zone; consequently, the drain-source voltage will decrease and the main current (drain current) will be able to flow. Since the electrons are conducting current by 100 % and are majority charge carriers in the n - - drift area, the highly resistive n - -zone will not be flooded by bipolar charge carriers; the MOSFET is a unipolar component. Whereas the drain-source on-resistance of low-voltage MOSFETs is composed of single cellular resistances about 5 % to 30 %, 95 % of the R DS(on) of high reverse voltage MOSFETs result from the n - -epitaxial area resistance. Therefore, on-state voltage drop V DS(on) = I R with I D : drain current and D DS(on) R DS(on) k V (BR)DS -9 A -1 = with k: material constant, e.g. k = for a chip surface of 1 cm 2 ; V (BR)DS : Drain-source forward breakdown voltage as a theoretical limit value of the actually available MOSFETs is always higher for MOSFETs from about V off-state voltage than for comparable bipolar components and the current 16

16 1 Basics carrying capacity is lower. Recently developed structures with improved parameters will be dealt with in chapter On the other hand, there are no storage effects because the majority charge carriers are exclusively responsible for charge transportation. Very short switching times may be produced however, requiring rather high control currents for changing the internal capacitances in the case of extensive components (high voltage/ high current) with about 0.3 µc per cm 2 chip surface. The capacitances resulting from the physical structure of the MOSFETs are the most important parasitic elements in Figure 1.3; their influence on the characteristics of components will be described in the corresponding chapters. Source C GS R G Gate SiO 2 Source Al D (Drain) n + R W p - C GD p - R D p + p + C DS C GD C DS R D n - n + n + n - G (Gate) R G C GS R W "Inverse Diode" Drain S (Source) a) b) Figure 1.3 Power-MOSFET-cell with the most important parasitic elements a) Parasitic elements within the cellular structure b) Equivalent circuit with parasitic elements The follwing table explains causes and designations of the parasitic capacitances and resistances in Figure 1.3: Symbol Designation C GS Gate-source capacitance Overlapping gate and source metallization; dependent on gate-source voltage; independent of drain-source voltage C DS Drain-source capacitance Junction capacitance between n - -drift zone and p- well; dependent on cell surface, drain-source breakdown voltage and drain-source voltage G GD Gate-drain capacitance Miller capacitance; generated by overlapping of gate and n - -drift zone R G Gate resistance (internal) Poly-silicon-gate resistance; in modules with several transistor chips often additional series resistors are needed to minimize oscillations between chips R D Drain resistance Resistance of n - -zone; often main part of MOSFET-on-state-resistance R W Lateral resistance of p- well Base-emitter resistance of parasitic npn- bipolar transistor 17

17 1 Basics IGBT [278] p + p + Emitter B B A Gate Emitter A p - SiO 2 n n - p d p Collector n p + Al G Gate G Gate Collector C E Emitter Collector C E Emitter A-B: wide of elementary cell a) d: length of channel b) Figure 1.4 IGBT with NPT-structure a) IGBT-cell with charge distribution during on-state b) Common switch symbols Figure 1.4 explains structure and function of a vertical n-channel-enhancement IGBT with planar gate and NPT-(Non-Punch-Through)-structure. In contrast to MOSFETs, IGBTs are equipped with a p + -conductive area with connection to the collector below the n-zone. After having passed the n - -drift area, the electrons enter the p + -area, thus arranging for positive charge carriers (holes) to be injected from the p+-zone to the n - -zone. The injected holes will flow directly from the drift-area to the emitter-p-contact as well as laterally to the emitter passing the MOS-channel and the n-well. In this way the n - -drift area will be flooded with charge carriers which are conducting the main current (collector current); this charge enhancement will lead to a space charge reduction and, consequently, to a reduction of the collector-emitter voltage. Although, compared to the pure ohmic on-state behaviour of the MOSFET, the IGBT has an additional threshold voltage at the collector pn-junction layer, the on-state voltage of highvoltage IGBTs (from about 400V) is lower than that of MOSFETs because of the enhancement of minority carriers in the highly resistive n - -zone. In comparison to MOSFETs, IGBTs may be designed for considerably higher voltages and currents for similar chip surfaces. On the other hand, the surplus p-storage charge Q S that has not been extracted during the collector voltage increase period has to recombine in the n - -zone during turn-off. Q s has an almost linear characteristic in the low-current range and rises proportionally to the forward current in the rated current and overcurrent range according to a radical law. [282]: Q s I in the low-load forward current range Q s I 0.5 in the rated current and overcurrent range Q s V (BR)CE 18

18 1 Basics Storage charge enhancement and depletion processes cause switching losses, a delay time (storage time) and a collector tail-current during turn-off. (see chapter 1.2.3). Apart from the Non-Punch-Through -structure (NPT) shown in Figure 1.3, the Punch- Through (PT)-structure is also applied in IGBTs today. It was the conceptional basis for the first IGBTs. Basically, the two structures differ in the PT-IGBT s highly-doped n + -layer (buffer layer) between n - - and p + -zone and in the manufacturing process. Whereas the n + - and n - -layers in a PT-IGBT are usually generated on a p + -substrate by an epitaxial procedure, the basis of the NPT-IGBT is a thin, hardly doped n-wafer, at the reverse side of which the collector p+-zone is generated by implantation. The MOS-control zones on top of both IGBTs are identical in their planar structure. Figure 1.5 compares both IGBT-structures and their electrical field characteristics during offstate. Emitter Gate Emitter Al E n n p n - n + p + A Collector p xp+p n + n - a) Emitter Gate Emitter Al E n n p p n - p p xpp n - b) Collector Figure 1.5 IGBT-structures and off-state electrical field characteristics [193] a) PT-IGBT b) NPT-IGBT 19

19 1 Basics The space charge zone in a PT-IGBT or IGET (E: epitaxial structure) spreads over the whole n - - area during off-state. In order to keep the epitaxial layer as thin as possible for high off-state voltages also, the electrical field is reduced by the highly doped n + -buffer at the end of the n - - drift area. The n - -drift area in an NPT-IGBT or IGHT (H: homogeneous structure) is dimensioned large enough so that the electrical field can be completely discharged within the n - -drift area during off-state at maximum off-state voltage. The electrical field cannot spread over the whole n - -zone (punch through) within the permissible operation range. For further explanations on IGBT-functions and the deviating characteristics of PT- and NPTcomponents it is, first of all, necessary to study the equivalent circuit resulting from the IGBTstructure (Figure 1.6b). Emitter C GE R G Gate Emitter C (Collector) SiO 2 Al n + R W p - C GC p - R D p + p + C GC C CE C CE R D G (Gate) R G C GE R W n - n - p + p + Collector a) b) E (Emitter) Figure 1.6 IGBT-cell (NPT-structure) with the most important parasitic elements a) Parasitic elements in the cellular structure b) Equivalent circuit with parasitic elements Causes and designations of the parasitic capacitances and resistances in Figure 1.6 are analogous to Figure 1.3. Symbol Designation C GE Gate-emitter capacitance Overlapping gate and source metallization; dependent on gate-emitter voltage; independent of collector-emitter voltage C CE Collector-emitter capacitance Junction capacitance between n - -drift zone and p- well; dependent on cell surface, drain-source G GC breakdown voltage and drain-source voltage Gate-collector capacitance Miller-capacitance: generated by overlapping of gate and n - -drift zone R G Gate resistance (internal) Poly-silicon-gate resistance; in modules with several transistor chips often additional series resistors are needed to minimize oscillations between chips R D Drift resistance Resistance of n - -zone (base resistance of a pnptransistor) 20

20 1 Basics Symbol Designation R W Lateral resistance of p- well Base-emitter resistance of the parasitic npnbipolar transistor Apart from internal capacitances and resistances, the equivalent circuit of the IGBT also shows features of the ideal MOSFET and the parasistic npn-transistor: n + -emitter zone (emitter)/p + - well (base)/n-drift zone (collector) with the lateral p + -well resistance below the emitters as baseemitter resistance R W. In addition to that a pnp-transistor may be generated by sequence of p + - collector (emitter)/ n - -drift (base)/ p + -well (collector), which represents together with the npntransistor thyristor circuit. Latch-up of this parasitic thyristor may happen basically during on-state (when a critical current density is exceeded, which decreases with rising chip temperature) and also during turn-off (dynamic latch-up due to the increased hole current compared to on-state operation), as soon as the following latch-up preconditions are met: ( α + α ) 1 M npn pnp = with α, α = α γ pnp npn T E M: multiplication factor; α npn, α pnp : current gain of the single transistors in base circuit; α T : base transportation factor; γ E : emitter efficiency This will lead to a loss of controllability of the IGBT and, therefore, to its destruction. The following design measures will reliably prevent latch-up in modern IGBTs under all permissible static and dynamic operation conditions; the turn-off current density of dynamic latch-up, for example, is about 15 times the rated current density. At first, the base-emitter resistance R W of the npn-transistor is reduced by means of - high doping of the p + -well directly below the n-emitters, and - shortening of the n-emitters to such an extent, that the threshold voltage of the npn-transistor base-emitter diode will not be reached in any permissible state of operation. Furthermore, the hole current (npn-transistor base current) is kept on a minimum level by a low current amplification in the pnp-transistor. However, switching behaviour and ruggedness have to be optimized with the on-state characteristics which also depend considerably on the pnptransistor design. This has been produced for PT- and NPT-IGBTs in different ways [278]. For PT-IGBTs, the efficiency (emitter efficiency) of hole injection of the p + -zone into the n - -drift area is very high, since the substrate is very thick and highly doped. The pnp-current amplification may only be lowered with the help of the base transportation factor (n - -drift zone, n + -buffer), implementing additional recombination centres (e.g. by gold doping or electron beam radiation) to reduce charge carrier life time in the n + -zone. The hole current adds up to % of the total current. In case of NPT-IGBTs the p+-emitter zone generated at the collector by implantation is much thinner than the PT-IGBT-substrate. Therefore, the doping material concentration can be exactly dimensioned during wafer production. The very thin p+-layer guarantees a low emitter efficiency (γ E = 0,5) of the pnp-transistor, so that it is not necessary to lower the base transportation factor by reducing charge carrier life time. The hole current sums up to % of the total current. 21

21 1 Basics Compared to the PT-IGBT, the NPT-IGBT shows the following advantages resulting from diminished emitter efficiency, longer charge carrier life time and more exact design possibilities, which is still to be detailed in chapters 2 and 3: - positive on-state voltage temperature coefficient ( automatic static balancing in the case of parallel connection), - lower, but partly longer turn-off tail current; lower turn-off losses at T j = 125 C, - (in the case of hard switching) shorter switching times and reduced switching losses, - considerably reduced temperature dependency of switching times / switching losses (T j = 125 C) and tail current, - increased overcurrent stability by improved current limitation in case of overload. Compared to the epitaxial substrates of the PT-IGBT, today s production of the homogeneous n - - substrate as basic material for NPT-IGBTs is more favourable, provided that the much thinner silicon wafers are handled properly Static behaviour In this chapter the static behaviour of power MOSFETs- and IGBT-modules is to be examined regarding the current-voltage characteristics of the main terminals in the I st and III rd quadrant of the respective output characteristic (Figure 1.7). On-State Region (Saturation Region) I D, I C Active Region On-State Current OP2 Forward Area Reverse Blocking (Series Diode) Forward Blocking Current On-State Voltage OP1 Forward Blocking Voltage P fw/max V DS, V CE Reverse Area Reverse Conducting (Antiparallel-Diode) Figure 1.7 Basic output characteristic of a power transistor module 22

22 1 Basics The I st quadrant shows the forward area, where power transistor modules can block high voltages and switch high currents. The exact designation blocking state - analogous to thyristors - for blocking in the I st quadrant is hardly used in connection with transistors. Usually, this is called forward off- state (as in the following explanations) or off-state (as long as there is no risk of confusion). Via the gate electrode, the power-mosfet or IGBT is turned from the forward off- state (OP1 in Figure 1.7) to the conductive state or on-state (OP2), where it can conduct load current. The active region is only passed during switching. Contrary to the perfect switch off-state voltage and on-state current are limited (see chapter 0). During the forward off-state a cut-off current (forward off-state current) causes blocking power dissipation within the transistors. In the conductive state the voltage left at the main power terminals depends on the on-state current and is called on-state voltage, causing on-state power dissipation. The maximum power dissipation during on-state (not during switching) is shown by the on-state power dissipation hyperbola for P fw/max in the output charcteristic. The current-voltage characteristics in the III rd quadrant of the output characteristic show the reverse behaviour of power transistor modules, in case a negative voltage is applied to the main terminals. This behaviour is determined by the characteristics of the transistors (reverse blocking, reverse conducting) and the features of the diodes within the power module (connected in series or anti-parallel to the transistors) Power-MOSFET The functional principles of the power-mosfet described above result in the output characteristics in Figure 1.8a. 23

23 1 Basics I D Ohmic Region Active Region Avalanche-Breakdown R DS(on) = V DS I D I D g fs = I D DS GS V GS V F0 V GS(th) V GS V F (-V DS ) V GS < V GS(th) Forward Blocking Characteristic V (BR)DSS V DS b) a) I F (-I D ) Figure 1.8 a) Output characteristics of a power-mosfet (n-channel-enhancement-type) b) Transfer characteristic I D = f(v GS ) Forward off-state When applying a positive drain-source voltage V DS and a gate-source voltage V GS smaller than the gate-source threshold-voltage V GS(th), there will only be a very small zero gate voltage drain current I DSS between drain- and source connection. I DSS will rise slightly with increasing V DS. If a certain specified maximum drain-source voltage V DSS is exceeded, this will cause an avalanche breakdown of the pin-junction p + -well/n - -drift zone/n + -epitaxial layer (breakdown voltage V (BR)DSS ). Physically, V (BR)DSS is almost equivalent to the breakdown voltage V CER of the parasitic bipolar npn-transistor in a MOSFET, generated by the sequence of layers: n + -source zone (emitter)/p + -well (base)/n - -drift zone/n + -epitaxial layerdrain connection (collector), see Figure 1.3. The multiplication current generated by the avalanche breakdown of the collector-base diode may lead to destruction of the MOSFET as soon as the bipolar transistor is turned on. However, the base and emitter zones are almost short-circuited by metallization of the source; both zones are only separated by the lateral resistance of the p + -well. Several structural improvements, such as small MOSFET cells, homogeneous cell arrangement, low-resistive p+-wells, optimized marginal structures and highly homogeneous technological procedures, may facilitate a very small avalanche breakdown current per cell in modern MOSFETs, so that the bipolar transistor will not yet be turned on, in case the defined specifications are strictly complied with. 24

24 1 Basics Therefore, a permissible avalanche energy E A for single pulses or periodic load (limited by the maximum chip temperature) can be defined; see chapter Since several parallelled MOSFET-chips in power modules cannot guarantee absolute symmetrical conditions, the maximum E A -value is only applicable for one single chip. On-state The forward on-state at positive drain-source voltage V DS and positive drain current I D can be divided into two characteristic regions (Figure 1.8, I st quadrant). Pinch-off or active region At a gate-source voltage V GS slightly exceeding the threshold voltage V GS(th), current saturation will cause a considerable drop of voltage over the channel (horizontal region of the output characteristic). The drain current I D is controlled by V GS. The transfer behaviour shown in Figure 1.8b is called forward transconductance g fs defined as follows: g fs = di D /dv GS = I D /( V GS -V GS(th) ). Forward transconductance in the pinch-off region rises proportionally to the drain current I D and the drain-source-voltage V DS and drops with increasing chip temperatures. Within the permissible operation conditions for power modules with several paralleled MOSFET-chips, the pinch-off region is only passed during turn-on and turn-off. On the other hand, stationary operation within the pinch-off region is mostly prohibited by the manufacturer, because V GS(th) will drop when the temperature rises and, therefore, thermal instability between the single chips might result from minor production deviations. Ohmic region The ohmic region, which is also called on-state during switching operations, is reached as soon as I D is determined only by the outer circuit. The on-state behaviour can be characterized as the quotient of changed drain-source-voltage V DS and drain-current I D via the turn-on resistance R DS(on). Consequently, the forward voltage V DS(on) may be defined by the following equation already mentioned in chapter (large-signal behaviour) V DS(on) = R DS(on) I D R DS(on) is dependent on the gate-source voltage V GS and the chip temperature. R DS(on) is approximately doubled within the MOSFET operation temperature range between 25 C and Reverse operation During reverse operation (III rd quadrant) the MOSFETcharacteristic is equivalent to a diode characteristic at V GS < V GS(th) (continuous curve in Figure 1.8a). This is caused by the parasitic diode within the MOSFET; the MOSFET reverse on-state behaviour at closed channel is controlled by the on-state voltage of the collector-base pn-junction or source-drain pn-junction, respectively ( inverse diode, bipolar current flow) (Figure 1.9a). 25

25 1 Basics Source Gate Source n + Al V GS = 0 V p - p + n p - p + n - n - n + V DS = -V F a) Drain Source Gate Source Al n + V GS > V GS(th) p + p - - p - p + V DS > -V F0 (z.b V) n - n - n + n + b) Drain Source Gate Source Al p - p + n n + p - p + n - n + n - V GS > V GS(th) V DS < -V F0 (z.b V) c) Drain Figure 1.9 Inverse operation of a power-mosfet [277] a) At closed channel (bipolar current flow) b) At open channel and small negative V DS (unipolar current flow) c) At open channel and big negative V DS (combined current flow) The bipolar inverse diode is utilized for currents up to the limit values specified for MOSFETs. In practice, however, the inverse diode - causes relatively high on-state power losses, which have to be dissipated together with the MOSFET power losses and 26

26 1 Basics - sets limits to the MOSFET s application field as a hard switch (see chapter 0) by its unfavourable turn-off behaviour. As shown in Figure 1.9b the conductance in the MOSFET-channel is principally controllable even at a negative drain-source-voltage, if a gate-source voltage is applied exceeding the threshold voltage. If the drain-source voltage is limited to a value lower than the inverse diode threshold voltage by external components, for example by paralleling of a Schottky-diode, the inverse current will be conducted from drain to source as a unipolar electron current (majority carrier current). Then, the turning-off corresponds to the turn-off behaviour of a MOSFET. The inverse current is dependent on V DS and V GS. (broken curve in Figure 1.8a). Operation with combined current flow according to Figure 1.9c (semi-coloned curve in Figure 1.8a) is given, if the channel is open and a conducting bipolar inverse diode is connected (drainsource voltage higher than diode threshold voltage). This results in a reduced on-state voltage compared to simple paralleling of diode and MOSFET, since the injected charge carriers will also diffuse laterally, thus increasing the MOSFET s conductivity. Apart from that, MOSFET-chips with fast inverse diodes have been developed by several manufacturers during the past few years (e.g. FREDFETs; Fast Recovery Epitaxial Diode Field Effect Transistors)[277]. Hole life time at inverse operation is minimized in FREDFET-chips by selective heavy-metal diffusion into the n - -drift area, similar to the design of fast diodes IGBT The functional principle of the IGBT described in chapter results in the output characteristic in Figure I C Saturation Region Active Region Avalanche-Breakdown V GE I C g fs = I C V GE V CE -V CE V Forward Blocking GE < V GE(th) Characteristic V (BR)CES V GE(th) V GE IGBT without hybride Antiparallel-Diode b) a) IGBT with hybride Antiparallel-Diode I F (-I C ) Figure 1.10 a) Output characteristic of an IGBT (n-channel-enhancement-type) b) Transfer characteristic I C = f(v GE ) 27

27 1 Basics Forward off-state In analogy to the MOSFET, the collector-emitter cut-off current I CES between collector and emitter is only very small, if the collector-emitter voltage V CE is positive and the gate-emitter voltage V GE is lower than the gate-emitter threshold voltage V GE(th). As a consequence of increasing V CE, the I CES -value rises slightly. When a certain specified maximum collector-emitter voltage V CES is exceeded, there will follow an avalanche breakdown of the pin-junction layers p + -well/n - -drift zone/n + -epitaxial layer (avalanche breakdown voltage V (BR)CES ). Physically, V (BR)CES corresponds approximately to the reverse collector-emitter voltage V CER of the bipolar pnp-transistor in the IGBT structure. (see Figure 1.6). The multiplication current generated by the avalanche breakdown of the collector-base diode may lead to destruction of the IGBT, as soon as the bipolar transistor is turned on. However, base and emitter are almost short-circuited by metallization of the emitter, only separated by the lateral resistance of the p + -well. By several structural improvements within the IGBT, similar to the measures taken for MOSFETs as described in chapter , the avalanche breakdown current per cell is kept at a minimum level, which results in a high forward off-state voltage stability (avalanche stability). On-state Also with the IGBT, the forward on-state at a positive collector-emitter voltage V CE and a positive collector current I C can subdivided up in two characteristic regions (Figure 1.10, I st quadrant). Active region At a gate-emitter voltage V GE slightly exceeding the threshold voltage V GE(th), current saturation will cause a considerable voltage drop over the channel (horizontal region of the output characteristics). The collector current I C is controlled by V GE. The transfer behaviour shown in Figure 1.10b is called - in analogy to the MOSFET - forward transconductance g fs defined as follows: g fs = di C /dv GE = I C /( V GE -V GE(th) ) Forward transconductance in the cut-off region rises proportionally to the collector current I C and the collector-emitter voltage V CE, and decreases with increasing chip temperatures. Within the permissible operation conditions for power modules with several paralleled IGBTchips, the cut-off region is only passed during turn-on and turn-off. Equivalent to MOSFET modules, stationary operation within the cut-off region will mostly be prohibited, since V GE(th) will decrease when the temperature rises and, also with IGBTs, thermal instability between the single chips might result from minor production deviations. Saturation region The saturation region (steep region of the output characteristic), also called on-state during switching operation, is reached as soon as I C is determined only by the outer circuit. The on-state behaviour is characterized by the IGBT voltage V CEsat (collector-emitter saturation voltage). At least for highly blocking IGBTs, the saturation voltage is considerably smaller than the on-state voltage of a comparable MOSFET due to the n - -drift-zone being flooded with minority carriers. As already mentioned, V CEsat of PT-IGBTs will drop at a temperature increase within rated current operation, whereas V CEsat of NPT-IGBTs will rise proportionally to the temperature. 28

28 1 Basics Reverse operation During reverse operation (Figure 1.10, III rd quadrant) the IGBT collector pn-junction is poled in reverse direction and there is no inverse conductivity, other than with MOSFETs. Although, due to the large n - -drift zone, this is actually the structure of a highly resistive pindiode, at least in the case of NPT-IGBTs, the reverse voltage in today s IGBTs is only some 10V. Apart from design of the chip margin, this is due to the fact that the chips have been designed mainly to comply with a high off-state voltage and an optimized collector heat dissipation. IGBT-switches designed for special reverse applications have therefore been equipped solely with adapted, fast hybrid diodes connected in series. So, the characteristics of the external or hybrid diodes (see chapter 1.3) are exclusively responsible for the reverse on-state behaviour of IGBT-modules Hard switching behaviour of MOSFETs and IGBTs Most switching applications for transistor switches require hard switching of ohmic-inductive loads with continuous load current, i.e. the time constant of the load L/R is much bigger than the cycle l/f of the switching frequency. The resulting basic waveforms for drain or collector current and drain-source or collector-emitter voltage are shown in Figure 1.11a. V GG V GS(th) V GE(th) t 1 t 2 t 3 t 4 t i D, i C I L MOSFET I t (IGBT) t v DS, v CE V DD V CC V DS(on) VCE(sat) MOSFET a) IGBT t 29

29 1 Basics V DD I L i D, i C on I L V GG i D off V CC I L V DD V CC v DS, v CE V GG i C b) Figure 1.11 Typical hard switching behaviour of MOSFET and IGBT (ohmic-inductive load with free-wheeling circuit) a) Current and voltage waveforms b) Curve and measurement circuit As already depicted in chapter 0, Figure 0.4 a high short-time transistor current and voltage during turn-on and turn-off are typical features of hard switching. In contrast to all types of thyristors, such transistors operate without passive snubber networks thanks to the dynamic junction which is generated in the drift zone during switching operation. In a transistor, however, considerable switching energy E on, E off = u idt t on, t off is dissipated as explained by the graph i C = f(v CE ) (and i D = f(v DS )) in Figure 1.11b. The curve may be directed nearer towards the axes with passive snubber networks. Switching losses are shifted from the transistor to the snubber, the total efficiency will decrease in most cases (chapter 3.8). Since the size of the operating area is influenced by many (non-ideal) transistor features apart from current/ voltage limitations and switching times, the SOA (Safe Operating Area) is given in the datasheets for different operating conditions (see chapters 2.1.2, and 2.3.3). Moreover, passive circuit elements have a tremendous influence on switching losses and operating areas, apart from the non-ideal transistor features and the diode characteristics described in chapter 1.3. The effects of such passive circuit elements also indicated in Figure 1.11a are explained in detail in chapter Physically, the typical current-voltage characteristics in Figure 1.11a are caused by the freewheeling diode, which has to prevent current snap-off by load inductance: 30

30 1 Basics - When the transistor is turned on, the free-wheeling diode can only take up reverse recovery voltage (turn off), after the load current has completely commutated to the transistor. Therefore, the collector or drain-current has to reach the load current level, before the collector-emitter (or drain-source) voltage may fall to the on-state value. - When the transistor is turned off, the free-wheeling diode can only take up the load current (turn on), after it has reached on-state voltage polarity. This will be the case when the collector-emitter (or drain-source) voltage has exceeded the commutation voltage level, before the collector or drain-current may fall to the cut-off current value. As shown in Figure 1.11a, the drain-source or collector-emitter voltage of comparable components will, shortly after turn-on of the MOSFET or IGBT, drop within some 10ns to a value, that is equivalent to the voltage drop over the n - -drift area. Whereas in the MOSFET the on-state voltage has already been reached by this, the n - -area of the IGBT is now flooded with positive charge carriers from the p-collector zone. After this procedure has been finished (appr. 100ns up to some µs), the static value of the on-state saturation voltage V CE(sat), which is relatively low for highly blocking components, has been reached (conductivity modulation). During turn-off of the MOSFET, the internal capacitances have to be recharged, that there are no charge carrier influence left in the channel area. Thereafter, the neutrality interferences in this area will quickly be reduced and the drain current will drop rapidly. The procedure within the IGBT is principally the same. However, after the emitter current in the n - -drift zone has been turned off, a large number of p-charge carriers generated by injection from the IGBT-collector zone is still left. These p-charge carriers have now to be recombined or reduced by re-injection, which would cause a so-called collector tail current I t. (Figure 1.11a). Since this tail current will fade away within some µs only with already increased collectoremitter voltage, the hard turn-off power losses in the IGBT are mainly determined by the tail current waveform (see chapter 2.3.2, 3.1.3) and are considerably higher than those in MOSFETs. Apart from the explained differences, the switching behaviour of MOSFETs is very similar to that of IGBTs due to the equivalent gate structure. As described in chapter 1.2.1, the forward on-state and forward off-state capability, the reverse behaviour and the limits of the transient currents and voltages during switching are influenced by the internal structures of the bipolar transistor and the lateral resistances. The switching behaviour (switching velocity, switching losses) of MOSFET and IGBTpower modules is determined by their structural, internal capacitances (charges) and the internal and outer resistances. Contrary to the ideal of a powerless voltage control via the MOSFET or IGBTgate, a frequencydependent control power is required resulting from the necessary recharge currents of the internal capacitances, see chapter 3.5. Moreover, the commutation processes are affected by the parasitic connection inductances existing in the power layout and generated by connection of transistor chips in power modules; they induce transient overvoltages and may cause oscillations due to the circuit and transistor capacitances (see chapter 3.4). In the following, the switching behaviour of MOSFETs and IGBTs is to be analysed in relation to the internal capacitances and resistances of the transistor. 31

31 1 Basics When the MOSFET (IGBT) is turned off, C GD (C GC ) is low and is approximately equal to C DS (C CE ). During on-state C GD (C GC ) will increase rapidly due to inversion in the enhancement layer below the gate zones, as soon as the gate-source (emitter) voltage has exceeded the drain-source (collector-emitter) voltage. Additionally, C GD (G GC ) will increase dynamically during the switching procedure due to the Millereffect: C GDdyn = C GD ( 1- dv DS /dv GS ) (MOSFET) C GCdyn = C GE ( 1- dv CE /dv GE ) (IGBT) In most datasheets the following voltage-dependent low-signal capacitances of turned off transistors are given (see chapters 2.2.2, 2.2.3). Power MOSFET IGBT C iss = C GS + C GD C iss = C GE + C GC Input capacitance C rss = C GD C rss = C GC Reverse transfer capacitance C oss = C GD + C DS C oss = C GC + C CE Output capacitance For calculation of the switching behaviour, these datas may only be applied to a certain extent, since e.g. C iss and C rss will again increase enormously in a fully switched on transistor (V DS < V GS bzw. V CE < V GE ), a fact that is not considered in most datasheets (Figure 1.12 and Figure 1.13) [277]. Therefore, switching times in relation to gate current, drain-source voltage and drain current are determined with the aid of the MOSFET gate charge characteristic indicated in the datasheets, plotting the gate-source voltage over the gate charge Q G on condition of rated current and 20 % or 80 % of the maximum drain-source voltage (Figure 1.12). Load conditions and measurement circuit are equivalent to Figure However, for simplification purposes, constant current is supposed to be fed to the gate. Now, switching intervals may be determined very simply with the following relation (see chapter 3.5.1): i G = dq G /dt 32

32 1 Basics V GS [V] 16 V DS1 <V DS2 V DS1 V DS2 V GG 10 t 3 (V DS2 ) t 1 t 2 t 3 (V DS1 ) t 4 (V DS1 ) t 4 (V DS2 ) V GS(th) 2 0 Q G1 Q G2 250 Q G3 500 Q Gtot Q G [nc] Figure 1.12 a) Gate-source voltage characteristic (V GS ) of a power MOSFET dependent on the gate charge Q G (gate charge characteristic) b) Low-signal capacitances of a power MOSFET Turn-on: switching interval 0...t 1 (blocked transistor) Gate current will be triggered by applying a control voltage. Up to the charge quantity Q G1 the current i G solely charges the gate capacitance C GS. The gate voltage V GS rises. As V GS is still below the threshold voltage V GS(th), no drain current will flow during this period. Turn-on: switching interval t 1...t 2 (rise of drain current) As soon as V GS has reached V GS(th) -level at t 1, the transistor is turned on, first passing the active region (see chapter ). Drain current rises to I L -level (ideal free-wheeling diode) or even exceeds I L - as indicated in Figure 1.11a for a real free-wheeling diode. Similarly, V GS, which is connected to the drain 33

33 1 Basics current in the active region by the transconductance g fs with I D = g fs * V GS, will increase up to the value V GS1 = I D /g fs (time t 2 ). Since the free-wheeling diode can block the current only at t 2, V DS will not drop considerably up to t 2. At t = t 2 charge Q G2 has flown into the gate. Turn-on: switching interval t 2...t 3 (transistor during turn-on) When the free-wheeling diode is turned off, V DS will drop almost to on-state value V DS(on) by time t 3. Between t 2 and t 3 drain current and gate-source voltage are still coupled by transconductance; therefore, V GS remains constant. While V DS is decreasing, the Miller capacitance C GD is recharged by the gate current i G with the charge quantity (Q G3 -Q G2 ). By t = t 3 charge Q G3 has flownflown? into the gate. Turn-on: switching interval t 3...t 4 (ohmic characteristic area) At t 3 the transistor is turned on, its curve has passed the pinch-off area to enter the ohmic area. V GS and I D are no longer coupled by g fs. The charge conducted to the gate (Q Gtot -Q G3 ) at this point affects a further increase of V GS up to the gate control voltage V GG. Since the drain-source on-resistance R DS(on) depends on I D and V GS, the on-state voltage V DS(on) = I D * R DS(on) may be adjusted to the physical minimum by the total charge quantity Q gtot conducted to the gate. The higher the drain voltage V DD (or commutation voltage), the bigger the charge Q gtot required to reach a certain gate-source voltage, see Figure Turn-off During turn-off the described processes are running in reverse direction; the charge Q Gtot has to be conducted out of the gate by the control current. For approximations to determine the gate charge quantity required for turn-off, the gate charge characteristic in Figure 1.12 may be used. The further the specific transistor application deviates from the hard switch -application described, the more the step-form of the gate-source voltage blurs. The intervals decoupled by the free-wheeling diode during hard switching will then more or less merge into one another, which requires a more complex explanation of the switching behaviour. [278]. The above-mentioned description may be applied to IGBTpower modules by analogy. The switching behaviour can be determined correspondingly by the gate charge characteristic also indicated in the datasheets. Since an IGBTgate is mostly switched between a positive and a negative gate voltage, also a certain charge quantity is required to switch the gate capacitance between 0V and V GG-. Therefore, the gate charge characteristic has to be extended as depicted in Figure to calculate the total gate charges. 34

34 1 Basics V GE [V] V CE2 >V CE1 V GG+ 15 t 3 (V CE2 ) t 1 t 2 t 3 (V CE1 ) t 4 (V CE1 ) V CE1 V CE2 t 4 (V CE2 ) V GE(th) Q G- 0 Q G1 Q G2 250 Q G3 500 Q Gtot Q G [nc] a) V GG- b) Figure 1.13 a) Extended IGBT gate charge characteristic for gate control between V GG+ and V GGb) IGBT low-signal capacitances New developments in MOSFET and IGBT technology For the time being, the most important goals in research and development of MOSFET- and IGBT chips are: a) Reduction of the on-state voltage b) Reduction of switching power losses c) Improved ruggedness (overcurrent-, overvoltage-behaviour, switching performance) d) Increased off-state voltage for high-volt transistors e) Consequent to a)...c): increased current density (shrinking) f) Provided that e) is complied with, increase of current per chip or decrease of chip surface and costs g) Optimized low saturation and high speed-igbts 35

35 1 Basics h) Integration of monitoring, protection and driver functions or power electronic circuits (monolithic, chip-on-chip or silicon-on-insulator) Especially during the past years a rapid development progress is to be noted concerning mainly the optimization of the horizontal and vertical cell design, the refinement of the cell structure and the successful handling of ultra-thin silicon wafers. With mastery of the thin-wafer technology (wafer thickness 100µm), for example, the production of extremenly low-loss 600V-IGBTs in NPT-technology had been possible [164]. For the time being, the principal improvement potential for MOSFETs and IGBTs lies in optimizing the cell design. Firstly, there are new superfine structures, such as the S-FET product range by SIEMENS, thanks to the latest self-adjusting processes realizing an on-state resistance that is a fifth of that of conventional MOSFETs and a clearly improved switching and avalanche stability [216]. These structures, which are applied in similar forms also in modern high-density IGBTs, contain double-implantation gates with spacers in the margin region (Figure 1.14). Spacer AISi TEOS Polysilicon Source Body C p + n + p Drain n - Figure 1.14 Double-implantation gate structure (Siemens S-FET) [298] A lately developed gate structure for MOSFETs and IGBTs which will replace the conventional gate structure is the trench-gate, which allows for a vertical passage of the channel in the p-well (Figure 1.15). Since this structure provides for more active silicon surface, control of the channel cross-section becomes easier and a smaller channel resistance may be realized. The on-state losses can be reduced by about 30 %. Furthermore, the cell surface can again be reduced, allowing higher current density, reduced onstate losses, improved latch-up stability, reduced switching losses and a higher breakdown voltage compared to planar MOSFETs and IGBTs. The disadvantages, however, are a decreased short-circuit stability and an approximately three times higher gate capacitance compared to that of planar elements. 36

36 1 Basics Structure of Field Stop IGBT emitter gate p emitter p n-emitter gate oxide p-emitter n - n collector field stop layer Figure 1.15 IGBT-cell with trench-gate and field stop layer Also the so-called IEGTs (Injection Enhaced Gated Transistors) for extremely high voltage applications ( kv) have been designed in trench technology; due to the cathode emitter structure, the leak-off process of the holes is impeded, causing a charge carrier density similar to that of thyristors during on-state [194]. A remarkable progress within the high-volt power MOSFET has been made with the CoolMOS introduced by SIEMENS in 1998 [216]. As shown in Figure 1.16, the MOSFET-cell structure of the CoolMOS has been equipped with p-conducting areas in the drift zone which are connected to the p-wells. Source Gate Source Source Gate Source SiO 2 Al SiO 2 Al n n n n p + p + p + p + p p p p n - n + n + n - n - n + n + p p n - Drain a) b) Drain Figure 1.16 MOS- cell structures a) Conventional structure b) CoolMOS-structure (principle) Since, during forward off-state, the electrical field is not only handled in vertical, but also in horizontal direction, the n - -drift area may be drastically reduced in size compared to conventional MOSFETs, by increasing its conductivity at the same time. The turn-on resistance R DS(on) will then not increase in the exponential way described under chapter anymore (exponent ), but only linearly to the breakdown voltage V (BR)DS. 37

37 1 Basics By this, the forward on-state losses of a 600V-CoolMOS, for example, will be reduced by the factor 5 in contrast to a conventional MOSFET with the same chip surface. Only 1/3 of the previous chip surface is required to manage the same current. Switching losses will be halved and on-state losses will be reduced to about 35 %; due to the reduced chip surface, also gate capacitance and gate charge will decrease to about a third of the previous value [216]. However, the bad dynamic behaviour of the inverse diodes inside the CoolMOS-structure is disadvantageous. This restricts the application in hard switching topologies with inductive commutation. Further progress will be achieved with the use of other semiconductor materials, such as silicon carbide (SiC). Compared to Si, SiC shows an almost 10 times higher breakdown field intensity. In spite of restricted mobility of the electrons, on-state resistances reduced by the factor 1/300 are realizeable in unipolar components, which guarantees for a high-voltage application range far beyond 1000V. As for bipolar SiC-components, the smaller drift area results in a scaled down storage charge. On the one hand, the energy gap, which is three times as big as that of Si, allows operating temperatures up to 500 C; on the other hand the threshold voltage of bipolar components is increased to 2.5V. Other unfavourable effects lie in the considerably higher junction capacitances compared to Sicomponents and in today s still tremendous technological problems: diffusion of impurity centers is almost impossible, non-defective big surfaces are currently not realizeable and today s fundamental technologies for the margin design are not applicable to SiC. [282], [124], [130]. The integration of monitoring, protection and driver functions or power electronic circuits (monolithic, chip-on-chip or silicon-on-insulator) to the chip is more and more gaining importance in low-voltage (e.g. car electronics) or low-current (e.g. consumer products) batch applications. For example, driver-, protection-, system- and diagnostic functions have been integrated on one chip in the intelligent SMARTPOWER-transistors, leading to a reduction of power losses and to an improvement of the system reliability apart from the advantages of system miniaturization [277], [213], [232]. The simplest method is to generate e.g. protection- and sensor units to manage currents, voltages or temperatures on control supply potential by diffusion to the MOSFET- or IGBT-chip surface. Popular designs to be mentioned are the SENSFET and the Sense-IGBT, where source- or emitter current, respectively, are separated into a main circuit conducting the main current share and a parallelled measuring circuit. By inverse feedback of the measuring signal to the control circuit, the measuring current is reduced by increase of the sense-resistance [194]. Sense-IGBTs are integrated in many IPMs. The TEMPFET is equipped with an integrated temperature sensor, which is used as overcurrent indicator at the same time and which will short-circuit the gate-source-connection, in case a certain temperature limit has been exceeded. PROFETs and HITFETs, for example, contain a complete driver circuit with overcurrent-/shortcircuit-protection, overvoltage- and overtemperature-protection, gate-protection, load indicator, polarity protection, over- and undervoltage turn-off and a charge pump for generation of the gate voltage, e.g. [4], [277]. The PROFET is being produced as single- and multi-channel high-side switch up to a break-over voltage of 60V. In contrast to the high-side switch, there is not sufficient supply voltage generated for the protection logic during on-state of a MOSFET for a low-side switch. Therefore, an integrated 38

38 1 Basics temperature sensor in the HITFET will reduce the gate voltage at a high chip temperature that the drain voltage is able to increase to the minimum supply voltage-value of 3V and the protection circuit may react. With reference to [232], monolithic integration of whole inverters with power semiconductors, high-voltage ICs for driver/ protection and micro-electronic system control circuits is limited to 1A/ 600V (soon up to approx. 2A) and 5A/75V for the time being, the disadvantages compared to hybrid system integration of chips (currently up to 30A/ 1200V and up to 150A towards the year 2002) being the limitation of the blocking voltage to 600 V, restricted ruggedness reffering to short-circuit- and pulse-currents and tripled losses in the used lateral transistors in contrast to vertical transistors. 1.3 Free-wheeling- and snubber-diodes Demands to free-wheeling and snubber-diodes Modern fast switching devices require fast diodes as free-wheeling diodes. With every turn-on of the switch, the free-wheeling diode is commutated from conductive to blocking state. At this process, it has to show soft-recovery behaviour. For a long time, the importance of fast diodes had been underestimated. The performance of the switch had been impaired by the free-wheeling diodes. During the past few years, however, free-wheeling diodes had regained importance, and significant progress could be made by improving the reverse-recovery behaviour Reverse voltage and forward voltage drop The reverse voltage V R indicates that, at a specified voltage, the leakage current must not exceed the limit current I R. The specifications in the databooks are indicated for an operating temperature of 25 C. In the case of lower temperatures, the blocking capability will decrease, e.g. by approximately 1.5 V/K for a 1200V-diode. For components which are operated at temperatures below the ambient temperature, this has to be considered in the circuit layout. I F I V R I R V F V Figure 1.17 Definition of reverse and forward voltage of a diode At temperatures above the ambient temperature the reverse voltage will increase accordingly, however affecting an simultaneous increase of the leakage current. Therefore, a leakage current 39

39 1 Basics value is specified also for high temperatures (125 C or 150 C). In case of gold-diffused devices the leakage current can rise very steeply, which might cause thermal instability in circuits, where the whole system is operated at high temperatures due to the losses of the switching devices. V V FRM 1,1 V F V F 0,1 V F t fr t Figure 1.18 Turn-on behaviour of power diodes The continuous forward voltage V F indicates that, at a specified current, the forward voltage drop over the diode must not exceed the specified limit value. Typically, these limit values are specified at ambient temperature. A decisive factor in the power loss balance, however, is the forward voltage at higher temperatures. All datasheets of free-wheeling diodes should contain a note of this temperature dependency Turn-on behaviour When the diode passes over to conductive state, the voltage will at first increase to the repetitive peak forward voltage V FRM, before it drops to forward voltage level again. Figure 1.18 shows the currently valid definition of V FRM and the turn-on time t fr. This definition, however, does not give much information on the behaviour of free-wheeling and snubber-diodes for IGBTs, because - the rise of the on-state current di/dt is so high that e.g. V FRM may increase to 200V or even 300V for an unsuitable 1700V-diode, which is more than 100 times V F, - the diode is normally turned on f run the blocking state, generating a considerably higher V FRM than if it is turned on from its neutral state. A low V FRM -value is one of the most important requirements to snubber-diodes, since the snubber-circuit becomes effective only after turn-on of the diode. The repetitive peak forward voltage is also of importance for free-wheeling diodes, which are designed for a reverse voltage of > 1200V. When the IGBT is turned off, a peak voltage is generated over the parasitic inductances, which is still superimposed by V FRM of the freewheeling diode. The sum of both components may lead to critical voltage peaks. However, this measurement is not trivial, since the inductive component and V FRM cannot be told apart in the application conform chopper circuit. Measurements may only be made with the open construction directly at the bonding wires of the diode. 40

40 1 Basics On the other hand, turn-on behaviour of a diode is not important for the power loss balance, since turn-on losses only amount to a small percentage of the losses during turn-off and forward on-state and may therefore be neglected Reverse recovery behaviour When passing over from the conductive to the blocking state, the internal diode storage charge has to be discharged. This results in a current flowing in reverse direction in the diode. The waveform of this current is characterized as the reverse-recovery behaviour. Figure 1.19 shows the simplest circuit for the characterisation. L K S I L V K D Figure 1.19 Reverse-recovery test circuit S depicts an ideal switch, I L is the current source, V K a voltage source and L K stands for the commutation circuit inductance. After closing switch S, a soft-recovery diode will show a current and voltage characteristic as shown in Figure Figure 1.20 is an example for a soft-recovery behaviour of a diode. Figure 1.21 shows two examples for diode current characteristics with snappy switching behaviour. Firstly, the definitions are explained by referring to Figure

41 1 Basics V,I I t 0 t rr t irm 0 t w t s t f di/dt 0,2 I RRM I RRM di r /dt V V M t Figure 1.20 Current and voltage characteristic of the reverse recovery process of a soft-recovery diode in a circuit as shown in Figure 1.19 and definition of the characteristics of the recovery behaviour The commutation velocity di/dt is determined by voltage and inductance: di = dt V L K K At t 0 current is at zero passage. At t w the diode starts to block. At this instant, the pn-junction in the diode gets free of charge carriers. At t irm the reverse current is at its maximum I RRM. After t irm the current will fall to leakage current level, the current characteristic depends solely on the diode. If the current drops very steeply, this is called snappy recovery behaviour. If the current drops very softly, this is called soft recovery behaviour. The reverse recovery time t rr is defined as the time between t 0 and the time, where the current has dropped to 20 % of I RRM. The subdivision of t rr into t f and t s shown in Figure 1.20 defines as quantitative value for the recovery behaviour: t Soft factor s = t f s This definition is insufficient, because, as a consequence, the current characteristic as in Figure 1.21a would be snappy. The characteristic in Figure 1.21b, however, would be classified as soft even though t f > t s holds, there is a hard snapp-off. (1.1) (1.2) 42

42 1 Basics ts t f t s t f 0,2 IRRM 0,2 IRRM a) b) Figure 1.21 Current characteristic for two different possibilities of snappy reverse recovery behaviour Better is the definition: Soft-factor di I = 0 S = dt (1.3) di r max dt Measurements have to be taken at a current flow of less than 10 % and of 200 % of the specified current. By this also the charactertistic in Figure 1.21b will be defined as snappy. Moreover, this considers that small currents are extremely critical for the reverse-recovery behaviour. The occurring overvoltage is determined by di r /dt according to the inductance law V ind = L K di r dt max Therefore, overvoltage occurring under certain measuring conditions or the peak voltage V M = V K + V ind may also be seen as characteristics for the recovery behaviour. V K and di/dt have to be figured in this context. But also this definition is not sufficient, because it still neglects the following parameters: 1. Temperature. Mostly, high temperatures have a negative influence on the recovery behaviour. But for certain fast diodes, the recovery behaviour will get worse at ambient temperature or at lower temperatures. 2. Applied voltage. Higher voltages will lead to impaired reverse recovery 3. Rate of rise of commutation current di/dt. The dependency on di/dt is very different for diodes of various manufacturers. Some types of diodes react more softly with increase of di/dt, other types behave more snappy. All these different influences may not be summarized in one simple definition of quantity. Therefore, the circuit in Figure 1.19 and the definitions according to (1.2) or (1.3.) are only usefull to explain the effects of the single production parameters of diode behaviour. An overall estimation of reverse recovery behaviour can only be made under application-related conditions. An application-related measuring circuit is shown in Figure (1.4) 43

43 1 Basics + L σ1 R Gon V K Driver R Goff V I L L σ2 L L L σ3 - Sensor I Figure 1.22 Application-related chopper circuit of a step-down converter (double-pulse operation) for reverse recovery measurements The commutation velocity di/dt is adjusted by the gate resistor R Gon of the switching device. V K is the DC-link voltage. A parasitic inductance L σ1 is generated in the connections between capacitors, IGBT and diode. Figure 1.23 shows the IGBT control signals and the current flow within IGBT and diode under double-pulse operation. By turn-off of the IGBT, the load current will be taken over by the free-wheeling diode. As soon as the IGBT is turned on next time, the diode will be commutated, characterizing its recovery behaviour at that moment. During turn-on, the IGBT also takes over the reverse current of the free-wheeling diode. This procedure is depicted for a soft-recovery diode in Figure 1.24 at a higher resolution of the time axis. Figure 1.24a shows an IGBT current and voltage characteristic and also the turn-on power losses. Figure 1.24b shows the FWD-current and voltage characteristic as well as power losses. V(t) Driver I(t) t IGBT I(t) t FWD Reverse-Recovery-Current t Figure 1.23 Driver control signal, IGBT- and FWD-current waveforms in a circuit according to Fig (doublepulse operation) 44

44 1 Basics While the IGBT conducts the peak reverse current I RRM, the IGBT-voltage is still on DC-link voltage level (1200V in Figure 1.24a). This is the moment of maximum turn-on losses in the IGBT. The diode reverse recovery characteristic may be divided up into two phases: 1. The phase of increase up to the reverse peak current and the consequent reverse drop current with di r /dt. di r /dt is within the range of di/dt as far as a soft-recovery diode is concerned. The peak reverse recovery current I RRM exerts most stress on the switching device. 1200V V IGBT turn-on IRRM Diode 150A I P=V*I Eon Won P:10 5 W/div 0 SKM 200 GB 173 D T = 125 C 0 a) 200ns/div 0 150A Diode turn-off I V 0 IRRM -1200V tail current SKM 200 GB 173 D P=V*I Eoff 200ns/div T = 125 C 0 P:10 5 W/div b) Figure 1.24 Current, voltage and power losses during IGBT turn-on (a) and diode turn-off (b) for a measurement in a test circuit according to Figure The tail phase, where the reverse current slowly declines to zero. There is no point in defining a t rr. The main power losses in the diode are due to the tail phase, where voltage has already been applied to the diode. A snappy diode without tail current would cause less 45

45 1 Basics switching losses, but would be unsuitable for the application. In the IGBT, the switching losses during the tail phase are not that extreme, because the applied voltage has already decreased at that time. Compared to IGBT switching losses, the losses the diode are low in the application (diode switching losses in Fig. 1.24b are drawn to the same scale as the IGBT switching losses in Fig. 1.24b). In order to keep power losses of both, IGBT and diode, as low as possible, it is important to care for a small peak reverse current and to have the main part of the storage charge discharged during the tail phase. A limit to this is set by the maximum switching losses that can be dissipated in the diode. The peak reverse recovery current I RRM is the most important parameter for the diode taking influence on the total losses. Therefor it should be minimized. In a typical application, where the chopper is in a semiconductor module, the parasitic inductance L σges is in the range of 40nH, reducing the generated overvoltage. Due to lack of ideal switches, the voltage applied to the IGBT will drop to a certain degree during the recovery phase. The voltage taken becomes di R V(t) = VK L σges + V dt CE (t) with V CE (t) being the voltage still applied to the IGBT at the respective time. It is typical of softrecovery diodes that, for moderate rates of rise up to 1500A/µs and minimized parasitic inductances, V(t) is smaller than V K at any time and that there will be no voltage peaks (1.5) max [V] Platinum-diffused Diode Conditions: V K = 800 V di/dt = 1200 A/µs T j = 150 C CAL-Diode Forward Current [A] Figure 1.25 Peak voltage during commutation in dependence of forward on-state current as a parameter for the switching behaviour of diodes Figure 1.25 gives an example for characterization of the recovery behaviour by this method. In these conditions, the overvoltage occurring in a CAL-diode has been compared to that occurring in a diode, the charge carrier life of which had been adjusted by platinum-diffusion, showing soft-recovery behaviour by reduced p-emitter efficiency. A platinum-diffused diode behaves as soft as a CAL-diode at rated current (75A). Smaller currents, however, will cause overvoltages up to a maximum of more than 100 V at 10 % of rated current due to snappy switching behaviour. Even smaller currents are switched more slowly by the applied IGBT, affecting a 46

46 1 Basics decrease of overvoltage. In contrast to that, there will be no substantial overvoltage on any of those conditions with CAL-diodes. All further explanations in this manual are based on the following definition: A diode shows soft-recovery behaviour, if, in all conditions relevant to the application in an application-related circuit, no overvoltage occurs, caused by reverse current snap-off due to the diode. Relevant conditions being the total current range, all commutation velocities useful for the application and the temperature range of -50 C up to +150 C. This definition is valid as long as di/dt is not too high (> 6 ka/µs) or high parasitic inductances (> 50 nh) are applied, which might lead to circuit-dependent voltage peaks also with soft-recovery diodes. An equally important requirement for free-wheeling diodes with a voltage from 100V upwards (apart from soft switching behaviour) is dynamic ruggedness. Figure 1.24b shows that nearly the whole DC-link voltage is taken up by the diode, while it is still conducting a substantial tail current. If the IGBT is switched very steeply (small gate resistance R G ), reverse current and tail current will rise, at the same time causing a decrease of V CE at the IGBT, which switches over to the diode with a respectively higher dv/dt. The density of the current-carrying charge carriers (holes) will then be above the original doping density, the consequence of which will be an inevitable avalanche breakdown in the semiconductor at applied voltages far below reverse voltage level (dynamic avalanche). To manage these operating conditions is characteristic of the dynamic ruggedness of a free-wheeling diode. The dynamic ruggedness may be defined as follows: The dynamic ruggedness is the ability of a diode to manage high rates of rise of commutating di/dt and a high DC-link voltage at the same time. If the diode shows no sufficient dynamic ruggedness, manufactures limit the di/dt of the IGBT or admit only a maximum reverse recovery peak current of the diode thus accepting increased switching losses Demands on free-wheeling diodes used in the rectifier and inverter mode of voltage source converters Free-wheeling diodes in IGBT- or MOSFET-converters have to cope with different requirements depending on whether they are used in rectifiers or inverters with the same power regarding the power losses occurring. Typically, the average energy flow in inverter mode is directed from the DC-link to the AC-side, i.e. a consumer is connected to and supplied by the AC-side (e.g. three-phase motor). On the other hand, the average energy flow in rectifier mode is directed from the AC-side to the DC-link. In this case the converter works as a pulse rectifier connected to an AC-mains or generator. Although the power performance in both cases is the same, the power semiconductors are subject to different power losses basically due to the opposite phase shift between voltage and current on the AC-side, when in rectifier or inverter operation. This can be explained using to the basic circuit in Figure

47 1 Basics i IGBT1 i Diode1 V d /2 IGBT T1 Diode D1 V out i L V d /2 IGBT T2 Diode D2 i IGBT2 i Diode2 V, i V out(1) V d/2 V out i L -V d/2 Figure 1.26 Basic circuit of a converter phase with IGBTs and free-wheeling diodes It shows: - if v out = positive and i L > 0: current flow over IGBT 1, - if v out = negative and i L > 0: current flow over diode 2, - if v out = positive and i L < 0: current flow over diode 1, - if v out = negative and i L < 0: current flow over IGBT 2. Consequently, the IGBT- and FWD- on-state power losses occurring at a given RMS-current value are dependent on the cos phi between voltage and current fundamental frequency as well as on the modulation factor m of the converter (determines duty cycles). In the case of inverter-operation 0 m * cos phi 1. Power losses in semiconductors reach their limits, if m * cos phi = 1. In this case maximum on-state losses and, therefore, total losses in the IGBTs have been reached, whereas losses in the free-wheeling diodes are at their minimum. In the case of rectifier operation 0 m * cos phi -1. Power losses in semiconductors reach their limits, if m * cos phi = -1. In this case, minimum on-state losses and, therefore, total losses in the IGBTs have been reached, whereas losses in the free-wheeling diodes are at their maximum. Applied to the characteristics in Figure 1.26, this situation is given when the fundamental 48

48 1 Basics frequency of the pulse rectifier converts pure active power from the line and the neutral point of the line is connected to the centre point of the DC-link voltage. This is illustrated with the graphs in Figure 1.27 with an example. IGBT 1200 V / 50 A; V d = 540 V; I Leff = 25 A; T j = 125 C 30 Forward Losses [W] IGBT Diode ,8-0,6-0,4-0,2 0 0,2 0,4 0,6 0,8 1 m*cos phi 25 Switching Losses [W] IGBT Diode Switching Frequency (khz) Figure 1.27 Switching and forward on-state losses of IGBT and free-wheeling diode in a VSI At given DC-link voltage and RMS-AC-current values the switching losses of the components are merely dependent (linear) on the switching frequency (Figure 1.27). A large number of the available IGBT and MOSFET modules with integrated free-wheeling diodes are dimensioned for being applied in inverters regarding the power losses that may be dissipated at rated current (e.g. cos phi = ). Due to their reduced on-state and total losses, diodes have been designed for a considerably lower dissipation of power losses compared to IGBTs (ratio IGBT : diode 2..3:1). Therefore, the use of power modules with higher rated current is recommended when dimensioning pulse rectifiers with the same converter power as a corresponding pulse inverter. Example: Driving system: * Power supply (400 V/50 Hz) pulse rectifier (f s = khz) DC-link pulse inverter (f s = khz) three-phase motor (400 V/50 Hz/22 kw) 49

49 1 Basics * Pulse rectifier with standard IGBT-modules (phase leg) 1200 V/100 A (T c = 80 C) * Pulse inverter with standard IGBT-modules (phase leg) 1200 V/75 A (T c = 80 C) This difference is not required for power modules with higher rated diodes Structure of fast power diodes We have to distinguish between two basic types: Schottky-diodes and pin-diodes. In Schottky-diodes, the metal-semiconductor junction serves as blocking junction. There is no diffusion voltage at the pn-junction as in pin-diodes; this guarantees a lower on-state voltage as with any pin-diode, provided the n - -zone is very thin. When passing over from conductive to blocking state, ideally only the space charge zone has to be charged. Due to this, the component is suitable for very high frequencies (> 100 khz). This advantage is, however, restricted to voltages < ~ 100 V. In this range, the Schottky-diode is the appropriate free-wheeling diode for a MOS-transistor. If, on the other hand, the component is dimensioned for higher voltages, - the on-state voltage will rise considerably, since w B increases and only one sort of charge carriers is available (unipolar) and - the leakage current will rise considerably, which will cause thermal instability. w n- n + Schottky- Barrier p n- p n- w B n+ n+ Schottky-Diode Epitaxial-Diode Diffused Diode N,N A D n + p + n + p + n + n - w n - w w n - Figure 1.28 Schottky-, pin-epitaxial - and pin-diffused diode structures Top: structure Bottom: doping profile (scheme) The advantages of pin-diodes become effective in the range of more than 100V. In diodes produced today, the middle zone is not i (intrinsic), but of n-type with a very low doping level (n - ) compared to the marginal zones. In pin-epitaxial-diodes (Figure 1.28, mid) a n - -zone is separated from the highly-doped n + -substrate (epitaxy). Then, the p-zone is diffused. By this technology, a very small base width w B down to some µm may be produced, the silicon wafer being thick enough to manage high production yields. By diffusion of recombination centres 50

50 1 Basics (mainly gold-diffusion) very fast diodes can nevertheless be produced with a low forward onstate voltage due to the small w B. However, the on-state voltage will always be above the diffusion voltage of the pn-junction of 0.6 to 0.8 V. The main applications of epitaxial (epi-) diodes are within the range of 100 V and 600 V, some manufacturers are even producing epidiodes for 1200 V. From 600 V upwards the n - -zone will be enlarged to such an extent that a diffused pin-diode (right Figure) may be produced. The p- and n + -zones are diffused into the n - -wafer. Similar, recombination centres are necessary to adjust the dynamical characteristic. As the major applications of power modules are within the range above 100 V, pin-diodes will be explained in more detail in the following Characteristics of fast power diodes As for free-wheeling diodes, a compromise has to be found for optimizing the contrasting requirements. Therefore, we have to come up against the physical limits of the material, which makes the design of excellent free-wheeling diodes very sophisticated Forward and blocking behaviour In forward direction, there is the pn-junction and the resistance of the adjacent n - -zone. The voltage drop is composed of V = V + V f diff ohm The pn-junction diffusion voltage V diff is dependent on the doping of both pn-junction sides and is, typically, between V. For fast diodes with a blocking voltage of 600V and more, the ohmic part prevails. Charge carrier lifetime of free-wheeling diodes has to be kept very low so that the on-state voltage will depend exponentially on the base width w B and the charge carrier lifetime τ [283]: (1.6) V Ohm 3πkT = e 8q w B 2LA L A is the ambipolar diffusion length L A = D τ A, with the ambipolar diffusion constant k: Boltzmann-constant; J/K q: electronic charge; C D A µ nµ p kt = 2. µ + µ q n p (1.7) µ n and µ p stands for the mobility of the electrons and holes on condition of a n - -zone flooded by free electrons and holes [284]. Due to this exponential correlation, the smallest possible w B should be selected. In spite of this, the base width w B has a definite influence on the blocking voltage. Two different cases may occur (see Figure 1.29): If w B has been dimensioned in such a way that the space charge zone cannot protrude into the n + - zone (triangular characteristic), this is called non-punch-through structure [285]. If w B has been dimensioned in such a way that the space charge zone will protrude into the n + -zone, the characteristic will be trapezoidal, which will be called punch-through-diode. However, a real punch-through, where the space charge zone would reach the area of another doping type, is not realized in this case. Nevertheless, the designation has generally been accepted. 51

51 1 Basics E 0 E 0 p -E(w) n+ p -E(w) n+ n - 0 w w B n- 0 w non-punch-through (NPT) -Diode punch-through (PT) -Diode a) b) E 1 wb w* Figure 1.29 Dimensioning of a diode for triangular (a) and trapezoidal (b) characteristic For an ideal NPT-diode w B is dimensioned so that it is located at the end of the triangular characteristic. If the doping is optimal, the minimum width for w B would then be w = 2 B 2 3 C 1 6 V 7 6 R (1.8) with C = 1.8*10-35 cm 6 V -7 Minimum doping necessary for PT-diodes can be calculated similarly. As a extreme, the characteristic would be rectangular, E 1 = E 0 (see Figure 1.29). Consequently, w (PT, extreme) = C B 1 6 V 7 6 BD Compared to w B of the NPT dimensioning (1.8): w B (PT, extreme) = w B (NPT) 0.63w B (NPT) This extreme case, however, may not be achieved, but with the existing technology it may be approximated by w B (PT) 0.66 w B (NPT) (1.9) (1.10) (1.11) The difference between PT-structure according to (1.11) and NPT-structure according to (1.8) adds up to about 0.8 V on-state voltage, considering the necessary low charge carrier lifetime. Therefore, PT-structure should be preferred Turn-on behaviour When the diode is turned on, it has to overcome the resistance of the low-doped base. Therefore, the turn-on peak voltage will increase proportionally to w B. The turn-on peak voltage becomes critical, especially if a significant base width w B has to be chosen due to a high blocking voltage over 1200V. In this respect, PT-diodes will show optimized turn-on behaviour. Free-wheeling diodes always contain recombination centres. For free-wheeling diodes dimensioned for applications of 1200V and more, recombination centres that cause increase of the base resistance have to be avoided. A like recombination centre would be one that had been generated by gold-diffusion. Recombination centres generated by platinum-diffusion, electron 52

52 1 Basics beam radiation or light ions will only slightly increase the turn-on overvoltage in comparison to diodes without recombination centres Turn-off behaviour The turn-off behaviour of fast diodes is determined by the way in which the charge declines to zero. Figure 1.30 shows the procedure for a snappy diode, Figure 1.31 for a soft-recovery diode. 1E+20 N A, N D, p 1E+18 Charge Carrier Hill n + t 0 1E+16 p Hole Current t 2 t 3 t 4 t 2 Electron Current 1E+14 t 5 n - t w in µm Figure 1.30 Diffusion profile and decline of charge carriers (density of holes) in a snappy diode (ADIOS-simulation) During on-state, the n - -zone is flooded by > cm -3 electrons and holes, the concentration of electrons n and holes p presumably being the same. After commutation the charge carrier hill is within the n - -zone between t 2 and t 4, provided n p. The decline of charge carriers towards the cathode is effected by the flow of electrons, that move towards the anode by the flow of holes, which flow as reverse current in the outer circuit. In case of the snappy diode in Figure 1.30 the charge carrier hill declines to zero shortly after t 4. Between t 4 and t 5 the diode will suddenly turn from its state with charge carrier hill to a state without charge carrier hill, the reverse current snaps off. The switching behaviour of the diode is snappy. Figure 1.31 shows the same procedure for a soft-recovery diode. A charge carrier hill feeding the reverse current is kept during the whole procedure. At t 5 the diode has already taken on the applied voltage. The procedure described in Figure 1.31 will lead to a tail current as shown in Figure Whether soft-recovery behaviour is reached or not, depends on the successful reduction of charge carriers. This is difficult to achieve by microstructures on the surface, a technology where the semiconductor industry has made an enormous progress in the past. Therefore, it has taken a relatively long period of time until the reverse recovery behaviour could be controlled. 53

53 1 Basics 1E+20 N A, N D, p 1E+18 Charge Carrier Hill n + 1E+16 p t 0 Hole Current t 2 t 3 t 4 t 5 t6 Electron Current 1E+14 n - t 5 t w in µm Figure 1.31 Diffusion profile and decline of charge carriers (density of holes) in a soft-recovery diode (ADIOSsimulation) The following measures will effect a softer recovery behaviour: 1. The basis width w B of the n - -zone is enlarged, NPT-dimensioning is applied (see equation (1.9)), an additional zone is generated in the diode, which is not reached by the field at rated voltage. But this will lead to extreme increase of the on-state voltage (see equation (1.7)) or the V F /Q RR -ratio. Nevertheless, this inconvenience is accepted even in lately developed solutions (as mentioned e.g. in [286]). 2. In order to slightly neutralize the w B -increase, a two-phase n - -zone may be applied [287] showing a highly doped area near to the nn + -junction. In Figure 1.30 and 1.31 a similar effect is realized by a flat gradient at the nn + -junction. This measure on its own will not be sufficient in order to reach soft-recovery behaviour. 3. Inversion of the charge carrier distribution by a low-efficiency p-emitter (see chapter ). 4. An axial charge carrier lifetime profile, providing for a low charge carrier life at the pnjunction, and a longer charge carrier life at the nn + -junction (see chapter ). To guarantee for soft-recovery behaviour on any condition, usually several of those measures have to be taken at the same time. Progress in this respect has always to be assessed on consideration of the acceptance of a high on-state voltage drop or a higher Q RR Dynamic ruggedness While the space charge zone is increasing, a hole current, carrying I R, is flowing through the empty area of the n - -zone. Therefore, the density p of the holes is: I p = qv R d A (1.12) In this equation, v d stands for the drift velocity (7.57 * 10 6 cm/s) and A for the area of the diode. 54

54 1 Basics The hole density (shown in Figure 1.30 and 1.31 from t 2 to t 4 each) must no longer be neglected with respect to the basic doping level [288]. P is added to the positively charged donators N D, the effective doping N eff at that moment is N eff = N D + p (1.13) This will cause premature avalanche breakdown. Electrons and holes will be generated at the pnjunction by dynamic avalanche. The holes will move through the highly doped p-zone. On the other hand, the electrons will move through the n - -zone, causing an effective doping N eff = N D + p n av (1.14) Here, n av stands for the density of the electrons generated by dynamic avalanche, which move from the pn-junction through the space charge zone, partly compensating the hole density and thus counteracting the avalanche effect. In [289] dynamic avalanche is designated as a selflimiting effect: it is limited to a degree which is just sufficient to manage the field intensity resulting from the reduced effective doping. Consequently, the diode is not likely to be destroyed by dynamic avalanche. Reduced forward current will cause reduced reverse current, and consequently reduced density of holes p (according to (1.12)). But, since the switching devices have a higher dv/dt at smaller currents, stress caused by dynamic avalanche may be higher, if small currents are applied. For diodes dimensioned for higher blocking voltages, τ has to be increased due to the enlarged w B. This will cause higher reverse currents, leading to increased hole density and to dynamic avalanche according to (1.12). But dynamic ruggedness is especially important for the application in this case Modern diodes with optimized recovery behaviour Emitter conception In the conventional pin-diode the pn-junction is flooded by more charge carriers than the nn + - junction (Figure 1.30). The idea of the emitter conception is to invert the charge carrier distribution: the nn + -junction is to be flooded by more charge carriers than the pn-junction. This is achieved by reducing the injection quantity at the p-emitter. p+ p+ Schottky- Barrier n - p n - n+ n+ a) b) Figure 1.32 P-emitter for improvement of soft-recovery behaviour: a) Emitter structures, e.g. the merged PiN/ Schottky diode b) Reduced p-doping 55

55 1 Basics Various emitter structures had been considered, which, in summary, would meet this effect by their functions. One example is the merged PiN/Schottky-diode, consisting of a sequence of p + -zones and Schottky-areas [290] (Figure 1.32a). There is a number of structures similar to that, comprising also structures with diffused p- and n-zones. The advantages of Schottky or similar zones, however, are restricted to voltages below 600V. As for blocking voltages of 1000 V and more, the ohmic potential drop will prevail. Only the reduced injection area at the p-zone remains. The same effect as with emitter structures is achieved by a continuous low-doped p-zone (Figure 1.32b). On balance the result of the application of these structures is that they have not lived up to the set expectations. Also the latest developments are aiming at the reduction of the emitter doping quantity and, thus, the improvement of recovery behaviour. [132], [291]. Further progress can be made by reducing the depth of penetration. However, with a di/dt-rate of more than 1000 A/µs, some diodes with reduced p-doping do not show sufficient dynamic ruggedness. Figure 1.33 shows a failure statistics considering more than 16 production lots with free-wheeling diodes altogether. The failure results in a hole within the active area of the diode. This points to filamentation. According to statistics, the number of failures caused by low-doped diodes and therefore higher resistance in the p-zone (Figure 1.33, 160 Ω/squ) was higher than that of diodes with reincreased doping (Figure 1.33, 60 Ω/squ), but those had shown impaired soft switching behaviour. This demonstrates the contrast of both requirements to this technology: soft switching behaviour on the one hand, and dynamic robustness on the other hand. Even accepting the restriction of soft switching behaviour could not completely avoid failures. In order to guarantee safe field application, all modules had to be subjected to a full load test in a chopper circuit under field conditions. 3 2,5 2,47 2 1,5 1,31 1 0,5 0 0,15 0,33 0,18 0,04 0,38 0,23 0,04 0,00 0,19 0,00 0,12 0,19 0,19 0,16 Production Lot 160 Ohm/squ 60 Ohm/squ Figure 1.33 Proportion of failures of diodes with reduced p-doping for several production lots (at very high di/dt) It seems possible that the failures in Figure 1.33 may be reduced by technological optimization. However, it remains doubtful whether they can be completely avoided. SEMIKRON has, at least, stopped any developments related to the emitter conception for freewheeling diodes in fast switches. 56

56 1 Basics Controlled Axial Lifetime (CAL) - conception Recombination centre profiles similar to those shown in Figure 1.34a and 1.34b can be generated by implantation of protons or He ++ -ions in silicon. Some time ago, this technology which required accelerators performing up to 10 MeV, had been exclusively reserved for research purposes, but the situation has changed. Basic research is interested more and more in the GeVrange, and medium energy accelerators are available for other fields of application. N A,ND N rek N rek N A,ND N rek p + n + p + n + a n - b n - Figure 1.34 Axial profile of recombination centres generated by light ion radiation a) Narrow partial zone with higher concentration of recombination centres in the middle of the n - -zone b) Narrow zone with high concentration at pn-junction The first assumption, that the best results could be achieved by implantation of a zone of highly concentrated recombination centres in the middle of the n - -zone as depicted in Figure 1.34a, had proven wrong. The arrangement of such a zone at the pn-junction as in Figure 1.34b turned out to be more favourable [292] [293]. Reference [147] explains that the relation between peak reverse current and forward on-state voltage is improved with approximation of the recombination centre peak to the pn-junction. If the recombination centre peaks are arranged directly at the pn-junction, the charge carrier distribution will be inverted during on-state. The charge carrier distribution shown in Figure 1.31 results from a calculation based on the recombination centre profile according to Figure As for the CAL-diode, the recombination center peak (generated by He ++ -implantation) has been arranged in the p-zone close to the pn-junction as in Figure 1.35, since this will lead to reduction of leakage currents. He ++ -implantation has been combined with an adjustment of the basic charge carrier lifetime, preferably achieved by electron beam radiation. 57

57 1 Basics Ba 1E+16 Recombination Centers Peak 1E+15 rec [cm-3] 1E+14 Basic-Recombination Center Density p n - n + 1E x [µm] Figure 1.35 Recombination centre profile in the CAL-diode (scheme) The characteristics of a CAL-diode in combination with an IGBT have already been referred to in Figure The reverse peak current can be decreased by the recombination centre peak level, which is to be adjusted by the He ++ -implantation dose. The biggest share of the storage charge of the CAL-diode occurs in the tail current, which, on the other hand, can be controlled by the basic recombination centre density. Reduction of the basic charge carrier lifetime will reduce tail current duration, however at increase of the on-state voltage of the diode. Recovery behaviour can be greatly controlled by both parameters, basic charge carrier lifetime and He ++ - implantation dose. So the diode will show soft-recovery behaviour under any operating conditions, especially when low currents are applied. CAL-diodes manufactured this way are proving a high dynamic ruggedness. CAL-diodes dimensioned for 1200 V and 1700 V have been tested under lab conditions at di/dts up to 15 ka/cm²µs without destruction of the diode. CAL-diodes are especially not likely to fail under the operating conditions shown in Figure This fact is based on the production of over 26 million CAL-diodes up to now. A ruggedness test of a 3,3 kv CAL-diode is shown in Figure In the measurements in Figure 1.35 stress on the diode is still intensified by an additional parasitic inductance of 0.5 µh, generating a peak voltage of 1500 V directly subsequent to the commutation. In contrast to other diodes, CAL-diodes may also be operated in this voltage range at a high di/dt (here 2000 A/cm²µs). 58

58 1 Basics I [A] U[V] V 100A C 1800A/µS Figure 1.36 Ruggedness test of a 3300 V-CAL-diode The base width w B can be dimensioned comparatively narrowly for CAL-diodes, similar to the PT-dimensioning indicated in equations 1.10 and This provides for a comparatively low on-state voltage or a better compromise between switching behaviour and on-state voltage, respectively. The base width is also of special importance to the turn-on behaviour of the diode. The forward recovery voltage V FR increases proportionally to w B; components designed for 1700V and more are likely to generate some 100 V V FR in the free-wheeling diode due to high di/dt during turn-off of the IGBT. In contrast to conventional diodes, V FR can be reduced by more than 50 % in 1700 V-CAL-diodes. [106]. Recently developed free-wheeling diodes for IGCTs as well as snubber-diodes [294] are being produced according to the CAL-conception, because 1. dynamic robustness is one of the most important demands, 2. dimensioning similar to PT-dimensioning results in an improved cosmic ray stability, 3. a favourable trade-off between on-state voltage and switching characteristics of the diode may be adjusted by the measure mentioned above, 4. minimum V FR can be achieved in snubber-diodes, 5. a low leakage current can be realized compared to the conventional gold-diffusion process The concept of hybrid diodes The concept of the hybrid diode was invented in 1991 [295], [296]. This conception is based on the idea that a soft-recovery diode is connected in parallel to a PT-diode with a low on-state voltage, but a snappy recovery behaviour, as shown in Figure

59 1 Basics Anode I I S I E p w S n - n + p n - n + w E soft-recovery Diode punch through Diode D S D E Cathode Figure 1.37 Structure of a hybrid diode The function principle is shown in Figure The main part of the on-state current is conducted by the snappy diode D E. The rest is conducted by diode D S. Current I S is conducted through diode D S and is the first to drop to zero passage, reaching its reverse current peak at t 1. At this time, diode D E is still carrying forward current. At t 1 the pn-junction of diode D S is free of charge carriers. Now, diode D E is commutated with increased di/dt. The total current is still determined by the outer circuit. I snap-off- Diode D E soft-recovery- Diode DS t4 t t 1 t 2 t 3 Figure 1.38 Current flow in the components of a hybrid diode At t 2 the pn-junction of D E is free of charge carriers. Between t 2 and t 3 the reverse current in D E will snap off. It will then rise accordingly in diode D S, which is not completely free of charge at that moment. The total current does not show a reverse current snap-off. Consequently, there will be no induced overvoltage. The charge carrier density in diode D S is reduced between t 3 and t 4. The combination behaves soft. To achieve efficient function of the hybrid diode, D S has to supply sufficient charge even after the reverse current snap-off of D E. To manage this, the soft diode D S has to take on between 10 % and 25 % of the forward current. Therefore, the forward voltages have to be attuned. 60

60 1 Basics The first modules that contained hybrid diodes were introduced to the market the beginning of They have been applied preferably as free-wheeling diodes in chopper circuits with 100Vor 200V-MOSFET switches. Here, an epitaxial diode designed for 400V is used as snappy diode D E. The part of the soft-recovery diode D S is taken over by a modified CAL-diode. The basic recombination centre density in it is kept on low-level, which results in a forward voltage of about 1.1 V at 150 A/cm². V V on [ns] on [ns] Figure 1.39 Voltage characteristic in a 350 A, 100 V chopper module, on the left: with epitaxial diodes, on the right: with a hybrid diode Figure 1.39 shows the voltage taken at turn-on of the MOSFET in a 350 A/100 V chopper module. The diagram to the left shows the voltage characteristic for the free-wheeling diode being realized by parallelling of 7 epitaxial diodes. The diagram to the right shows the voltage characteristic, if one of the 7 epitaxial diodes has been replaced by the soft-recovery diode D S. The induced peak voltage will decrease from 100 V to 33 V, the interfering oscillations will disappear. By application of a like free-wheeling diode, the MOSFET can be turned on with a high di/dt. If the turn-on time of the MOSFET is reduced from 1.3 µs to 0.3 µs by decreasing the gate resistance, the voltage characteristic will still be acceptable. Total losses of the circuit will drop to 48 % (= sum of line- and switching losses of all components). Hybrid diodes are of special advantage in a voltage range of 600 V. In this range, diodes with a minimum w B may be applied, if they are integrated as part of a hybrid diode. On the other hand, hybrid diodes will not offer decisive advantages to high-voltage applications, since differences in w B between soft-recovery CAL-diodes and PT-diodes are not that serious Series and parallel connection of fast power diodes Series connection In series connections, attention must be paid to the symmetry of circuits with respect to static reverse voltage and with respect to the dynamic reverse voltage. 61

61 1 Basics C R C R Figure 1.40 RC-circuit for series connection of fast diodes With reference to the static reverse voltage, the variation of leakage current due to production processes will drive the components with the lowest leakage current to avalanche mode. As long as the avalanche stability of the components can be relied on, no resistors will have to be connected. If, however, components with a blocking capability of > 1200 V are connected in series, it is common practice to parallel a resistor. This parallel resistor has to be dimensioned with respect to the fact that voltage distribution is always determined by its resistance. If the leakage current is supposed to be independent of the voltage and if resistance tolerances are neglected, the simplified rule for dimensioning the resistance for series connection of n diodes of a specified reverse voltage V r will be [297] : nvr Vm R < (n 1) I r (1.15) V m stands for the maximum series voltage and I r for the maximum spread of leakage current in the diode, based on the maximum operating temperature. According to [297] it may be supposed with high confidence that I r = 0.85 I rm, (1.16) with I rm being specified by the manufacturer. According to this estimation, the current conducted through the resistor is approximately 6-times the leakage current in the diode. Considering existing experiences, it will be sufficient for modern free-wheeling diodes to dimension the resistor in such a way that it will carry a current three times as high as the maximum leakage current of the diode. However, even then considerable power losses are generated within the resistor. Dynamic voltage distribution may differ basically from static voltage distribution. If the pnjunction in one diode is free of charge carriers earlier than in another one, this diode will also take on voltage earlier. If capacitor tolerances are neglected, a simple dimensioning rule can be used for this capacitor paralleled to a series connection of n diodes of a specified reverse voltage V r : 62

62 1 Basics (n 1) Q C > n V V r RR m (1.17) Q RR stands for the maximum variation of storage charge of the diodes. In all probability, it can be supposed that Q RR = 0.3Q RR (1.18) if all diodes used are taken from the same production lot. Q RR is specified by the semiconductor manufacturer. The charge stored in this capacitance is maintained in addition to the storage charge generated when the free-wheeling diode is turned off and has also to be taken up by the IGBT during turn-on. Based on these dimensioning rules, the occuring charge will be up to twice the storage charge of a single diode. Free-wheeling diodes are usually not connected in series, due to the following additional sources of power dissipation: - n-fold diffusion voltage of the pn-junction, - power losses in the parallel resistor, - increased storage charge to be taken up by the IGBT, - more components necessary for the RC-circuit. This holds, if a freewheeling diode for the required voltage range is available. Series connection may however be made exceptionally, if the on-state power losses are not of considerable importance and if the application is dependent on short switching times and low storage charge, which is typical for low-voltage diodes Connection in parallel Connection in parallel does not require any additional RC-circuit. It is important for parallel connection that the variation of the on-state voltage is kept as low as possible. A decisive parameter to assess the parallelling capability is the temperature dependency of the on-state voltage. If the on-state voltage drops due to increasing temperature, the temperature dependency of the on-state voltage will be negative, the only advantage of which can be noticed in the power loss balance. If the on-state voltage rises due to increasing temperature, the temperature dependency will be positive. V[V] V[V] Figure 1.41 Temperature dependency of the forward on-state voltage for different types of diodes Left side: extremely negative temperature dependency Right side: positive temperature dependency above rated current (75 A) 63

63 1 Basics A positive temperature dependency is of advantage for the application-specific parallelling, since a heated diode carries less current and the system stabilizes. An extremely negative temperature coefficient (> 2 mv/k) involves the risk of thermal instability for parallel connection of diodes, which always show spreading of the forward on-state voltage due to production processes. Parallelled diodes are thermally coupled - via the substrate in case of parallelling within the module, - normally via the heatsink in case of parallelling of modules. Principally, at a slightly negative temperature coefficient, this coupling effect will be sufficient to avoid thermal runaway of the diode with minimum on-state voltage. For diodes with a negative temperature coefficient of > 2 mv/k we recommend selecting a lower total rating than the current of the single diodes would add up to (derating). 1.4 Power modules: special features of multi-chip structures Structure of power modules In a power module several power semiconductors (MOSFET or IGBT chips and diode chips) which are electrically isolated from the mounting surface (heatsink) are integrated into a case on a common base plate. The chips are soldered (or glued) to the metallized surface of an isolation substrate, which electrically isolates the chips from the module base plate, and at the same time creates good thermal conductivity. The chip top sides are connected to the structured areas of the metallized surface by thin Al-bond wires. In addition to that, passive elements such as gate resistors, shunts/ current sensors or temperature sensors (e.g. PTC-resistors) may be integrated into the module (hybrid) and also partly into the transistor chips (monolithic). Moreover, intelligent power modules contain additional protection and driver circuits, see chapter 1.6. The currently used isolation substrates for power modules are listed in the table below: Isolation material ceramic: aluminum oxide Al 2 O 3 organic: epoxy aluminum nitride AlN polyimide (Kapton) (beryllia oxide BeO) (silicon carbide Si 3 N 4 ) Substrates Metal sheets: (Direct Copper Bonding) Metal sheets: IMS (Insulated Metal Substrate) AMB (Active Metal Brazing) Multilayer-IMS Thick film layers: TFC (Thick Film Copper) DCB (Direct Copper Bonding) Figure 1.42 shows the structure of a power module with IGBTs and free-wheeling diodes in the most common current technology with substrates made of DCB-ceramics with Al 2 O 3 or AlN isolation, combining good thermal conductivity and high isolation voltage. 64

64 1 Basics Diode-Chip IGBT-Chip Solder DBC Substrate Solder Cu-Baseplate C1 E1 G1 E2 C2,E1 E2 G2 3 C1 C2 2 1 E2 E1 G2 E2 G1 E1 Figure 1.42 Structure of an IGBT module SKM100GB123D in a SEMITRANS 2 case For production of a DCB-substrate, copper surfaces with a thickness of e.g. 300 µm are applied to the top and bottom areas of the isolation material (thickness mm) by means of eutectic melting over 1000 C. After the necessary track structure for the module circuitry has been etched into the top side copper surface, the chips are soldered on, and the connection to the contacts on the chip top side is effected by bonding. The bottom side of the DCB-ceramic substrate is fixed to the module base plate (thickness e.g. 3 mm) mainly by soldering, see Figure Other module types (e.g. SEMITOP, SKiiPPACK, MiniSKiiP) do not necessarily require a base plate and the previous soldering procedure may be avoided. In these modules, the DCB-substrate is pressed on to the heatsink by means of suitable case constructions (see chapter 1.5). Advantages of the DCB-technology compared to other structures are mainly the high current conductivity due to the copper thickness, good cooling features due to the ceramic material, the high adhesive strength of copper to the ceramic (reliability) and the optimal thermal conductivity of the ceramic material [52]. AMB (Active Metal Brazing) The AMB process ( brazing of metal foil to substrate) has been developed on the basis of DCB technology. The advantages of AMB-substrates with AlN-ceramic materials compared to 65

65 1 Basics substrates with Al 2 O 3 -ceramic materials are e.g. lower thermal resistance, lower coefficient of expansion and improved partial discharge capability. Figure 1.43 explains the differences between DCB and AMB. eutectic copper/ copper oxide DCB copper AMB solder silver/ copper/ titanium ceramic aluminium oxide Figure 1.43 Direct Copper Bonding (DCB) and Active Metal Brazing (AMB) IMS (Insulated Metal Substrate) IMS is mainly applied in the low cost/ low power range and is characterized by direct connection of the isolation material to the module base plate. For insulation, polymers (such as epoxies, polyamides) are usually applied to an aluminum base plate. The upper copper layer is produced in foil form and glued on the isolation substrate (similar to PCB production) and is structured by etching (Figure 1.44). Chip (Si ; 280 µm) Solder (SnAg ; 80 µm) Copper (Cu ; 100 µm) Isolation (Polyimid ; 125 µm) Baseplate (Al ; 3 mm) Figure 1.44 Basic structure of an IMS power module [194] Advantages of IMS are low costs, filigree structure of tracks (possible integration of driver and protection facilities), high mechanical robustness of substrate and relatively wide substrate areas, compared to DCB. The very thin isolation layer, however, leads to comparably high coupling capacitances against the mounting surface (see chapter ). Furthermore, the thin upper copper layer only provides a comparably low spread of heat, which is improved by additional metallized heat spreading layers under the chips or by adding Al-particles to the isolation layer. TFC (Thick-Film-Copper)-thick film substrates Just as with DCB, the basic material for thick film substrates is an isolation ceramic, which is glued directly on to the base plate or a heatsink by means of silicone or applied by soldering (Figure 1.45). The tracks on the top side of the ceramic substrate are made of copper and are applied by screen printing. The power semiconductor chips or other components are soldered or glued on to the tracks. 66

66 1 Basics Chip (Si ; 280 µm) Solder (SnAg ; 80 µm) Printed Conductor (Cu µm) Isolation (Al 2O 3 (96%) ; 380 µm) Adhesive (Silicone ; 35 µm) Baseplate (Al or Cu ; 3 mm) Figure 1.45 Basic structure of a TFC-power module [194] TFC-technology can also be combined with standard thick film technology. Since very low resistances may be produced by the paste materials which are usually applied in thick film technology, and since isolated tracks can be arranged one on top of the other and connected to each other, quite a number of system components may be integrated very closely together. However, the very filigree tracks (thickness e.g. 15 µm)will limit the current capability of such structures to about 10 A Features of power modules The assessment of parameters relevant for module assemblies will always depend upon the specific application. The most important parameter with respect to railway drives, for example, will be reliability, whereas low costs are the decisive criterion for the production of consumer goods. In this chapter, the applicability of a power module is to be regarded under the aspects of the following comprehensive criteria: optimized complexity of a module, heat dissipation capability, isolation voltage and partial discharge stability, temperature resistivity and loadcycling capability of the internal connections, internal low-inductance structure, static and dynamic symmetry of the structure, electromagnetic stability, defined and safe failure behaviour, simple assembly and connection technology and favourable, non-polluting production and recyclability Complexity Optimized complexity cannot be defined in general. On the one hand, complex modules will reduce appliance costs and minimize problems encountered when several components are to be combined (parasitic inductances, interferences, wrong wiring). On the other hand, increasing complexity will impair the universality of a module (reduced production lots). The number of tests and the costs per module will increase. With an increasing number of integrated components and connections the module will be more likely to fail and the efforts for repair will be higher. Drivers, sensors and protection facilities have to meet high demands for thermal and electromagnetic stability. Up to now, none of the following module configurations has gained acceptance as a world standard with respect to the integration of drivers. The actual state of this development is described in chapter 1.6. The universality of power modules is greatly impaired by increasing the integration of driver functions, the module increasingly becomes a sub-system. On the one hand, intelligent modules are aiming at real mass production markets (consumer, automotive), on the other hand markets are also involved, where many like applications can be supplied with innovative module systems consisting of similar basic elements. In spite of inevitable redundancies, the user may profit from reduced system costs due to the synergies achieved at the module manufacturer. Regarding the arrangement of IGBTs and diodes in the most commonly used power modules, the configurations shown in Figure 1.46 have mainly gained a position in the market, meeting the 67

67 1 Basics demands of most applications in power electronics and drive technology. Figure 1.46 is correspondingly applicable to modules with power MOSFETs, which are mainly applied in configurations for power supplies today. a) b) c) d) e) f) g) h) i) j) k) l) m) n) o) p) q) r) Figure 1.46 Important configurations of power modules with IGBTs and diodes 68

68 1 Basics a)...ga...: single switch, consisting of IGBT and hybrid inverse diode (as for MOSFET modules, here and in the other configurations, mostly just a parasitic inverse diode). In case of external bridge circuits, the inverse diodes are mutually acting as free-wheeling diodes. b)...gb...: dual module (halfbridge module) consisting of two IGBTs and hybrid diodes (freewheeling diodes) c)...gh...: H-bridge with two arms consisting of IGBTs and free-wheeling diodes d)...gah...: asymmetrical H-bridge with two diagonal IGBTs with hybrid inverse diodes (freewheeling diodes) and two free-wheeling diodes across the other diagonal. e)...gd...: 3-phase bridge (Sixpack, inverter) with three arms consisting of IGBTs and freewheeling diodes f)...gal...: chopper module with IGBT, inverse diode + free-wheeling diode on the collector side g)...gar...: chopper module with IGBT, inverse diode + free-wheeling diode on the emitter side h)...gdl...: 3-phase bridge GD with chopper GAL (brake chopper) i)...gt...: Tripack-module with three pairs of switches j)...gax... single switch with series diode on the collector side (reverse blocking switch) k)...gay... single switch with series diode on the emitter side (reverse blocking switch) l)...gbd... dual module with series diodes (reverse blocking switch) m)...b2u-diode rectifier and IGBT-H-bridge n)...b2u-diode rectifier and IGBT-inverter (three-phase-bridge) o)...b6u-diode rectifier and IGBT-chopper GAL (IGBT and free-wheeling diode on the collector side) p)...b6u-diode rectifier and IGBT-H-bridge q)...b6u-diode rectifier and IGBT-inverter (three-phase-bridge) r)...b6u-diode rectifier, IGBT-chopper GAL and IGBT-inverter (three-phase-bridge) The SEMIKRON code designation system for SEMITRANS-IGBT and MOSFET modules is referred to in chapter 1.4.4; for SKiiPPACK, MiniSKiiP and SEMITOP see chapter Heat dissipation capability In order to guarantee optimal utilization of the theoretical current capability, generated power losses have to be conducted safely and straightforwardly through the connection and isolation layers to the heatsink. Figure 1.47 shows the internal characteristics of a module which affect the capability to dissipate heat (internal thermal resistance R/ internal thermal impedance Z), which determines the maximum losses in the module (current, switching frequency, voltage,...) together with cooling and ambient conditions. The R-C elements shown in Figure 1.47, which are assigned to certain structural elements, are not meant to give an exact reflection of the physical heat conditions, but are only to illustrate the vertical flow of power and the temperature drop from the chip to the heatsink. The thermal resistances R th characterize the static state, therefore they may be assigned to the structural elements. However, capacitances replace physical elements, and may be gained by the transformation of real heat capacitances from volume elements (characterized by volume and specific heat) as opposed to a common thermal reference potential. 69

69 1 Basics P tot T j Silicon Chip Solder Chip-Cu R thsi Z thsi R thso1 Z thso1 1 2 Chip 1... Chip n Silicon Chip 220 µm Solder 80 µm Aluminium oxide - Isolation 380 µm Upper & lower copper layer 300 µm Upper Copper Layer Isolator (Al 2 O 3 or AlN) R thcu1 Z thcu1 R thiso Z thiso 3 4 Solder 80 µm Baseplate (Copper) 3 mm Thermal compound 50 µm Heatsink Lower Copper Layer R thcu2 Z thcu2 5 R thjh = R thsi + R thso1 + R thcu1 + R thiso + R thcu2 + R thso2 + R thba + R thtc Solder Copper- Baseplate R thso2 Z thso2 6 Z thjh = Z thsi + Z thso1 + Z thcu1 + Z thiso + Z thcu2 + Z thso2 + Z thba + Z thtc Baseplate Thermal Compound Heatsink & Heatsink- Ambient R thba Z thba R thtc Z thtc R thha Z thha T C R thjh, Z thjh R thjc1 Z thjc1 Chip 1... R thch1 Z thch1... Module R thjcn Z thjcn Baseplate R thchn Z thchn Chip n T C Silicon Solders DCB-Substrate Baseplate Thermal Compound T a R thha T h Heatsink / Air Z thha T a Figure 1.47a Basic structure of a power module with DCB illustrating the influences on heat dissipation 70

70 1 Basics P tot T j Silicon Chip R thsi Z thsi 1 Solder Chip-Cu Upper Copper Layer R thso1 Z thso1 R thcu1 Z thcu1 2 3 Chip 1... Chip n Silicon Chip 220 µm Solder 80 µm Aluminium oxide - Isolation 380 µm Upper & lower copper layer 300 µm Thermal compound 50 µm Isolator (Al 2 O 3 or AlN) R thiso Z thiso 4 Heatsink Lower Copper Layer R thcu2 Z thcu2 5 R thjh = R thsi + R thso1 + R thcu1 + R thiso + R thcu2 + R thtc Z thjh = Z thsi + Z thso1 + Z thcu1 + Z thiso + Z thcu2 + Z thtc Thermal Compound Heatsink & Heatsink- Ambient R thtc Z thtc R thha Z thha T a 8 9 T h R thjh1 Z thjh1 Chip 1 Module... R thjhn Z thjhn Baseplate Chip n T j Silicon Chip-solder DCB-Substrate Thermal Compound R thha Heatsink / Air Z thha T a Figure 1.47b Basic structure of a power module with DCB without base plate illustrating the influences on heat dissipation The quality of the dissipation of total power losses P tot generated in chips during forward onstate and blocking state and during switching can be expressed by a minimized temperature drop T jh = T j - T h from chip (chip temperature T j ) to heatsink (heatsink temperature T h ). It is quantified as thermal resistance R thjh (stationary) or thermal impedance Z thjh (transient). Figures 1.47 and 1.48 illustrate the internal influences of the module on R thjh and Z thjh : - chip (surface, thickness, geometry and position), - structure of the DCB-substrate (material, thickness, top side structure), - material and quality of connections between chip and substrate (solder, adhesive,..), - existence of a base plate (material, geometry), - backside soldering of the substrate to the base plate (material, quality), - assembly of the module (surface qualities/ thermal contact to the heatsink, thickness and quality of thermal paste or thermal foil). 71

71 1 Basics This list is still to be supplemented by the mutual heating of chips (thermal coupling) in complex power modules. For modules with base plate the external thermal resistance or impedance (base plate-heatsink) is indicated with R thch or Z thch, respectively, in contrast to the internal resistance R thjc or impedance Z thjc (chip-base plate): R thjh = R thjc + R thch Z thjh = Z thjc + Z thch This difference cannot be made for modules without base plate. Figure 1.48 indicates the R thjc -shares of the above-mentioned influences for the most common module structures of today described in chapter with Al 2 O 3 -direct-copper-bonding (DCB)- substrates and Cu-base plates as well as for modules with insulated metal substrates (IMS). 8% Cu 10% Solder Baseplate 20% Solder Cu Si 2% 3% 2% 11% Baseplate 6% Si Al 2 O 3 Polyimid 56% 82% Figure 1.48 Influences on the internal thermal resistance of a 1200 V-power module, chip surface 9 mm * 9 mm [194] a) For DCB-substrates (Al 2 O 3 ) on a Cu-base plate b) For IMS The main share of thermal resistance is allotted to internal module insulation (the alternative of external insulation with foils or something similar would result in a deterioration of insulation by an even further 20 %...50 %!). Compared to Al 2 O 3 with a purity of 96 % (heat conductivity λ = 24 W/m * K), which is applied as a standard in common DCB-modules, improvements can be made by using highly pure (99 %) Al 2 O 3 (λ = 28 W/m * K) or aluminum nitride (AlN, λ = 150 W/m * K). In modules with high isolation voltages (thicker isolation ceramics) especially, AlN, which is still very expensive, is preferred nowadays. Despite the high thermal conductivity of its material (Cu: λ = 393 W/m * K), the base plate also contributes to a considerable share of thermal module resistance due to its thickness ( mm). This share may be only partly reduced, since a reduction of the base plate thickness would also bear the consequences of reduced temperature spreading and, thus, reduction of the area through which the heat passes under the chips. In modules without base plate the lack of heat spreading in Cu is compensated by missing thermal resistances of base plate and rear-side soldering. Furthermore, on condition there is a suitable assembly technology (DCB is pressed on to the heatsink over wide areas), the chips will adhere closer to the substrate compared to constructions 72

72 1 Basics with base plate, since base plate and heatsink will never fully contact each other because of unavoidable unevenness generated during the soldering process and, since the base plate is only fixed to the heatsink by means of pressure screws positioned at the margins (Figure 1.49). Baseplate Module a) pressure pressure Baseplate Thermal Compound Heatsink Module pressure b) DCB-Substrate Thermal Compound (thin!) Heatsink DCB c) Figure 1.49 Problems arising through contact of power module to heatsink a) Module with base plate before mounting (base plate with convex bending) b) Module with base plate after mounting (strongly exaggerated!) c) DCB-module without base plate (e.g. SEMITOP, SKiiP, MiniSKiiP) Another factor that must not be neglected is the thermal resistance of the chip-substrate and (if applicable) substrate-base plate connections, which are produced as solder connections (e.g. λ = 75 W/m * K). The share of this resistance may be reduced by about 50 %, in cases where there is no base plate. The thermal resistance share of metal substrate areas (Cu: λ = 393 W/m * K) depends mainly on the structure of the top side copper surface, which is used as chip carrier and internal electrical connection system of the module. While the lateral heat flow in the lower copper layer is practically not impaired, spreading of heat is limited by the geometrical dimensions of the copper layers under the chips. It had been determined in reference [194] that R thjc of a chip of 6.5 mm * 6.5 mm on a Al 2 O 3 -DCB-ceramic substrate exceeds the value of a ten times as big copper area by about 15 %, provided the chip and copper areas are identical. The thermal resistance share of silicon chips increases proportionally to the thickness of the chips, which is determined by forward blocking voltage and chip technology. Moreover, the chip area determines the area through which the heat passes between chip and base plate or heatsink. On the one hand, the thermal resistance is reduced by increased chip areas due to a bigger area through which the heat passes. On the other hand, an increase of the area/ circumference ratio of 73

73 1 Basics the chip will increase the influence of the thermal coupling of the heat flowing inside the chips on the thermal resistance, heat spreading will be diminished. Both opposite tendencies will lead to dependency of the thermal resistance R thjc on the chip area A ch shown in Figure R thjc [K/W] ,1 IMS ; K=0.65 DCB (Al 2 O 3 ) ; K=0.76 DCB (AlN) ; K=0.96 0,01 A Ch [mm 2 ] Figure 1.50 Dependency of thermal resistance R thjc on chip area A ch [194] The dependency of R thjc on A ch is almost linear, when the total heat conductivity of the substrate (e.g. AlN-DCB) is high, since the chip area will hardly influence heat spreading. The worse the heat conductivity of the ceramics, the higher the non-linearity of the R thjc -dependency on A ch. Therefore, the maximum power loss density in the chips (chip utilization) will be drastically reduced by increasing the chip areas in like assemblies. This correlation is also valid for the influence of module mounting to the heatsink, which is done with thermal paste or thermal foils. With a value of λ = 0.8 W/m * K the heat conductivity of this layer is relatively low, which will cause a thermal transient resistance R thch between module base plate and heatsink. Besides the thickness d of the thermal paste layer, the R thch -share in the thermal resistance R thjh between chip and heatsink will also rise with increasing chip area. 74

74 1 Basics R thca [K/W] 0,3 0,25 0,2 0,15 0,1 0,05 d= 50µm 30µm 20µm 10µm 5µm A Ch [mm 2 ] Figure 1.51 Thermal resistance of thermal paste R thca of a DCB-substrate (Al 2 O 3 ) according to [279] and [194] First of all, Figure 1.51 shows the influence of an optimal mounting technology (thin thermal paste layer) on thermal parameters. Secondly, it shows that thermal limits are set to the use of bigger chips to increase power output; the thermal resistance share R thjh of thermal paste, for example, will amount to approximately 30 % at an application thickness of 30 µm for a 50A-IGBT-chip (9 mm * 9 mm). Currently, the maximum chip sizes used in power modules are between 30 mm 2 (IMS) and 150 mm 2 (Al 2 O 3 -DCB). Higher power output can be reached by decentralization of heat sources (paralleling of a maximum number of chips). For the sake of a small geometry of the modules, more or less intensive thermal coupling of chips has to be accepted, which is due to the tight arrangement of transistor and diode chips. According to the calculations in reference [194] an increase of the chip temperature caused by thermal coupling e.g. on a Al 2 O 3 -DCB-ceramic substrate should always be taken into consideration, if the distance a of the chips equals: a = 0.58 A Ch As already mentioned above, apart from the static behaviour of power modules the dynamic thermal behaviour, which is characterized by the thermal impedance Z th, is also of major importance. Figure 1.52 shows the characteristic of the thermal impedances Z thjc of a module with Al 2 O 3 - DCB-substrate for different chip areas versus time. 75

75 1 Basics Z thjc [K/W] 1 56 mm² 81 mm² 121 mm² 0,1 0,01 0,001 0,0001 1,00E-05 1,00E-04 1,00E-03 1,00E-02 1,00E-01 1,00E+00 1,00E+01 t [s] Figure 1.52 Thermal impedances Z thjc of a module with Al 2 O 3 -DCB-substrate for different chip areas versus time [194] For the given module structure the Z th -characteristics for different chip areas may be shifted against each other, i.e. the absolute values will change proportionally to the chip area, however, without influencing the time constants of the exponential functions. Accordingly, thermal impedances for different chip areas may be calculated similarly to the thermal resistances in a given structure by Z thjc1 (t)/z thjc2 (t) = R thjc1 /R thjc2 = (A Ch2 /A Ch1 ) K. Hereby, the exponent K, as a parameter indicating the influence of heat accumulation effect, may be determined from Figure 1.50 [194] Isolation voltage/ partial discharge stability [275] Advancing in the high-voltage application range will result in increasing demands on IGBTmodules for high isolation voltages and a high partial discharge stability. Isolation and partial discharge stability are dependent on the thickness, material and homogeneity of the insulation on the chip bottom and the case materials and, sometimes, on the chip arrangement too. The current transistor modules are subject to isolation test voltages between 2.5 kv eff and 9 kv eff, applied to every module during production. Figure 1.53 shows the maximum attainable isolation voltages for different isolation substrates and today s standard substrate thicknesses d. 76

76 1 Basics 13 kv Isolation voltage 6 kv 7 kv 7 kv d= [mm] Al 2 O 3 AlN Epoxyd Polyimid Figure 1.53 Isolation voltages for different isolation substrates with DCB, IMS and TFC Power cycling capability Power cycling at frequencies below approximately 3 khz, especially at duty cycle operation, such as prevails in traction, lift and pulse applications, will expose the internal connections in a module to temperature cycling, such connections being: - bonded joints, - underside soldering of chips, - solder connection of DCB and base plate, as well as substrate lamination (Cu on Al 2 O 3 or AlN). The different coefficients of the length expansion of the layers cause thermal stress during production and operation, which will finally lead to wear and tear of the material; module load life (number of possible switching cycles) will be shortened when the amplitude of the chip temperature fluctuation increases during these cycles. Test procedures are dealt with in chapter 2.7; the correlation of module life and temperature cycling amplitude will be explained in chapter Figure 1.54a explains the structural details relevant to the module life of an IGBT. Bond Bond IGBT 2 Bonding Wire Diode Bond Chip Solder Base Plate Solder Substrat Thermal Grease Base Plate (GP) Heatsink a) 77

77 1 Basics L/L Thermal Coefficient of Expansion Al 2 O 3 AlN Al Si Cu AlSiC [75Vol%SiC] b) 3 x 3 mm² 3 x 3 mm² System: standard 34mm module SKiiP pressure system 0,38mm-Al2O3 / Cu base plate 0,38mm-Al2O3 Results: T-Tkk L/L L T-Tkk L/L L [K] [1E-6/K] [µm] [K] [1E-6/K] [µm] silicon 69,7 4,1 0,86 62,6 4,1 0,77 substrate 55,4 8,3 1,38 48,3 7,8 1,13 base plate 40,5 17,5 2,13 2,13 0,00 silicon 1,38 1,23 0,86 0,89 substrate base plate 0,00 0,50 1,00 1,50 2,00 2,50 L [µm] 0,00 0,50 1,00 1,50 2,00 2,50 L [µm] c) 78

78 1 Basics 3 x 3 mm² 3 x 3 mm² System: standard 34mm module 34mm module SKiiP pressure system 0,63mm-AlN / Cu base plate 0,63mm-AlN / AlSiC base plate 0,63mm-AlN Results: T-Tkk L/L L T-Tkk L/L L T-Tkk L/L L [K] [1E-6/K] [µm] [K] [1E-6/K] [µm] [K] [1E-6/K] [µm] silicon 53,4 4,1 0,66 61,8 4,1 0,76 50,8 4,1 0,62 substrate 46,6 5,7 0,80 55,2 5,7 0,94 44,2 5,7 0,76 base plate 38,1 17,5 2,00 42,7 7 0,90 2,00 0,90 0,00 silicon 0,80 0,94 0,76 0,66 0,76 0,62 substrate base plate 0,00 0,50 1,00 1,50 2,00 L [µm] 0,00 0,50 1,00 1,50 2,00 L [µm] 0,00 0,50 1,00 1,50 2,00 L [µm] Figure 1.54 d) Thermal expansion in a power module a) Standard assembly of module with base plate b) Thermal coefficient of expansion c) Comparison: assembly with and without copper base plate; Al 2 O 3 substrate d) Comparison: assembly with and without copper/alsic base plate; AlN - substrate Figure 1.54 makes clear that the solder connection of the substrate to the copper base plate is most critical, since it is the most extensive connection - medium differences in the expansion coefficients of the adjacent materials provided. Therefore, high-quality solders and sophisticated soldering procedures have to be applied in order to avoid deformation and destruction of the substrate also in case of high temperature cycling amplitudes. Moreover, often the DCB-substrates are divided up to keep the absolute difference of the expansion coefficient as small as possible by reducing the solder areas. Other, lately developed module types are replacing copper by a material with a smaller expansion coefficient (such as AlSiC), see chapter and [206]. It is also shown in Figure 1.54 that modules with AlN-DCB are especially sensitive, because the expansion coefficient of AlN is very similar to that of the chip silicon, but there are greater deviations to copper than with Al 2 O 3. Therefore, today s modules with AlN-DCB and Cu-base plate cannot completely utilize the actual material performance with reference to the corresponding datasheets. It has become very obvious that one of the main causes for wear and tear can be eliminated by doing without a base plate and the necessary soldering, as long as the heat transfer from the substrate to the heatsink can be sufficiently ensured and the disadvantages of reduced heat spreading can be compensated. This has been realized with SKiiP, MiniSKiiP, SEMITOP and SKiM technologies (see chapter 1.5). 79

79 1 Basics The temperature cycling capability of the soldering of the chips to the substrate can be improved by - use of AlN-substrates with less deviation of the expansion coefficient to Si than Al 2 O 3, - substitution of soldering by low-temperature connections; the connection between chips and substrate is realized by sintering silver powder at comparably low temperatures ( C), which will minimize thermal stress among the materials during production. Bond connections. Also the lifetime of the connection between bond wire and chip is influenced decicively by the difference in thermal coefficients of expansion. Silicon shows a relative slight lenght expansion (4.7 ppm/k) during power cycling. However, the Al-metallization of the emitter and gate contacts which are stressed by the same temperature fluctuations shows a considerable higher relative lenght expansion (23 ppm/k). The stress inside of the metallization caused by this difference in expansion effects a rearrangement of the crystal grains. This process is called reconstruction. The reconstruction - mostly identifiable by an optical dispersive surface leads to the destruction of the bond wire connection [304]. Reconstruction of Al-contact metallization can be reduced by a polyimide-cover. The lifetime of the bond connection on the chip contact area is increased considerably using bond covers. However, another type of failure occurs. The mechanical deflection of the bond wire during thermal alternating stress caused by the different thermal expansion of substrate and Al-wire leads to a fracture of the bond wire nearby the bond-heel on the PCB-sided juncture since the chip-sided bond-heel is mechanical strengthened by the polyimide cover. Bond wire failures are mostly observed in lifetime tests whereas the failure is caused really by ageing of the solder layer. Caused by growing cracks in solder layer the thermal resistance increases and effects a increasing chip temperature and thus a higher stress for both the bond connection and chip solder layer. Finally, this positive feedback leads to a failure. In any case, the ageing of solder connection has to be investigated at failure analysis. Using today s technologies solder connections and bond connections have nearly the same lifetime at cycles with high temperature ripples ( T 100K). In state-of-the-art power cycling test equipment forward voltage drop and thermal resistance of power devices are measured and recorded. So, both degeneration of solder layer and bond connection failures (steps in foward voltage drop characteristic) can be observed. Bond connections in IGBT and diode-disc cells have been replaced by pressure contacts with a higher temperature cycling capability due to pressure contact technology. Processes for transferring this direct pressure contact technology to power modules are also currently being developed Internal low-inductive structure With the example of a halfbridge module, Figure 1.55 shows the most important internal parasitic inductances of a module, resulting from the necessary connections among the chips and to the module terminals (bond wires, internal connections). 80

80 1 Basics Lσ C TOP Lσ G Lσ EC BOTTOM Lσ G Lσ E L CE = Lσ C + Lσ EC + Lσ E Figure 1.55 Parasitic inductances in a dual IGBT-module L σg : parasitic gate inductances L σc : parasitic TOP-collector inductance L σec : parasitic inductance between TOP-emitter and BOTTOM-collector L σe : parasitic BOTTOM-emitter inductance L CE : total parasitic TOP-collector-BOTTOM-emitter inductance Minimization of these inductances, which induce overvoltages during turn-off and cause a di/dt reduction during turn-on as well as inductive coupling of control and power circuit, will directly affect the performance of power modules. Moreover, parasitic inductances in modules with internally paralleled chips may cause unequal dynamic performance of the chips and oscillations between the chips. Chapter gives details on these correlations Internal structure-adapted to EMC The short rates of rise of current and voltage within the ns-range realizable with MOSFET- and IGBT-modules generate electromagnetic interference with frequencies far beyond the MHzrange. Therefore, the parasitic elements typical of the internal and out-leading paths of propagation in the module exert considerable influence on the interference voltages generated. Suitable isolation materials, small coupling areas or conductive shields can reduce, for example, asymmetrical interferences [193]. In addition to that, the internal connections in the module have to be of such a structure, that excludes failures caused by outer stray fields or transformatory couplings into control lines. Another aspect of electromagnetic compatibility is the earth current, i.e. the current i E = C E * dv CE /dt that flows due to the capacitance C E of the isolation substrate caused by the dv CE /dt generated in the IGBTs during switching via the earthed heatsink to the earth connector. 81

81 1 Basics This earth current is identified as earth-leakage current by line monitors; its permissible maximum value is to be limited to % (1 % anticipated) of the nominal output current as soon as the new EN comes into effect. Accordingly, the permissible switching speed will increase proportionally to the decrease of capacitance of the isolation substrate. Figure 1.56 compares the capacitances of the most commonly used substrates with respect to their standard thicknesses. The deviating dielectric constants and the standard thicknesses depending on thermal conductivity (thickest substrate material is AlN with 630 µm, thinnest substrate is required in IMS-structures with 120 µm for epoxy isolation and 25 µm for polyimide isolation) result in respectively differing capacitances C E and, thus, in different limits of the maximum switching velocity dv CE /dt for the maximum tolerable earth current i E Capacity per unit area d=0.12 mm d=0.38 mm d=0.63 mm d=0.025 mm Al 2 O 3 AlN Epoxy Polyimid Figure 1.56 Capacitance per unit area for different isolation substrates Defined safe behaviour in case of module failure In the case of module failure (probably caused by use of wrong driver) the total energy stored in the DC-link capacitors will be transferred, for example, in a voltage-supplied circuit within the module case. After melting the bond wires this energy is mainly stored in the generated plasma, which allows the module to explode. In conventional transistor modules this may cause circuit interruption, short-circuit of the main terminals or even bridging of the isolation; plasma and particles of the case might be spread over the module surroundings with high kinetic energy. With the proper case construction, the dangers involved may be limited and the particles spread are guided in a defined direction. The latest developments in this field guarantee, for example, that up to a defined energy level of e.g. 15 kj no particles will leave the module; even at 20 kj the case might break, but no solid metal particles would be hurled out [196] Non-polluting recycling Today s power modules usually exclude toxic materials (e.g. BeO) and the number of materials used is kept as low as possible. Case and other materials are flame-resistant and must not release toxic gas during burn-out (ULspecification). 82

82 1 Basics The module has to be split up as simply as possible in metal and non-metal components during recycling. Therefore, the currently available modules are cast solely with elastomeric materials (soft moulding) Assembly and connection technology: types of cases Cases of current power modules containing MOSFET or IGBT-switches are mostly equipped with screw, plug-in or solder-terminals. For the majority of transistor modules, different manufacturers are striving for a large degree of compatibility with partly historically developed structures (Figure 1.57). First of all, the inevitably deviating high-integration modules (e.g. SKiiPPACK, MiniSKiiP) are not to be considered in the following. GB GAL GAR GD GDL GA GB GAL GAR Sixpack: GD GDL Figure 1.57a Transistor modules with base plate SEMITOP 83

83 1 Basics SKiM 3 SKiM 4 SKiM 5 Figure 1.57b Transistor modules without base plate The highest degree of standardization is assigned to module types with screw connectors. The main supplies may be contacted by busbars or sandwich assemblies. Often, additional outputs are provided for control and sense-units (e.g. control-emitter, sense-collector) in order to minimize the influence of inductive voltage drop in the main circuit generated during switching, especially at the bonded connecting wires. Auxiliary supplies are mostly designed as 2.8 mm flat strip plug connectors, sometimes also as screw connectors. For low-current modules the use of 6.3 mm or 2.8 mm flat strip plug connectors for power and control circuit, respectively, has also been very common up to now. Solderable modules for PCB-assembly (e.g. SEMITOP, ECONOPACK) are gaining importance, because they offer cost advantages during automatic production and tooling procedures. Optimized layout of connectors will take care of low-inductance assemblies, and currents up to 100 A may be realized by paralleling several solder connectors. In this respect, the necessary track sections (for high currents) and the realization of long creepage paths on the PCB might be problematic. 84

84 1 Basics SEMIKRON code designation system for SEMITRANS- and SEMITOP-power modules Different functions, internal circuits, current and voltage range and other informations are coded by the manufacturers in their type designations. The following tables indicate the code designation system for SEMIKRON MOSFET and IGBTmodules. SEMITRANS power-mosfet-modules There is an old and a new designation code for SEMITRANS-MOSFET-modules. The old designation code had been introduced with the first MOSFET-modules, some of which are still being produced, at the end of the eighties following the PRO-ELECTRON-recommendations by SEMIKRON. All newly developed modules are designated according to the new code, which gives more information and corresponds basically to the designation code for SEMITRANS- IGBT-modules. old designation code, e.g. new designation code, e.g. SK M A F R C SK M 120 B 020 SEMIKRON component MOS technology SEMIKRON component MOS technology Circuit configuration Drain current grade 1: Single switch (I D /A at T case = 25 C) 2: Dual mode (halfbridge) 3: Special type Circuit configuration 4: 4-pack (H-bridge) A: Single switch 6: 6-pack (three-phase-bridge) B: Dual mode (halfbridge) D: 6-pack (three-phase-bridge) Voltage grade M: 2 MOSFETs in center tap connection 0: V DS = 50 V 5: V DS = 500 V 1: V DS = 100 V 8: V DS = 800 V Drain-source voltage grade 2: V DS = 200 V 9: V DS = 1000 V (V DS /V/10) 4: V DS = 400 V Internal arrangement 0: chips in parallel 3: Special type 1: 6 chips in parallel 4: 4+4 chips 2: 2 chips in parallel A: avalanche-proof single chips F: built-in fast inverse diode R: built-in gate series resistors C: built-in gate driver circuit (manufactured until 1996) 85

85 1 Basics SEMITRANS IGBT-modules z.b. SK M 100 G B 12 3 D L SEMIKRON component M: MOS technology D: 7D-pack (B6-diode input bridge with IGBT chopper) Collector current grade (I C /A at T case = 25 C) G: IGBT switch Circuit configuration A: Single switch AL: Chopper module (IGBT and free-wheeling diode on collector side) AR: Chopper module (IGBT and free-wheeling diode on emitter side)) AH: Asymmetric H-bridge AX: Single IGBT + series diode on collector side (reverse blocking) AY: Single IGBT + series diode on emitter side (reverse blocking) B: Dual module (halfbridge) BD: Dual module (halfbridge) + 2 diodes in series (reverse blocking) D: 6-pack (three-phase-bridge) DL: 7-pack (three-phase-bridge + AL-chopper) H: Full single phase H-bridge M: 2 IGBTs in collector connection Collector-emitter voltage grade (V CE /V/100) IGBT-series no. 0: first generation (collector current grade specified at T case = 80 C) 1, 2: first generation (collector current grade specified at T case = 25 C) (600V-types: PT-IGBTs, collector current grade specified at T case = 80 C) 3: second generation (high density-npt-igbts for 600 V and 1200 V), first generation NPT-IGBT-chips for 1700 V, CAL-diodes; 600 V-types: collector current grade specified at T case = 80 C, 1200 V-/1700 V-types: collector current grade specified at T case = 25 C; low inductance case 4: high density, lowv CEsat -NPT-IGBT-chips (1200 V, 1700 V) 5: high density, high speed-npt-igbt-chips (600 V, 1200 V) 6: Trench-NPT-IGBT-Chips Features D: fast inverse diode K: SEMITRANS 5-case with screw connectors L: 6-pack-case with solder pins S: Collector-Sense-Terminal I: enlarged inverse diode (higher power capability) SKiiP converter in an automobile with hybrid drive 86

86 1 Basics SEMITOP power modules The SEMIKRON SEMITOP module range comprises solderable power modules with thyristors, diodes, power MOSFETs and IGBTs; in the following only SEMITOPs with MOSFETs and IGBTs are considered, e.g. SK 100 G B 12 3 x SEMIKRON component Current rating in A at T h = 25 C G: IGBT-switch M: MOSFET-switch Circuit A: Single switch AL: Chopper module (IGBT/MOSFET + free-wheeling diode at collector side) AR: Chopper module (IGBT/MOSFET + free-wheeling diode at emitter side) AH: Asymmetric H-bridge B: Dual module (halfbridge) D: 6-pack (three-phase-bridge) H: Full single phase H-bridge Voltage grade (V CE /V/100 or V DS /V/100) IGBT-series 2: PT-IGBT-chips (only for 600 V) 3: high density-npt-igbt-chips 4: high density, low V CEsat -NPT-IGBT-chips 5: high density, high speed-npt-igbt-chips Features (not yet defined for SEMITOPs with IGBT and MOSFET-chips) The fast inverse diode(s) integrated in every IGBT-SEMITOP are not indicated in the designation code. 1.5 Examples for new packaging technologies New packaging technologies are being developed mainly with regard to: - improvement of heat dissipation and temperature cycling capability, - minimized inductances in the module and in the supply leads by means of suitable module construction, - highly flexible assembly and connection technology, easy mounting at the user s facilities, - higher complexity of integration (converter circuits), - integration of monitoring, protection and driver functions, - delivery of tested electric or thermal-electrical systems. The following four ranges of power modules, which have been developed with consideration to the requirements mentioned above, are therefore regarded as exemplary. 87

87 1 Basics SKiiPPACK Figure 1.58 shows the scheme of a SKiiPPACK (Semikron integrated intelligent Power Pack). pressure plate elastic material main terminal DCB substrate with chips housing frame pressure screw PC board with auxiliaryconnectors plastic pressure spread spring integrated in pressure spread as auxiliaryconnector thermal conductive layer heatsink Figure 1.58 Basic SKiiPPACK structure In contrast to conventional transistor modules, the DCB-substrates carrying the IGBT and diode chips are not soldered on to a copper base plate, but are pressed almost with the complete surface directly to the heatsink by means of a plastic pressure spread. The electrical connection of the DCB to the SKiiPPACK terminals, designed for connection of laminated, low-inductance busbars, is made by pressure contacts and low-inductive track layout. A metal plate serves as pressure element and as thermal and EMI-shield for the driver circuit, which is also integrated into the SKiiP case. By paralleling many, relatively small IGBT-chips and with their optimal contact to the heatsink, the thermal resistance may be reduced considerably compared to standard modules, since the heat is spread evenly over the heatsink. Three sizes of cases (2, 3 and 4 arms in GB, GAL or GAR-configuration) and different chip arrangements as well as adapted driver components connected by simple external constructions guarantee the realization of dual modules, H-bridges, SIXPACKS and SEVENPACKs in 600 V-, 1200 V- and 1700 V-technology V-SKiiPPACKs are under development. In Figure 1.59 the special flexibility of the SKiiPPACK principle is explained with an example. 88

88 1 Basics a) b) c) Figure 1.59 Possible applications of a SKiiPPACK with 3 identical DCBs (example) a) View of a SKiiPPACK on an aluminium heatsink b) SIXPACK c) Dual module (halfbridge) Besides transistor and diode chips, PTC-temperature sensors are integrated into the DCB; their output signal directly affects driver operation (temperature limit) and - due to analogous amplification in the driver - it can also be used for evaluation of the heatsink temperature. The AC-connectors of the SKiiPPACK accommodate current sensors for overcurrent and shortcircuit protection of the IGBTs. Signal processing and linkage is done by the internal driver, which is positioned on the pressure plate; this will be described in detail in chapters 1.6 and The potential-free current signals may also be used as actual values for external sensors and control circuits. Advantages offered by SKiiPPACKs in comparison to conventional modules are: - improved temperature cycling capability, - reduced thermal resistance by direct heat transfer chip-dcb-heatsink, - possibility of producing very compact constructions with high power density, - low switching overvoltages due to thorough low-inductive structure, i.e. high permissible DC-link voltage and reduction of interference generation, - repairable and recyclable by excluding hard moulding and internal soldering, - optimal adjustment of internal, intelligent driver, - load test of complete systems carried out at manufacturer. 89

89 1 Basics Figure 1.60 shows SKiiPPACK cases and some of standard internal circuits. Further circuits are available and may be integrated if required by the customer, respectively (e.g. brake chopper, asymmetrical bridges). Besides the heatsink shown below, other air or water-cooled heatsinks may also be used for mounting of the SKiiPPACKs. view from right Case S2 Case S3 Case S4/S5* * * (with standard heatsink for air-cooling) * case S5 has an additional DIN-Connector on the right quarter of top (for brake-chopper-input) ** F-Option: fibre optic connectors for driver input and fault detector output Figure 1.60 SKiiPPACK cases and standard internal circuits MiniSKiiP Another new development for the low-power range, which is outstanding for its special flexibility and easy mounting is SEMIKRON s MiniSKiiP with pressure contacts, the basic structure of which is shown in Figure

90 1 Basics Printed Circuit Board (PCB) Pressure Screw Pressure Lid Case Contact Spring Bond Wire Chip Isolation Substrate Heatsink Figure 1.61 Basic structure of a MiniSKiiP Basic elements of a MiniSKiiP are: - DCB isolation substrate with soldered, wire-bonded semiconductor chips (e.g. IGBTs, MOSFETs, diodes, thyristors) as well as other components, such as current and temperature sensors, resistors and capacitors, - silicone filled case with integrated contact springs and glued in DCB and - hard plastic cover. One or two screws take care of all electrical and thermal connections (to the heatsink) making a detachable connection between SKiiP cover, PCB, MiniSKiiP and heatsink. The contact springs have several functions: they serve as the electrical connection between the power semiconductors on the DCB and the other circuits on the PCB, and also as pressure spring pad between DCB and heatsink in the mounted state. The high number of springs spread over the total MiniSKiiP area provides for even pressure between components and heatsink, which guarantees a low thermal resistance. For the current range above 10 A, the contacts are connected in parallel. The multitude of spring shafts results in a high degree of flexibility concerning the production of many different circuits for drives and power supplies as well as other applications. Several types of cases designed for different power ranges are available from MiniSKiiP 1 (line voltage up to 230 V, rated current up to 12 A) to MiniSKiiP 8 (line voltage up to 400 V, rated current up to 125 A) (Figure 1.62). 91

91 1 Basics MiniSKiiP Case M 1 MiniSKiiP Case M 2 MiniSKiiP Case M 3 MiniSKiiP Case M 8a; Case M 8 M 8a M 8 Figure 1.62 Standard MiniSKiiP types and circuits 92

92 1 Basics In the biggest MiniSKiiP (MiniSKiiP 8) curved, pressure contact springs are used because of the high currents applied; these can be supported by compensating current sensors on the AC-side. (Figure 1.63). Figure 1.63 MiniSKiiP 8 curved springs with current sensors In order to avoid too high a concentration of heat sources, the standard circuit is divided up over two cases, one of them containing the uncontrolled or half-controlled bridge rectifier and the brake chopper, the other containing the three-phase-converter SEMITOP The product range of SEMITOP, which has already been mentioned, comprises 3 types of cases (see Figure 1.57). Just like SKiiPPACK and MiniSKiiP, SEMITOP is also assigned to those constructions without base plate that generate widespread pressure of the DCB to the heatsink by a special construction of the plastic housing. One or two screws make a closed linkage between module and heatsink. In contrast to MiniSKiiP the contacts to the PCB are made by two lines of solder pins. Due to the ability of such a small module to integrate up to 12 power components, SEMITOP is used preferably in low-size applications. The unrestricted useability of the space between the solder pins for other printed circuit board components is advantageous in comparison to MiniSKiiP, which is very similar in its technology New low-inductive IGBT module constructions for high currents and voltages A very interesting and promising development in high-power electronics (e.g. 1.2 ka and 2.5/3.3 kv) is the low-inductive FLIP-module (ABB Semiconductors, [6]) and the SKiM20- module (without base plate) by SEMIKRON (Figure 1.64). These modules had been designed especially for high-power range. Therefore, the development goals had been mainly high reliability (high power and temperature cycling capability), good heat dissipation behaviour (decentralized heat sources / low thermal resistances), minimized inductances in the module and module busbarring as well as safe failure behaviour (explosion protection by means of defined areas for pressure balancing). Figure 1.64 shows the basic assembly of a SKiM20-module as the most modern version of such module constructions. 93

93 1 Basics Figure 1.64 Construction of an IGBT-module SKiM20 As the other SKiM-models shown in Figure 1.57 the SKiM20 has no base plate. From this the advantageous basic features discussed in chapter (Figure 1.54) result. The semiconductor chips are arranged on three small areas of AlN ceramic substrates. One ceramic substrate combined with a case element and a pressure spread element made from plastic as well as a pressure plate forms a sub-module. The pressure spread element presses the substrate almost over its full area to the heatsink. The main terminals of each sub-module are soldered to the substrate. The control and auxiliary terminals are made as pressure contacts. The case cover also acts as pressure element. 1.6 Integration of sensors, protective functions, drivers and intelligence In the following, some examples for the integration of peripheral functions in power modules are described, sorted by increasing degrees of integration. Sense IGBT-Module Sense IGBT-modules contain sense-igbts as described in chapter Compared to solutions with shunts in the emitter circuit, a much higher measuring resistance may be chosen. Other than with overcurrent protection by V CE -monitoring, either shorter deadtimes are required or none at all. 94

94 1 Basics Modules with integrated temperature sensor As an alternative to the TEMPFET (see chapter 1.2.4) as a solution for discrete power semiconductors, simple PTC-temperature sensors in SMD-design are being used in modules more and more, with a higher degree of integration; they are soldered on to the DCB-substrate near the chips. The heatsink temperature is indicated at a defined point by the sensors. Ideally, the transversal heat flow between this point and the heatsink areas under the hottest chips may be neglected. A suitable evaluation board takes care of overtemperature protection by active control on the driver or processing the analogous signal. Rugged Modules [281] Besides the IGBT hybrid protective circuit are integrated into the case for protection of the IGBT in case of failure. The terminal behaviour are determined by the driver just as with conventional IGBTs; the protective circuits are activated only in case of failure and will limit the short-circuit current. IPM (Intelligent Power Modules) [280] IPM modules are able to integrate, in addition to the IGBTs and free-wheeling diodes, drivers and protective units (IPM minimal configuration) as well as complete inverter control units. The user, himself, can no longer control switching and on-state characteristics, therefore IPMs are often designed specifically for the application (ASIPM = Appl. Specif. IPM). SKiiPPACKs (Semikron integrated intelligent Power Packs) As already described in chapter 1.5.1, SKiiPPACKs contain a driver unit, laid out as an SMD- PCB, which integrates all the necessary protective and monitoring functions and which is positioned over the pressure plate. (see Figure 1.58). SKiiPPACKs may be driven and supplied on potential of the superordinated control system (CMOS or TTL level). The SKiiPPACK driver integrates all necessary potential separation, a SMPS and the power drivers. SKiiPPACKs are equipped with current sensors in the AC-outputs and temperature sensors as well as an optional DC-link voltage sensor. The driver valuates the signals transmitted by the sensors in order to care for overcurrent/ short-circuit, overtemperature and overvoltage protection as well as supply-undervoltage protection. An error signal and standardized analogous voltage signals of the actual AC-output current value, the actual heatsink temperature and, optionally, the DC-link voltage are available on separate potentials at the driver connector for evaluation in the superordinate control circuit. Figure 1.65 describes the OCP (Over Current Protection) driver principle, which will be detailed in chapter

95 1 Basics Figure 1.65 OCP-driver principle [264], [265] 96

96 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules 2.1 General Letter symbols, terms, standards Letter symbols and terms [264], [265] Voltages: firstly, two index letters are used to indicate the terminals between which the applied voltage is taken. If the potential of the terminal designated with the first index letter is positive versus the terminal designated with the second index letter (reference potential), the applied voltage is positive, e.g. V CE. As for diodes, F is used for the forward on-state voltage (positive anode potential versus cathode potential) and R for the reverse blocking voltage (positive cathode potential versus anode potential). As for transistors, an additional third index letter may indicate the type of circuit between terminal 2 and a non-designated third terminal, e.g. V CGR, where the third letter symbol is defined as follows: S: short-circuit between terminal 2 and 3, R: resistor to be specified between terminal 2 and 3, V: external voltage between terminal 2 and 3, to be specified, X: resistor and external voltage between terminal 2 and 3, to be specified. Index letters can be followed or preceded by other index abbreviations for further specification of parameters, either with or without brackets and either as capital or small letters (e.g. V (BR)DS or V GE(th) or V CEsat ), for example: (BR): breakdown voltage, sat: saturation voltage, (th): threshold voltage, clamp: clamping voltage limited by external circuits. Supply voltages are often marked by doubleindex letters, e.g. V GG (supply voltage of gateemitter circuit), V CC, V DD. Currents: at least one index letter is used to specify a current. Positive values specify positive currents, which enter the component at the terminal and are named first in the index, e.g. I GE. If there is no danger of mix-up, only the first index letter is usually used, e.g. I C (collector current), I D, I G. The same applies when indicating negative currents. As for diodes, F is used for indicating forward on-state currents (anode-cathode) and R for reverse currents (cathode-anode). As for transistors, an additional third index letter may indicate the type of circuit between terminal 2 and a non-designated third terminal, e.g. I GES, where the third letter symbol is defined as follows: S: short-circuit between terminal 2 and 3, R: resistor to be specified between terminal 2 and 3, V: external voltage between terminal 2 and 3, to be specified, X: resistor and external voltage between terminal 2 and 3, to be specified. 97

97 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Index letters can be followed or preceded by other index abbreviations, either with or without brackets and either as capital or small letters, for example: AV : average value, RMS: effective value, (root mean square) M: peak value (maximum), R: periodic (repetitive), S: non-periodic (spike), puls: pulsed (direct current). Other symbols: the terminology used for other symbol indications for electrical, thermal and mechanical parameters mainly follows the terminology for voltages and currents; for further explanation please see the following table. Index letters may also specify turn-on (on) and turnoff (off) switching states (mostly in brackets). Standards for terms and definitions Details with regard to definitions, determination of terms, datasheet parameters and measurement procedures may be taken, for example, from the following standards: Standards, terms and definitions DIN T5 Semiconductors, switching symbols DIN Diodes: terms and definitions DIN T3 Power semiconductors: symbols DIN Field effect transistors: terms and definitions IEC Mechanical standards (cases) IEC 50 (521) 1984, (551) 1982 International dictionary for electrical engineering IEC Graphic symbols, switching symbols for diagrams IEC 971 ( ) Semiconductor converters: designation system Datasheet parameters and measurement procedures DIN T1 Principle designations for datasheets DIN T2 Test procedures: diodes T3 IEC 747-1: 1983 IEC 747-2: 1983, A1(1992), A2(1993) IEC 747-8: 1984, A1(1991), A2(1993) IEC : 1998 FDIS Test procedures: heat resistance Semiconductor components/ Volume 1: General hints with reference to maximum ratings and characteristics, test procedures Rectifier diodes Field effect transistors IGBTs (in preparation) R & D standards and reliability IEC 664-1: 1992 Co-ordination for the isolation of electrical appliances < 1 kveff Volume 1: principles, test procedures IEC : 1991/EN : 1993 Semiconductor converters: basic requirements DIN EN50178 (VDE0160): 4/1998 Electronic devices for power systems: general isolation test procedures IEC /EN :1997 Designation system for low-voltage appliances, volume 4. UL 1557: 5/1993 Inflammability, isolation safety 98

98 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules UL 94-V0: 9/1981 Inflammability of plastic materials IEC 747-1, IX: 1983 Components at risk of ESD (Electrostatic Discharge) DIN IEC Reliability tests ISO 9001/EN29001: 1995 Quality system certification DIN EN ISO 9001: 8/1994 Re-qualification of quality system Maximum ratings and characteristics Maximum ratings Maximum ratings for modules indicated in the datasheets are extreme values of electrical, thermal and mechanical load permissible without risk of destruction or damage. Every limit value has been specified according to exactly defined conditions, which have inevitably to be indicated in the datasheets, since some of these conditions have not (yet) been standardized. Exceeding one of the maximum ratings may lead to destruction of the component, even if other maximum ratings have not been strained to their utmost limit. In addition to the static maximum ratings listed in the following there are so-called dynamic maximum ratings, which designate the permissible course of the characteristics (current/ voltage) during switching. If not otherwise shown, the maximum ratings in the datasheets are valid at a chip or case temperature of 25 C, for higher temperatures deratings usually have to be considered. Characteristics Characteristics describe the features of components determined under certain specified measuring conditions (mostly application-specific). Just as with maximum ratings, all characteristics are subject to exactly specified ambient conditions which have to be indicated in the datasheets, since some of those conditions are also not standardized. Characteristics are often indicated as typical values within a range. The reference temperatures for chip or case are normally indicated with e.g. 25 C or 125 C so temperature dependency has to be considered in the case of differing temperatures. Limits and characteristics are published in the form of tables and diagrams. 2.2 Power MOSFET modules [264], [265] Maximum ratings MOSFETs/module structure Drain-source voltage V DS Maximum voltage between drain and source contacts of MOSFET chips for open or closed gatesource circuit. Parameter: case temperature T case = 25 C 99

99 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Drain-gate voltage V DGR Maximum voltage between drain and gate, Parameters: external resistance R GS between gate and source, case temperature T case = 25 C Continuous direct drain current I D Maximum direct current at drain output Parameters: case temperature, e.g. T case = 25 C, 80 C: I C, I C Peak value of a periodic drain current I DM or pulsed drain current I Dpuls Peak value of current at drain output during pulse operation, Parameters: pulse duration t p, case temperature, e.g. T case = 25 C, 80 C and pulse/break ratio (diagram maximum safe operating area ) Single pulse avalanche energy dissipation E AS Maximum avalanche energy dissipation from drain to source of a single chip during turn-off of an unclamped inductive load (single pulse load), Parameters: instantaneous drain current i D, drain-source supply voltage V DD, external gate-source resistance R GS, external drain inductance L, chip temperature, e.g. T j = 25 C Gate-source voltage V GSS or V GS Maximum voltage between gate and source Parameter: case temperature T case = 25 C Total power dissipation P tot or P D Maximum power dissipation per transistor/diode or within the whole power module P tot = (T jmax -T case )/R thjc, Parameter: case temperature T case = 25 C Operating temperature range T vj or T j ; T j(min)...t j(max) Permissible chip temperature range within which the module may be permanently operated Storage temperature range T stg ; T stg(min)...t stg(max) ) Temperature range within which the module may be stored or transported without being subject to electrical load. Isolation test voltage V isol or V is Effective value of the permissible test voltage between input terminals/ control terminals (shortcircuited, all terminals connected to each other) and module base plate. Parameters: test duration (1 min, 1 s), rate of rise of test voltage, if required; according to IEC (1991), EN (1993), section (corresponds to VDE 0558, volume 1-1: ) and DIN VDE 0160 ( ), section 7.6 (corresponds to EN (1994)/ E VDE 0160 ( ) the test voltage shall only rise gradually up to its maximum rating. Grade of humidity describes the permissible ambient conditions (atmospheric humidity) according to DIN Grade of climate describes the permissible ambient test conditions (climate) according to DIN IEC

100 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Inverse diodes/ free-wheeling diodes Forward current I F Maximum forward current value of inverse or free-wheeling diodes, Parameter: case temperature, e.g. T case = 25 C, 80 C Peak forward current I FM or pulsed forward current I Fpuls Peak value of diode current during pulse operation Parameters: pulse duration t p, case temperature, e.g. T case = 25 C, 80 C Characteristics MOSFETs/ module structure Drain-source breakdown voltagev (BR)DSS Breakdown voltage between drain and source, gate-source short-circuited (V GS = 0) Parameters: Reverse drain current I D, case temperature T case = 25 C Gate-source threshold voltage V GS(th) Gate-source voltage above which considerable drain current will flow, Parameters: drain-source voltage V DS = V GS, drain current I D, case temperature T case = 25 C Zero gate voltage drain current I DSS Blocking current between drain and source with gate-source short-circuited (V GS = 0) and drainsource voltage V DS = V DSS, Parameter: chip temperature, e.g. T j = 25 C and 125 C Gate-source leakage current I GSS Leakage current between gate and source with drain-source short-circuited (V DS = 0) at maximum gate-source voltage V GS, Parameters: gate-source voltage V GS, case temperature T case = 25 C Drain-source on-resistance R DS(on) Quotient of changing drain-source voltagev DS and drain current I D in a thoroughly gatecontrolled MOSFET at a specified gate-source voltage V GS and a specified drain current I D (at rated current ), In this state V DS is proportional to I D, during large-signal behaviour the forward on-state voltage V DS(on) = R DS(on) * I D. Parameters: gate-source voltage V GS, drain current I D ( rated current ), case temperature T case = 25 C (R DS(on) is extremely dependent on temperature!). Forward transconductance g fs Quotient of changing drain current and gate-source voltage at a specified drain current I D (at rated current ), Parameters: drain-source voltage V DS, drain current I D ( rated current ), case temperature T case = 25 C Capacitance chip-case C CHC Capacitance between a sub-component and the case base plate or the heatsink potential, Parameter: case temperature T case = 25 C 101

101 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Input capacitance C iss Capacitance between gate and source with drain-source short-circuited for AC and gate-source voltage V GS = 0. Parameters: drain-source voltage V DS, measuring frequency f, case temperature T case = 25 C Output capacitance C oss Capacitance between drain and source with gate-source short-circuited (V GS = 0), Parameters: drain-source voltage V DS, measuring frequency f, case temperature T case = 25 C Reverse transfer capacitance (Miller capacitance) C rss, C mi Capacitance between drain and gate with drain-source short-circuited at AC and gate-source voltage V GS = 0. For measuring, the source has to be connected with the protective shield of the measuring bridge. Parameters: drain-source voltage V DS, measuring frequency f, case temperature T case = 25 C Parasitic drain-source inductance L DS Inductance between drain and source Switching times Switching times indicated in MOSFET datasheets are determined from a measuring circuit under ohmic load according to Figure 2.1a. They refer to the gate-source characteristics during turn-on and turn-off, see Figure 2.1b. Switching times as well as real current and voltage characteristics are determined by internal capacitances, inductances and resistances and by those of the gate and drain circuit; for this reason, all indications in the datasheets and the characteristics depicted therein may serve only as a guide. As the current and voltage characteristics are not relevant to most applications, because they are based on the application of pure ohmic load, their importance is actually restricted to the definition of switching times. The waveforms will deviate significantly especially if inductive or capacitive loads are involved (chapter 1.2.3) and also the measurement results may differ. 102

102 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules a) b) Figure 2.1 a) Measuring circuit b) Definition of MOSFET switching times under ohmic load The following parameters are indicated relevant to switching times: measuring circuit, drain-source supply voltage V DD, gate-source control voltage V GS, drain current I D, gate series resistance R G (internal resistance of the control circuit), sometimes gatesource resistance R GS, case temperature T case = 25 C. Turn-on delay time t d(on) After sudden turn-on of a positive gate-source control voltage V GG, the gate-source voltage V GS starts to rise with a time constant determined by input capacitance and gate resistance. As soon as the threshold voltage V GS(th) has been reached, the drain-source voltage V DS will start to decrease and the drain current I D will begin to rise. The turn-on delay time t d(on) is defined as the time interval between the moment when the gateemitter voltage V GE has reached 10 % of its end value (V GG ), and when the drain-source voltage has dropped to 90 % of its initial value (V DD ). Rise time t r The rise time t r is defined as the time interval following the turn-on delay time, where the drainsource voltage drops from 90 % to 10 % of its initial value (V DD ). During this time, the drain 103

103 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules current will rise (therefore rise time ), i.e. the major part of the turn-on losses is generated during this time interval. The sum of turn-on delay time t d(on) and rise time t r is called turn-on time t on. As the drain-source voltage V DS will not yet have reached its forward on-state value V DS(on) = R DS(on) * I D at the (defined) end of t on, but still amounts to 10 % of V DD, there will still be higher losses after t on than the forward on-state losses. Turn-off delay time t d(off) After sudden turn-off of the positive gate-source control voltage V GG, the gate-source voltage V GS starts to decline with a time constant determined by the input capacitance of the MOSFET and the gate-source resistance R GS. The drain current which is coupled with the gate voltage in the active operating area via forward transconductance g fs = di D /dv GS also begins to decrease, whereas the drain-source voltage starts to rise accordingly. The turn-off delay time t d(off) is defined as the time interval between the moment when the gateemitter voltage V GE has declined to 90 % of its initial value (V GG ), and the drain-source voltage has risen to 10 % of the supply voltage V DD. Fall time t f The fall time t f is defined as the time interval following the turn-off delay time, where the drainsource voltage rises from 10 % to 90 % of its end value V DD. During this time, the drain current will fall accordingly (therefore fall time ), i.e. most of the turn-off losses are generated here. The sum of turn-off delay time t d(off) and fall time t f is called turn-off time t off. As the drain current I D will not have dropped to cut-off current level at the defined end of t off, but still amounts to 10 % of its forward on-state value, there will still be higher losses after t off than the blocking losses. Internal thermal resistance junction to case R thjc per MOSFET The thermal resistance R thjc describes the passage of heat between the MOSFET chips (index j) and the module case (index c). It characterizes the static heat dissipation of a MOSFET system within a module (mostly consisting of paralleled chips) and depends on chip size and module assembly. The temperature difference T jc between chip temperature T j and case temperature T case at a constant power dissipation P is defined as follows: T jc = T j - T case = P * R thjc. Contact thermal resistance case to heatsink R thch per MOSFET module The thermal resistance R thch describes the passage of heat between the module case (index c) and the heatsink (index h). It characterizes the static heat dissipation of a MOSFET module (possibly with several MOSFET switches) and depends on module size, heatsink and case surfaces, thickness and parameters of thermal layers (pastes, foils, print covers) between module and heatsink as well as on the mounting torque of the fixing screws. The temperature difference T ch between case temperature T c and heatsink temperature T h at a constant total amount of single power dissipations P n within the module is defined as follows: T ch = T case - T h = P n * R thch. Separate determination of R thjc and R thch is not possible for modules without base plate (e.g. SEMITOP, SKiiPPACK, MiniSKiiP). For these module, R thjh is indicated per MOSFET and per module. The temperature differences may be calculated in analogy. 104

104 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Mechanical data Apart from the case construction type, the following mechanical data are usually indicated in the datasheets: Mounting torque M 1 of the fixing screws (minimum and maximum value) in Nm or lb.in.; Mounting torque M 2 of the output terminals (minimum and maximum value) in Nm or lb. in.; Weight w of the module in g; Permissible acceleration under vibration a in m * s -2. Free-wheeling diodes/ inverse diodes Inverse diode forward voltage (negative source-drain voltage) V SD, V F Negative source-drain voltage drop with gate-source short-circuited (V GS = 0). V SD describes the forward characteristics of the parasitic inverse diodes of the MOSFETs or the hybrid freewheeling diodes, which are antiparallel to the MOSFETs. Parameters: forward current I F ; case temperature T case = 25 C Threshold voltage of the inverse diode V (T0) Forward slope resistance of the inverse diode r T With the help of threshold voltage and forward slope resistance a simplified approximation of the forward characteristic may be produced. The threshold voltage indicates the point of crossover with the voltage axis, the forward slope resistance determines the rate of rise of the characteristic. Reverse recovery time of the inverse diode t rr Reverse recovery time of the internal or hybrid MOSFET inverse diode during free-wheeling operation, i.e. when a high drain current -I D = I F is commutated with a high di F /dt and a high reverse voltage V R = V DD. Note: t rr depends very strongly on the temperature (almost doubled value between 25 C and Parameters: forward current I F ; reverse voltage V R, rate of fall of forward current -di F /dt, chip temperature T j = 25 C und 150 C. Recovered charge of inverse diode Q rr Recovered charge of internal or hybrid MOSFET inverse diode during free-wheeling operation, i.e. when a high drain current -I D = I F is commutated with a high di F /dt and a high reverse voltage V R = V DD. Note: Q rr depends very strongly on the temperature (initial value may be doubled or even increased eight-fold between 25 C and 150 C). Parameters: forward current I F ; reverse voltage V R, rate of fall of forward current -di F /dt, chip temperature T j = 25 C and 150 C. 105

105 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Diagrams Following the sequence of the datasheets, this chapter will give some hints concerning MOSFET datasheet diagrams. In the case where the diagram concerned is detailed in other chapters, this will be referred to. Rated power dissipation P D of a MOSFET module versus case temperature T case Figure 2.2 Rated power dissipation Based on the rated power dissipation per MOSFET P D(25 C) = (T jmax 25 C)/R thjc which is limited to T case = 25 C per definition, the function depicted in the diagram describes derating at a higher case temperature. Maximum safe operating area during pulse operation (SOA) As explained in chapter the MOSFET has to manage an almost rectangular characteristic i = f(u) between V DD and I L in the case of hard switching. The SOA (Safe Operating Area)-diagrams indicate to what extent this may be realized during different operations without risk of destruction: The SOA is terminated by the following parameters: - maximum drain current (horizontal termination); - maximum drain-source voltage (vertical termination); - maximum power dissipation or chip temperature (diagonal broken termination line in Figure 2.3); - turn-on resistance (diagonal continuous termination line). Figure 2.3 shows the maximum curve I D = f(v D ) during switching and on-state for different pulse durations t p at a double logarithmic scale. It is important that the maximum ratings are valid at a case temperature T c = 25 C and for single pulses, which will not heat the MOSFET over the maximum chip temperature T j = 150. Although the lowest of the depicted diagonals represents the hyperbola of the maximum stationary power losses P tot, MOSFET modules may only touch the linear characteristic area during switching operation. Analogous operation over a longer period of time is not permitted, since asymmetries due to spreading among the chips as well as negative temperature coefficients of the threshold voltages might cause thermal instability. 106

106 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Figure 2.3 Maximum safe operating area I D = f(v DS ) during pulse operation (SOA) Forward output characteristic I D = f(v DS ) Figure 2.4 shows the output characteristic (typical values) with parameter V GS (also see chapter ). Figure 2.4 Typical MOSFET output characteristic I D = f(v DS ) with parameter V GS Transfer characteristic I D = f(v GS ) The transfer characteristic (Figure 2.5) describes the behaviour of the MOSFET in the active operating area at V DS = 25 V (linear operation). The drain current is coupled with the gate-source voltage via I D = g fs * (V GS -V GS(th) ). 107

107 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Figure 2.5 Typical transfer characteristic I D = f(v GS ) On-resistance versus chip temperature see chapter 2.6 Drain current derating versus case temperature see chapter 2.6 Drain-source breakdown voltage versus temperature As shown in Figure 2.6 the drain-source breakdown voltage of a MOSFET increases linearly to the temperature. As the maximum rating indicated in the datasheets refers to T j = 25 C, deratings at low chip temperatures have to be accepted. Figure 2.6 Drain-source breakdown voltage V (BR)DSS versus T j 108

108 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Drain-source voltage derating versus rate of fall of drain current see chapter Internal capacitances versus collector-emitter voltage see chapter Gate charge characteristic see chapter Diode forward characteristic see chapter On-resistance versus drain current Figure 2.7 explains the relationship between on-resistance R DS(on) and drain current I D or gatesource voltage V GS for a fully controlled MOSFET. Figure 2.7 Typical characteristic of on-resistance R DS(on) versus drain current I D and gate-source voltage V GS The on-resistance decreases with increase of the gate-source voltage. At any point of the curve, a slight increase of R DS(on) together with the drain current has to be considered. Gate-source threshold voltage versus temperature Figure 2.8 shows three curves with typical and limit values characterizing the relationship between gate-source threshold voltage V GS(th) and MOSFET chip temperature T j. 109

109 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Figure 2.8 Gate-source threshold voltage V GS(th) versus temperature V GS(th) will decrease linearly when T j increases. The temperature coefficient of the threshold voltage amounts to about 10 mv/k within the temperature range of C. Transient thermal impedances for IGBTs and free-wheeling diodes see chapter IGBT-modules [264], [265] Maximum ratings IGBTs/ module structure Collector-emitter voltage V CES or V CE Maximum collector-emitter voltage with gate-emitter short-circuited (V GE = 0) Parameter: case temperature T case = 25 C Collector-gate voltage V CGR Maximum collector-gate voltage, Parameters: external gate-emitter resistance R GE ; case temperature T case = 25 C Continuous collector current I C Maximum direct current at collector output Parameter: case temperature, e.g. T case = 25 C, 80 C: I C, I C Peak value of a periodic collector current I CM or pulsed collector current I Cpuls Peak value of current at collector output during pulse operation Parameters: pulse duration t p, case temperature, z.b. T case = 25 C, 80 C and pulse/ break ratio Gate-emitter voltage V GES or V GE Maximum gate-emitter voltage Parameter: case temperature T case = 25 C 110

110 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Total power dissipation P tot Maximum power dissipation per transistor/ diode or within the whole power module P tot = (T jmax -T case )/R thjc, Parameter: case temperature T case = 25 C Operating temperature range T vj or T j ; T j(min)...t j(max) Permissible chip temperature range within which the module may be permanently operated. Storage temperature range T stg ; T stg(min)...t stg(max) ) Temperature range within which the module may be stored or transported without being subject to electrical load. Isolation test voltage V isol or V is Effective value of the permissible test voltage between input terminals/ control terminals (shortcircuited, all terminals connected to each other) and module base plate. Parameters: test duration (1 min, 1 s), rate of rise of test voltage, if required; according to IEC (1991), EN (1993), section (corresponds to VDE 0558, volume 1-1: ) and DIN VDE 0160 ( ), section 7.6 (corresponds to EN (1994)/ E VDE 0160 ( ) the test voltage shall only rise gradually up to its maximum rating. Grade of humidity describes the permissible ambient conditions (atmospheric humidity) according to DIN Grade of climate describes the permissible ambient test conditions (climate) according to DIN IEC 68-1 Inverse diodes/ free-wheeling diodes Forward current I F Maximum forward current value of the inverse or free-wheeling diodes, Parameter: case temperature, e.g. T case = 25 C, 80 C Peak periodic forward current I FM or pulsed forward current I Fpuls Peak value of the diode current during pulse operation Parameters: pulse duration t p, case temperature, e.g. T case = 25 C, 80 C Characteristics IGBTs/ module structure Collector-emitter breakdown voltage V (BR)CES Breakdown voltage between collector and emitter, gate-emitter short-circuited (V GE = 0), Parameters: collector blocking current I C, case temperature T case = 25 C Gate-emitter threshold voltage V GE(th) Gate-emitter voltage above which considerable collector current will flow Parameters: collector-emitter voltage V CE = V GE, collector current I C, case temperature T case = 25 C 111

111 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Collector-emitter cut-off current I CES Collector-emitter blocking current with gate-emitter short-circuited (V GE = 0) and collectoremitter voltage V CE = V CES Parameter: chip temperature, e.g. T j = 25 C and 125 C Gate-emitter leakage current I GES Leakage current between gate and emitter with collector-emitter short-circuited (V CE = 0) and at maximum gate-emitter voltage V GE Parameter: gate-emitter voltage V GE, case temperature T case = 25 C Collector-emitter saturation voltage V CEsat Saturation value of collector-emitter voltage (on-state voltage drop of the active IGBT) at a specified collector current I C (at rated current, see chapter 2.3.3, or at maximum collector current). For PT-IGBTs V CEsat will drop proportionally to the temperature within rated current range, for NPT-IGBTs, however, it will rise proportionally to the temperature. Parameters: collector current I C, gate-emitter voltage V GE, chip temperature, e.g. T j = 25 C and 125 C. For calculation of forward on-state losses the following parameters are often indicated additionally in the datasheets: V CE(TO) (static collector-emitter threshold voltage) and r CE (onstate slope resistance) of a substitutional straight line. V CEsat = f(i C ) = V CE(TO) + r CE * I C This means that, for calculation, the saturation voltage characteristic is approximated by means of a diode characteristic. Forward transconductance g fs Quotient of changing collector current and gate-emitter voltage at a specified collector current I C, Parameters: collector-emitter voltage V CE, collector current I C ( rated current, resp.), case temperature T case = 25 C Capacitance chip-case C CHC Capacitance between a sub-component and case base plate or heatsink potential Parameter: case temperature T case = 25 C Input capacitance C iss Capacitance between gate and emitter with collector-emitter short-circuited for AC and gateemitter voltage V GE = 0. Parameters: collector-emitter voltage V CE, measuring frequency f, case temperature T case = 25 C Output capacitance C oss Capacitance between collector and emitter with gate-emitter short-circuited (V GE = 0). Parameters: collector-emitter voltage V CE, measuring frequency f, case temperature T case = 25 C Reverse transfer capacitance (Miller capacitance) C rss, C mi Capacitance between collector and gate with collector-emitter short-circuited for AC and gateemitter voltage V GE = 0. For measuring the emitter has to be connected with the protective shield of the measuring bridge. Parameters: collector-emitter voltage V CE, measuring frequency f, case temperature T case = 25 C 112

112 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Parasitic collector-emitter inductance L CE Inductance between collector and emitter Switching times More related to practice than switching times of MOSFETs, switching times of IGBTs indicated in the datasheets are determined from a measuring circuit under ohmic-inductive load according to Figure 2.9a. The load time constant L/R is high compared to the switching frequency cycle duration T = 1/f, so that an continuous load current is generated by the load inductance. Just as with MOSFETs, switching times of IGBTs refer to the gate-emitter characteristics during turn-on and turn-off, see Figure 2.9b. Switching times as well as real current and voltage characteristics are determined by internal and external capacitances, inductances and resistances of the gate and drain circuit; for this reason, all indications in the datasheets and the characteristics depicted therein may only serve as a guide. +15 V R L I L V GG+ R Gon i C V CC v CE R Goff v GE 0 V E x E V GG- -15 V a) 113

113 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules v GE v GE V GG+ 90% 10% t V GGi C idealized waveform I L 90% I L 90% I L t d(on) 10% I L t r 10% I L t d(off) t f t t on t off v CE V CC Turn-on Turn-off t b) Figure 2.9 a) Measuring circuit b) Definition of IGBT switching times under ohmic-inductive load [264],[265] The following parameters are indicated in the datasheets relevant to switching times: measuring circuit, collector-emitter supply voltage V CC, gate-emitter control voltages V GG+, V GGor V GE, collector current I C, external gate series resistors R Gon,R Goff (resistance of control circuit at turn-on and turn-off), chip temperature T j = 125 C Turn-on delay time t d(on) As already mentioned, the total forward on-state current of the IGBT is to be conducted by the load inductance before turn-on. After sudden turn-on of a positive gate-emitter control voltage, the gate-emitter voltage V GE starts to rise with a time constant determined by IGBT input capacitance and gate resistance. As soon as the threshold voltage V GE(th) has been reached, the collector current I C will start to rise. The turn-on delay time t d(on) is defined as the time interval between the moment when the gateemitter voltage v GE has reached 10 % of its end value, and the collector current i C has increased to 10 % of the load current. Rise time t r The rise time t r is defined as the time interval following the turn-on delay time, where the collector current i C increases from 10 % to 90 % of the load current. During this time interval most of the turn-on losses are generated in the IGBT, since a certain share of I L is continuously conducted through the free-wheeling diode as long as the i C -value is below load current I L. 114

114 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Therefore, the collector-emitter voltage v CE will not drop significantly below the collectoremitter supply voltage V CC. The difference between V CC and v CE depicted in Figure 2.9b during t r is basically determined by the transient voltage drop over the internal parasitic inductances of the commutation circuit. The sum of turn-on delay time t d(on) and rise time t r is called turn-on time t on. As the collector-emitter voltage v CE will not yet have reached its forward on-state value V CEsat at the (defined) end of t on, the major share of the switching losses will be generated after t on. Turn-on peak current: after the total load current I L has been commutated to the IGBT, the free-wheeling diode will block, releasing its recovered charge Q rr at the same time. Therefore, the IGBT collector current i C will rise during reverse recovery of the free-wheeling diode (t rr ) by the value of the peak reverse recovery current I RRM over I L (turn-on peak current see Figure 2.10). v CE (200 V / Div) i C (20 A / Div) v GE (20 V / Div) 0,2 µs / Div Figure 2.10 Commutation from the conducting free-wheeling diode to the IGBT (turn-on peak current) during turn-on of an IGBT Dynamic saturation voltage: after having dropped very steeply during turn-on time, the collector-emitter voltage v CE will decline relatively slowly (within µs-range) to its static value V CEsat. This dynamic saturation phase is necessary for flooding the wide n - -zone of the IGBT with (bipolar) minority carriers (conductivity modulation). 115

115 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Turn-off delay time t d(off) After sudden turn-off of the positive control voltage and turn-on of a negative gate-source control voltage, the gate-source voltage V GS starts to decline with the time constant determined by the input capacitance of the IGBT and the gate resistance. The collector-emitter voltage v CE of the IGBT begins to rise. The IGBT s collector current i C cannot drop considerably at that time, since the free-wheeling diode is poled in reverse direction as long as V CC is higher than v CE and, therefore, is not able to take over load current I L. Due to this, the turn-off delay time t d(off) for IGBTs is defined as the time interval between the moment when the gate-emitter voltage v GE has dropped to 90 % of its turn-on value and the collector current has declined to 90 % of the load current value. Fall time t f As soon as the collector-emitter voltage v CE has exceeded the supply voltage V CC during turn-off of the IGBT, the load current may commutate to the free-wheeling diode, which is poled in forward direction at that time and the collector current i C will drop. The fall time t f is defined as the time interval, where the collector current i C drops from 90 % to 10 % of the load current I L. The overshoot of v CE over V CC indicated in Figure 2.11 mainly results from the parasitic inductances of the commutation circuit and increases proportionally to the turn-off speed - di C /dt of the IGBT. The turn-off time t off is defined as the sum of turn-off delay time t d(off) and fall time t f. Since i C will not have dropped to cut-off current level at the defined end of t off, but still amounts to 10 % of the load current, the losses arising after t off will still exceed the blocking losses. Tail time t t, tail current I t Other than with MOSFETs, the drastic decrease of power losses in IGBTs achieved by the injection of minority carriers in the n - -zone is realized by generation of a tail current I t, shown in Figure The tail time t t is not included in the turn-off time t off per definition, however it contributes to a significant share of switching losses due to the collector-emitter supply voltage V CC which has already been applied during that time interval. 116

116 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules v CE (200 V / Div) i C (20 A / Div) v GE (20 V / Div) 0,2 µs / Div Figure 2.11 Turn-off characteristics of an NPT-IGBT Energy dissipation during turn-on E on ; energy dissipation during turn-off E off per cycle The typical values of E on and E off of an IGBT are indicated in the diagram turn-on/ turn-off energy E on, E off as a function of the collector current I C included in the datasheet. Power dissipation during switching may be calculated by multiplication of the switching frequency f with E on or E off, respectively: P on = f * E on or P off = f * E off. The turn-on energy dissipation E on comprises the effects of the reverse peak current of the freewheeling diode, which corresponds to the diode integrated in the power module. Energy dissipation during turn-on may be determined by integration of the power dissipation during turn-on P on up to the moment when V CE amounts to approximately 3 % of the collector-emitter supply voltage V CC. Apart from the power losses generated during the actually defined turn-off time t off = t d(off) + t f, energy dissipation during turn-off also comprises the tail current losses generated during the tail time t t up to the moment when the collector current has fallen below load current by 1 %. Parameters: operating voltage, chip temperature T j = 125 C, control voltages, gate series resistance. Thermal resistance junction to case R thjc per IGBT The thermal resistance R thjc describes the passage of heat between the IGBT chips (index j) and the module case (index c). It characterizes the static heat dissipation of an IGBT system within a module (mostly consisting of paralleled chips) and depends on chip size and module assembly. The temperature difference T jc between chip temperature T j and case temperature T case at a constant power dissipation P is defined as follows: T jc = T j - T case = P * R thjc. Contact thermal resistance case to heatsink R thch per IGBT module The thermal resistance R thch describes the passage of heat between module case (index c) and heatsink (index h). It characterizes the static heat dissipation of an IGBT module (possibly with several IGBT switches) and depends on module size, heatsink and case surfaces, thickness and parameters of thermal layers (pastes, foils, print covers) between module and heatsink as well as on the mounting torque of the fixing screws. 117

117 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules The temperature difference T ch between case temperature T c and heatsink temperature T h at a constant total amount of single power dissipations P n within the module is defined as follows: T ch = T case - T h = P n * R thch. Separate determination of R thjc and R thch is not possible for modules without base plate (e.g. SEMITOP, SKiiPPACK, MiniSKiiP). For these module, R thjh is indicated per IGBT and per module. The temperature differences may be calculated in analogy. Mechanical data Apart from the case construction type mainly the following mechanical data are indicated in the datasheets: Mounting torque M 1 of the fixing screws (minimum and maximum value) in Nm or lb.in.; Mounting torque M 2 of the output terminals (minimum and maximum value) in Nm or lb. in.; Weight w of the module in g; Permissible acceleration under vibration a in m * s -2. Free-wheeling diodes Inverse diode forward voltage (negative emitter-collector voltage) V EC, V F Negative emitter-collector voltage drop with gate-emitter short-circuited (V GE = 0). V EC describes the forward characteristics of free-wheeling diodes, which are connected antiparallel to the IGBTs. Parameters: forward current I F ; case temperature T case = 25 C Threshold voltage of the inverse diode V (T0) Forward slope resistance of the inverse diode r T With the help of threshold voltage and forward slope resistance a simplified approximation of the forward characteristic may be produced. The threshold voltage indicates the point of crossover with the voltage axis, the forward slope resistance determines the rate of rise of the characteristic. Reverse recovery time of the inverse diode t rr Reverse recovery time of the IGBT inverse diode during free-wheeling operation, i.e. when a high collector current -I C = I F is commutated with a high di F /dt and a high reverse voltage V R = V CC. Note: t rr is very strongly dependent on the temperature (almost doubled value between 25 C and 150 C). Parameters: forward current I F ; reverse voltage V R, rate of fall of forward current -di F /dt, chip temperature T j = 25 C and 150 C. Recovered charge of inverse diode Q rr Recovered charge of IGBT inverse diode during free-wheeling operation, i.e. when a high collector current -I C = I F is commutated with a high di F /dt and a high reverse voltage V R = V CC. Note: Q rr is very strongly dependent on the temperature (initial value may be doubled or even increased eight-fold between 25 C and 150 C). Parameters: forward current I F ; reverse voltage V R, rate of fall of forward current -di F /dt, chip temperature T j = 25 C and 150 C. 118

118 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Thermal resistance junction to case R thjc per diode The thermal resistance junction to case R thjc describes the passage of heat between diode chips (index j) and module base plate (index c) Diagrams Following the sequence of the datasheets, this chapter will give some hints concerning IGBT datasheet diagrams. In cases where the diagram concerned is detailed in other chapters, this will be referred to. Maximum total power dissipation P tot of IGBT module versus case temperature T case Figure 2.12 Maximum total power dissipation Based on the maximum total power dissipation per IGBT (or per free-wheeling diode) P tot(25 C) = (T jmax 25 C)/R thjc which is limited to T case = 25 C per definition, the function depicted in the diagram describes derating at a higher case temperature. 119

119 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Turn-on/ turn-off energy E on, E off per pulse of an IGBT as function of the collector current I C Figure 2.13 Turn-on/ -off energy dissipation as function of I C The turn-on/-off energies E on, E off determined from a measuring circuit under ohmic-inductive load are indicated versus different collector currents I C (e.g. chip temperature T j = 125 C, collector-emitter supply voltage V CC = 600 V) with specified control parameters. Switching losses may be determined by multiplying dissipation energy and switching frequency f: P on = f * E on P off = f * E off. E on and E off are indicated for IGBT at rated current (I T case = 80 C) in the characteristic values of the datasheet. Turn-on and turn-off energy E on, E off per pulse of an IGBT as function of the gate series resistors R G (R Gon, R Goff ) see chapter Maximum safe operating area during switch operation (SOA) As explained in chapter the IGBT has to manage an almost rectangular characteristic i = f(u) between V CC and I L in case of hard switching. The SOA (Safe Operating Area)-diagrams indicate to what extent this may be realized during different operations without risk of destruction: - SOA for switching, on-state and single pulse operation - RBSOA (Reverse Biased SOA) for periodic turn-off - SCSOA (Short Circuit SOA) for non-perdiodic turn-off of short circuits (chapter 3.6.2) The SOA is limited by the following parameters: - maximum collector current (horizontal limit); - maximum collector-emitter voltage (vertical limit); - maximum power dissipation or chip temperature (diagonal limits) see Figure 2.14; Maximum safe operating area during pulse operation (SOA) Figure 2.14 shows the maximum curve I C = f(v CE ) during switching and on-state for different pulse durations t p at a double logarithmic scale. 120

120 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules It is important that the maximum ratings are valid at a case temperature T c = 25 C and for single pulses, which will not heat the IGBT over the maximum chip temperature T j = 150. Although the lowest of the depicted diagonals represents the hyperbola of the maximum stationary power losses P tot, IGBT modules may only touch the linear characteristic area with approximately V CE > 20 V or V GE < 9 V during switching operation. Analogous operation over a longer period of time is not permitted, since asymmetries due to variation among the chips as well as negative temperature coefficients of the threshold voltages might cause thermal instability. Figure 2.14 Maximum safe operating area I C = f(v CE ) during pulse operation (SOA) Turn-off safe operating area Figure 2.15 shows the turn-off safe operating area of an IGBT. Figure 2.15 Turn-off safe operating area (RBSOA) 121

121 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules During periodic turn-off the IGBT may effect a hard turn-off of I C = T C for T jmax and defined driver parameters, provided that v CE (chip) has reached V CES -level (influence of parasitic inductances and driver parameters, see chapters and 3.5.2). Safe operating area at short circuit see chapter Derating of collector current versus case temperature see chapter 2.6; analogous to Figure 2.23b Forward output characteristic I C = f(v CE ) Figure 2.16 shows the output characteristics for T j = 25 C and 125 C (typical values) with parameter V GE, also see chapters and 2.6. a) b) Figure 2.16 Typical IGBT output characteristic I C = f(v CE ) with paramter V GE a) T j = 25 C b) T j = 125 C Transfer characteristic I C = f(v GE ) The transfer characteristic (Figure 2.17) describes the behaviour of the IGBT within the active area at V CE = 20 V and t p = 80 µs (linear operation). The collector current is coupled with the gate-emitter voltage via transfer transconductance: I C = g fs * (V GE -V GE(th) ). 122

122 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Figure 2.17 Typical transfer characteristic I C = f(v GE ) Gate charge characteristic see chapter Internal capacitances versus collector-emitter voltage see chapter Switching times versus collector current Figure 2.18 shows typical dependencies of switching times t d(on) (turn-on delay time), t r (rise time), t d(off) (turn-off delay time) and t f (fall time) on the collector current I C during hard switching of inductive loads. Figure 2.18 Typical dependency of switching times on collector current (inductive load) The slightly overproportional increase of t r verifies that di C /dt does not increase to the same extent as I C when the collector current rises. 123

123 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Switching times versus gate resistor see chapter CAL diode forward characteristic see chapter Diode turn-off energy dissipation Figure 2.19 demonstrates the dependency of the diode turn-off energy E offd on the diode current I F conducted before turn-off, and on the turn-on speed of the IGBT determined by gate resistance R G, during current commutation between free-wheeling diode and IGBT (hard switching). Figure 2.19 Diode turn-off energy dissipation E offd versus collector current I C and gate resistance R G As expected, the diode turn-off losses increase with the forward current as well as with the rate of rise of commutation current due to a simultaneous rise of storage charge and reverse current amplitude (see chapter ). Transient thermal impedances of IGBT and free-wheeling diode see chapter Free-wheeling diode reverse recovery current as function of forward on-state current Figure 2.20 shows typical values of the peak reverse recovery current I RRM versus forward current I F and di/dt determined by the gate resistance R G = R Gon. 124

124 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Figure 2.20 Typical peak reverse recovery current I RRM of free-wheeling diode versus I F and R G As expected, the peak reverse recovery current is higher, the faster the IGBT is switched on (low R Gon ). At first, the reverse recovery current will increase together with rising forward current. If high collector currents are applied, the share of charge carriers in the CAL-diode drift area, which already re-combine during commutation, will increase with the duration of commutation; therefore, I RRM will again drop in the high current range. Free-wheeling diode reverse recovery current as function of di F /dt Figure 2.21 depicts the typical dependency of the free-wheeling diode reverse recovery current I RRM on di/dt, determined by control of the given gate resistances R G = R Gon of the IGBT on the measuring conditions indicated. Figure 2.21 Typical free-wheeling diode reverse recovery current I RRM versus di/dt and R G The reverse recovery current increases almost linearly to di/dt. 125

125 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules Free-wheeling diode recovered charge as function of di F /dt Figure 2.22 shows the typical dependency of the free-wheeling diode recovered charge Q rr on di/dt for different collector currents I C. In addition, the gate resistances R G = R Gon have been entered which determine the given di/dt on the measuring conditions indicated. Figure 2.22 Typical free-wheeling diode recovered charge versus di/dt, R G and I C Just like the reverse recovery current, the free-wheeling diode recovered charge will rise together with the collector current and di/dt. The rate of rise will be more distinct for high collector currents than for the low current range. Rated collector current at short circuit as a function of gate-emitter voltage and temperature see chapter Special parameters for MiniSKiiPs Apart from IGBTs and diodes for inverters and brake choppers diodes (or thyristors) for input rectifiers are also integrated in the MiniSKiiP. Supplementary to forward and blocking characteristics (maximum ratings, characteristics), the follwing parameters are specified for MiniSKiiPs: Rectifier diode surge forward current I FSM Peak value of a sinusoidal wave 50 Hz, which the diode is able to withstand without being damaged in the case of breakdown, if this does not occur too often. Rectifier diode peak load integral i 2 dt Reference parameter for the selection of fuses to be calculated as follows: i 2 dt = I FSM 2 * T/4 = 5 * 10-3s * I FSM 2 (@ f = 50 Hz) Resistance/ temperature coefficient of the temperature sensor Features of current sensors 126

126 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules 2.5 Special parameters for SKiiPPACKs SKiiPPACK datasheets have to include for example: - static/dynamic maximum ratings and characteristics of IGBT and free-wheeling diode chips; - thermal characteristics (including heatsink); - indications on isolation voltage of module and of all potential separations; - indications on threshold values of protective function; - input level, output performance and delay times of the driver and - indications on features related to mechanical stress and climate conditions. Therefore, SKiiPPACK datasheets are much more complex, although, on the other hand, all indications concerning the dependency of parameters on different driver conditions may be ignored. 2.6 Temperature dependency of static and dynamic characteristics of power modules Almost all electrical characteristics of IGBTs, power MOSFETs and free-wheeling diodes are more or less dependent on the chip temperature. The following table reflects the characteristic tendencies of the most important component parameters at rising temperature (<: rises; <<: rises steeply; >: falls; -: no notable temperature dependency). The special features marked with * are only valid for PT-IGBTs. For dimensioning in practice, the parameters marked with!, which will be detailed later on, are of main importance due to their distinct dependency on the temperature. For the temperature dependency of the parameters of free-wheeling diodes please refer to the explanations under chapter 1.3. Parameter MOSFET IGBT Free-wheeling diode Avalanche breakdown voltage < < < Blocking current, blocking power dissipation < < < Turn-on resistance/forward on-state voltage, <<! <(>*)! > forward power dissipation Turn-on time/energy dissipation during turn-on < < - Turn-off time/energy dissipation during turn-off < <(<<*)! << Threshold voltage > > > Forward transconductance > > - For the interpretation of the parameters indicated in the datasheets it should be taken into consideration that many ratings for power MOSFETs and IGBTs are related to a case temperature of 25 C and have still to be converted to the maximum operating temperature by means of other indicated parameters. This goes mainly for the maximum permissible drain or collector current I D, I DM, I C, I CM and the maximum power dissipation P tot or P D, respectively, which have to be reduced to ratings under realistic operating conditions as described in chapter The required current reduction is determined by the forward and blocking power dissipations which are also temperature-dependent, as well as by the switching losses. 127

127 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules The fact that blocking current and blocking power dissipation will increase by factor between 25 C and 125 C is of only minor importance for dimensioning, because the blocking power dissipation contributes to only a small share of total power dissipation. In contrast to this, the forward on-state temperature dependency is of major importance, which, therefore, shall be examined separately for the single components: Power MOSFET Figure 2.23 shows the increasing on-resistance R DS(on) of a power MOSFET and the resulting over-proportional derating of the continuos drain current I D at higher temperatures with an example. a) b) Figure 2.23 Forward on-state behaviour of a 100 V power MOSFET versus temperature a) On-resistance R DS(on) b) Continuous drain current I D derating R DS(on) is doubled within the operating temperature range of C; at T case = 80 C only 75 % of the maximum drain current I D can be utilized even under static conditions. On the other hand, the positive temperature coefficient of the forward on-state voltage offers advantages such as simplified paralleling ability and high resistivity during hard switching. IGBT The various concepts of IGBTs (PT/NPT, see chapter 1.2.1) also differ in their thermal behaviour. This is explained in Figure 2.24 with the basic characteristic of the collector-emitter saturation voltage V CEsat over the collector current I C at a chip temperature of 25 C and 125 C. 128

128 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules I C [A] C 125 C I C [A] C 125 C V CE GE = 15 V a) b) V CE GE = 15 V Figure 2.24 Forward characteristics of IGBTs a) SEMITRANS NPT-IGBT 100A@25 C b) PT-IGBT 100A@25 C The temperature coefficient of the forward on-state voltage V CEsat of the NPT-IGBT is positive for the whole current (approx. 8 mv/k at I C). The temperature coeffcient of V CEsat of the PT-IGBT, however, is negative for the actually utilized forward current range and rises to zero only when rated current has been approximated. The resulting consequences for NPT-IGBTs compared to PT-IGBTs are higher forward power dissipation on the one hand, and a better current symmetry on the other hand (homogeneous temperature spreading/ ruggedness, unselected paralleling ability). The I C -derating characteristic versus temperature analogous to Figure 2.22b is included in the IGBT-datasheets as well. As already mentioned, MOSFET and IGBT switching times and switching losses will also increase when the temperature rises. However, since dimensioning for hot chips has to be done in practice anyway, most ratings included in the current datasheets are taken at 125 C. In this respect, another difference between NPT- and PT-IGBTs should be referred to (Figure 2.25, see chapters and 1.2.3) 129

129 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules v CE (200 V / Div) v CE (200 V / Div) i C (20 A / Div) i C (20 A / Div) v GE (20 V / Div) v GE (20 V / Div) 0,2 µs / Div a) b) 0,2 µs / Div Figure 2.25 Turn-off behaviour of IGBTs a) SEMITRANS NPT-IGBT b) PT-IGBT The tail current I t generated during turn-off will increase together with the temperature. Whereas the tail current of an NPT-IGBT will have risen by almost 100 % at 125 C compared to 25 C (Figure 2.25a), the tail current of PT-IGBT (Figure 2.25b) will be almost tripled within this temperature range. This results in clearly reduced switching losses of NPT-IGBTs at high temperatures compared to PT-types. The minor temperature dependency of threshold voltage and forward transconductance has practically no importance for switching operation. But it is a basic restriction to linear operation of power modules. 2.7 Reliability Reliability, i.e. maintaining the promised characteristics over a defined period of time, is one of the most important quality features of power modules. On the one hand, power modules are outstanding for their high electrical and thermal efficiency; on the other hand, premature failure may cause danger, direct and consequent damage and, last but not least, high costs. Reliability is very difficult to express due to comparably small lots, often extreme long life requirements ( a) and complex test specifications, but may be defined by - exact control of all influences on production processes (built-in reliability), - reliability testing under conditions very close to the application in order to discover typical failure mechanisms, - testing of the components within the system and control of the most important parameters. [231] Some selected tests for power modules are shown in the following without going into details of the extensive EN ISO 9001 quality assurance system, based on which SEMIKRON is able to grant a 2 year TQM warranty on all its power semiconductors. 130

130 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules The following standard tests are being carried out for release and re-qualification of MOSFET and IGBT modules still to become finalised by further, individual product-specific reliablity testing: Test Standards Test conditions High temperature blocking voltage DIN 41749, IEC h, V DSmax, V CEmax, T jmax (HTRB) Hot gate stress DIN 45930, CECC , h, V GSmax, V GEmax, T jmax High temperature storage DIN 45930, CECC , h, T stgmax Low temperature storage 1.000h, T stgmin Humidity temperature blocking DIN 45930, CECC , h, 85 C, 85 % relative humidity. V CE, V DS = 0.8 V CEmax, V DSmax ; 80 V Temperature cycling DIN IEC test Na 100 temperature cycles T stgmax /T stgmin Power cycling DIN 41794, IEC cycles, T j =100 K Solder temperature DIN IEC , test Tb 260±5 C, 10±1 s Solderability DIN IEC , test Ta 235±5 C, aging 3 Vibration/ acceleration acc.to DIN IEC ,test F c 5 g The following failure criteria according to standard MIL-STD are valid: Gate-drain-/gate-emitter leakage current I GSS, I GES : > ± 20 na or >100 % of initial rating Zero gate voltage drain current or collector-emitter cut-off current I DSS, I CES : > ± 100 µa or >100 % of initial rating (max. 2x of specified max. rating) On-resistance/forward voltage R DS(on), V CEsat : > 120 % of initial rating max. change of threshold voltage V GS(th), V GE(th) : >± 20 % of initial rating Thermal resistance junction to case R thjc : > 120 % of initial rating Isolation test voltage V isol : < specified maximum rating Figure 2.26 and Figure 2.27 show examples for test procedures depicting measuring circuits and procedures for temperature cycling and power cycling. Temperature versus time of DUT in temperature cycling test Tmax T max DUT T [ C] Tmin SEMIKRON standards: Tmin/Tmax = -55/+150 C -40/+125 C - maximum storage temperatures - cycle time depending on thermal load T min t [min] Figure 2.26 Temperature cycling: measuring circuit and measuring procedure 131

131 2 Datasheet parameters for MOSFET, IGBT, MiniSKiiP- and SKiiPPACK modules SEMIKRON-THERM-SIM Tjunction,max DUT Tcase Tcase,max SEMIKRON standards: heating and cooling time usually controlled by Tcase (alternatively time-controlled) Tcase,min = 40 C Tjunction,max = 150 C 1 cycle 60 seconds Tcase,min 0s 10s 20s 30s 40s 50s 60s 70s 80s 90s Time Figure 2.27 Power cycling: measuring circuit and measuring procedure Principal characteristics of power modules related to reliability may be checked by means of temperature and power cycling testing, see also chapter Therefore, these tests are of decisive importance for the qualification of modules. 132

132 3 Hints for application 3 Hints for application 3.1 Dimensioning and selection of MOSFET, IGBT and SKiiPPACK modules The selection of power modules for any static or short-term (overload) operating conditions of a concrete application is subject to the consideration of - voltage capacitance, - current carrying capacity under realizeable cooling conditions and with reference to the switching frequency and - safe operating areas (SOA). Under no circumstances that might occur during any static or dynamic operation must the maximum ratings for blocking voltage (except for avalanche-proof MOSFETs), peak current, junction temperature and safe operating area (see chapter 2.7) indicated in the datasheets be exceeded. The same goes for the limit values of module case parameters (e.g. isolation voltage, vibration strength, climate persistence, assembly instructions). For the sake of high reliability and long life, modules have to be designed for managing a specified number of switching cycles, which usually go along with considerable temperatures cycling. (Chapters and 3.2.3). Furthermore, serious dimensioning will not presuppose total thermal utilization of the semiconductors to their maximum ratings T j(max) (e.g. 150 C) in order to keep a margin for theoretically unforeseeable cases and to be able to fall back upon the static and dynamic characteristics taken at a maximum of 125 C and guaranteed by the manufacturers. As already explained in chapter 2.6, the most important characteristics of power modules will deteriorate when the temperature rises. For this and other reasons, the determination of the maximum operating temperature has to be paid special attention to Forward blocking voltage Since most power modules are applied in DC-voltage links, which are AC-voltage supplied via single-phase or three-phase rectifier bridges, the blocking voltages of universally applied IGBTs (600 V, 1200 V, 1700 V) are adjusted to common line voltage levels; the same goes for highly blocking MOSFET-modules. Therefore, firstly a rough selection is made from line voltage (control angle 0 for controlled rectifiers) V N or no-load direct voltage V di as follows: V N /VrectificationV di /VV DSS, V CES /V 24B B B B , B B B

133 3 Hints for application Afterwards, it has to be checked whether on condition of utmost voltage capacitance, i.e. - maximum stationary input voltage (nominal voltage + line voltage tolerance, e.g. 15 %), - transient line overvoltage, as far as it has not yet been reduced by line filters, DC-link capacitors and circuits on the DC-side (suppressor diodes, snubbers, varistors), - turn-off overvoltage V d + V the maximum module voltage will be exceeded with V = L σ * I max /t f with parameters as follows: L σ : parasitic commutation inductance, see chapters and 3.4.2, I max : maximum turn-off collector or drain current (mostly with active shortcircuit turn-off, see chapter 3.6), t f : fall time of collector or drain current. Here, special attention has to be paid to the fact that the maximum rating for V DSS /V CES indicated in the datasheets is related to the characteristics of the transistor chips and not to the dynamic terminal behaviour of the module. The internal module inductance L CE also indicated in the datasheets (e.g nh) therefore corresponds to a share of L σ ; the voltage applied to the chips will exceed the voltage to be taken at the terminals by L CE * I/t f during turn-off. This is expressed by a diagram in the SEMITRANS MOSFET datasheets, which explains the derating of the permissible drain-source voltage at the terminals versus the rate of fall of the drain current di D /dt I D /t f (Figure 3.1). Figure 3.1 Drain-source voltage V DS derating of a SEMITRANS MOSFET-module SKM 111 A versus drain current rate of fall di D /dt Forward current The maximum continuous drain or collector currents I D or I C, respectively, indicated in the datasheets as typical currents for module designation and as maximum ratings may be calculated for a stationary fully controlled transistor at a case temperature T case of, for example, 25 C or 80 C according to the following formula I D ( T T ) ( R R ) = (MOSFET-module) j(max) case DS(on) or I C = (T j(max) - T case )/(V CEsat * R thjc ) (IGBT-module) thjc 134

134 3 Hints for application For modules without base plate T h will replace T case and R thjh will replace R thjc. The ratings for R DS(on) and V CEsat have been taken at a maximum chip temperature T j(max). These indications are only intended to give an orientation aid, since under real operating conditions switching and (low) blocking losses will occur additionally to the forward on-state losses, the case temperature will differ and the static maximum ratings of R DS(on) or V CEsat will not be reached during the whole turn-on procedure. At a given case temperature (25 C, 80 C), the peak current values for I DM or I CM are specified for single pulses with a pulse duration of 1 ms and, at the same time, are designating the maximum current ratings for periodic turn-on and turn-off (SOAR). Therefore, the utilizeable forward current is determined - mainly by the total power dissipation of the transistors and free-wheeling diodes of a power module and the chip temperatures within the transistors and free-wheeling diodes arising under specific cooling conditions (R thca ), which must not exceed T j(max) (chapter 3.2.2), - by the limits of the maximum safe operating area, see chapters 2.2 and 2.3. To avoid exceeding the limit values during hard turn-on under ohmic-inductive load, the amount of load current and reverse recovery current of the free-wheeling diode must not exceed I DM or I CM, see Figure 3.2. Due to the reasons mentioned in chapter a compromise has to be found between turn-on speed of the transistor (increase of turn-on losses!) and conductable load current in most cases. Further restrictions in practice have possibly to be accepted resulting from the characteristics of active overcurrent protection in the driver (see chapter 3.5) Switching frequency Figure 3.2 shows the measured turn-on and turn-off behaviour of a power MOSFET and an IGBT module for one specific operating point. Apart from the characteristics for v DS or v CE and i D or i C also the instantaneous power dissipation p(t) had been determined by multiplication of instantaneous current and voltage values; the integral of p(t) reflects the total MOSFET and IGBT losses over the whole period. To determine total power dissipation of the power module, the losses of the free-wheeling diode(s) within the module have to be added to the losses in the transistor, see chapter

135 3 Hints for application dv dt - caused current overshoot + reverse-recovery-current i D (40 A / Div) Avalanche Breakdown v DS (50 V / Div) v DS (40 V / Div) i D (10 A / Div) a) P on (1 kw / Div) 0,1 µs / Div Turn-on P off (2 kw / Div) 0,2 µs / Div Turn-off v CE (200 V / Div) i C (20 A / Div) i C (20 A / Div) v CE (200 V / Div) P on (20 kw / Div) P off (20 kw / Div) b) 0,2 µs / Div Turn-on 0,2 µs / Div Turn-off Figure 3.2 Measured switching processes (hard turn-on and turn-off under ohmic-inductive load) a) Power-MOSFET module b) IGBT module For explanations on quality features of current and voltage characteristics please refer to the remarks on Figure 1.11 in chapter The actual limits to the switching frequency are set by the switching losses, because they are increasing proportionally to the frequency. Other terminations may be set by the transistor turn-on and turn-off delay times t d(on), t d(off), the reverse recovery times of the free-wheeling diodes, the driver output power which increases proportionally to the frequency and the minimum turn-on, turn-off or dead times necessary for driver, interlocking, measuring, protection and monitoring functions, see chapter If switching losses are to be shifted to passive networks (snubbers) or overvoltages are to be limited by snubbers, the recharge time of such networks required after low-loss switching has to be considered as deadtime, see chapters 3.6 and 3.8. Switching times of MOSFET and IGBT power modules are within the range of some 10 ns to some 100 ns. Especially when high operating voltages and hard switching processes are involved, the theoretically reachable maximum switching frequency cannot be utilized in most cases, since the maximum switching speed is often determined by - the turn-off speed, limited by the permissible switching overvoltage and 136

136 3 Hints for application - the turn-on speed, limited by the permissible peak current (load current + reverse recovery current of the free-wheeling diode depending on di/dt). Moreover, transistor dv/dt and di/dt values, which are prone to be very steep within the high power range, might cause electromagnetic interferences and problems due to dv/dt in certain loads (machines). Therefore, an optimized compromise between the requirements resulting from the application (e.g. frequency out of range of audibility), switching times/ losses, power dissipation and EMCfeatures has to be looked for when determining switching frequency and switching times. These are the standard values for switching frequencies with standard modules, optimal technical utilization provided: for hard switching: MOSFET-modules low-voltage up to 250 khz high-voltage up to 100 khz IGBT-modules 600 V up to 30 khz 1200 V up to 20 khz 1700 V up to 10 khz 3300 V up to 3 khz for soft switching: MOSFET-modules low-voltage up to 500 khz high-voltage up to 250 khz IGBT-modules up to 150 khz Higher switching frequencies can be realized with modules specially designed for fast switching. 3.2 Thermal behaviour Balance of power losses Single and total power losses Introductory remarks All explanations in chapter 3.2 refer to IGBT modules. All considerations and calculations are applicable to MOSFET modules in analogy, provided all designation indices corresponding to MOSFETs are exchanged. The following explanations are focused on hard switching converters connected to a DC-voltagelink. In power electronics, IGBTs as well as diodes are operated mainly as switches, taking on various static and dynamic states in cycles. In any of these states, one power dissipation or energy dissipation component is generated, which heats the semiconductor and adds to the total power dissipation of the switch. Therefore, the maximum junction temperature T j = 150 C (for silicon components) given by the manufacturer has to be obeyed at any time of operation of the converter when using power semiconductors. Figure 3.3 shows a survey of the possible single power dissipations during switch operation. 137

137 3 Hints for application Total Power Losses Static Losses Switching Losses Driving Losses On-state Losses Blocking Losses Turn-on Losses Turn-off Losses Figure 3.3 Single power losses of power module switches IGBT Because they are only contributing to a minor share of the total power dissipation, forward blocking losses and driver losses may usually be neglected. On-state power dissipations (P fw/t ) are dependent on: - load current (over output characteristic v CEsat = f (i C, v GE )), - junction temperature, - duty cycles. For given driver parameters, the turn-on and turn-off power dissipations (P on/t, P off/t ) are dependent on: - load current, - DC-link voltage, - junction temperature, - switching frequency. IGBT total power losses: P tot/t = P fw/t + P on/t + P off/t Free-wheeling diode: Because they are only contributing to a minor share of the total power dissipation, reverse blocking power dissipations may usually be neglected. Schottky diodes might be an exception due to their high-temperature blocking currents. Turn-on power dissipations are caused by the forward recovery process. As for fast diodes, this share of the losses may mostly be neglected as well. On-state power dissipations (P fw/d ) are dependent on: - load current (over forward characteristic v F = f (i F )), - junction temperature, - duty cycles. For given driver parameters of the IGBT commutating with the diode, turn-off power dissipations (P off/d ) are dependent on: - load current, - DC-link voltage, - junction temperature, - switching frequency. Total diode power losses: P tot/d = P fw/d + P off/d 138

138 3 Hints for application Hybrid power module with n IGBTs and m diodes Total module power losses: P tot/m = (n * P tot/t ) + (m * P tot/d ) Power losses of a step-down converter Figure 3.4 shows the circuit diagram of a step-down converter with characteristics generated under ohmic inductive load. Transistor Control v d D v T F i i C v L CE ON OFF v d i LH i LL t 1 v out T i L i t Lavg t i F v out i C t i F t E off/t E on/t E fw/d E fw/t E off/d Figure 3.4 Step-down converter under ohmic-inductive load During the steady state of the circuit, power dissipations at a certain operation point may be calculated as follows: IGBT Turn-on power dissipation: P on/t = f s * E on/t (v d, i LL, T j/t ) Turn-off power dissipation: P off/t = f s * E off/t (v d, i LH, T j/t ) Foward power dissipation: t 1 1 Pfw/T = i C(t) v T 0 CE (t) dt Neglecting the load current ripple will result in: P fw/t = i Lavg * v CEsat (i Lavg, T j/t ) * (t 1 /T) = i Lavg * v CEsat (i Lavg, T j/t ) * D T D T = transistor duty cycle i Lavg = average load current 139

139 3 Hints for application Free-wheeling diode Turn-off power dissipation: P off/d = f s * E off/d (v d, i LL, T j/d ) Forward power dissipation: P fw/t = 1 T T t1 v (t) i F F (t) dt Neglecting the load current ripple will result in: P fw/d = i Lavg * v F (i Lavg, T j/d ) * (1-D T ) = i Lavg * v F (i Lavg, T j/d ) * (D D ) D D = diode duty cycle The calculation of IGBT and diode forward power dissipation is based on an ideal duty cycle (neglecting the share the switching time contributes to the total cycle duration). Selected ratings for energy dissipations during switching as well as for the IGBT and diode forward voltage drop are indicated in the datasheets (see chapter 2) Power losses in pulsed voltage source inverters/rectifiers with sinusoidal currents Basic circuit: Figure 3.5 shows ideal characteristics of an inverter phase for a sinusoidal modulation according to the sinusoidal pulse-width modulation. 140

140 3 Hints for application i C1 i F1 V d /2 IGBT T1 Diode D1 V 1 i 1 V d /2 IGBT T2 Diode D2 i C2 i F2 v ref ; v h v ref (t) v h (t) t i 1 ; v 1 1/f S 1/fout v 1 (t) v 1(1) (t) i 1 (t) t i C1 ϕ 2 fout t fw/t1 t i F2 t fw/d2 t Figure 3.5 Converter phase with sinusoidal modulation according to sinusoidal pulse-width modulation In the sinusoidal pulse-width modulation the pulse pattern is generated by comparison of a reference voltage v ref to an auxiliary control voltage v h, whereby the fundamental frequency of the AC-parameters f out is determined by the reference voltage and the switching or pulse frequency of the switches f s by the auxiliary control voltage. The intersections of reference and auxiliary control voltage are the basis for commutation times in the converter phase. If vˆ ref vˆ h, this is called linear modulation mode of the inverter. The following explanations refer to the linear modulation mode. Furthermore, it is presupposed that the fundamental frequency of the AC-parameters is exceeded by the pulse frequency by far. Voltage utilization of the converter may be expressed by the degree of modulation m. It indicates the ratio between fundamental harmonics amplitude of the AC-voltage and 50 % of the DC-link voltage. In case of a pure sinusoidal reference voltage, the degree of linear modulation will be 0 m

141 3 Hints for application The phase shift between the fundamental harmonics of AC current and voltage is described by the angle ϕ. The current and voltage characteristics for IGBTs and diodes, which are time-shifted, will turn out to be identical due to the symmetrical structure of the inverter circuit. Therefore, it is enough to consider just one IGBT (here T1) and one diode (here D2) with reference to the calculation of power dissipation (the result is then multiplied by the corresponding number of IGBTs/ diodes integrated in the inverter). In contrast to the calculations under chapter duty cycle, load current and junction temperature are not constant under static operation, but vary depending on the fundamental frequency of the AC side (e.g. 50/60 Hz). This means that switching and forward power dissipations of IGBTs and diodes are subject to temporal variability and require a extensive calculation of system power losses. Consequently, exact results cannot be produced with greatly simplified calculation procedures. Two calculation possibilities are to be introduced in the following. 1. Approximation of component characteristics by polynominal equations (detailed in [194]) In this calculation procedure, the dependencies of transistor and diode forward on-state voltages on load current and junction temperature as well as of transistor and diode switching energy dissipations on load current, DC-link voltage and junction temperature are approximated by polynominal equations of the type y = f(x) = A + Bx + Cx². For this, the available component parameters have to be taken from the datasheets or determined by simple pulse converter test circuits, which, however, requires considerable effort. The following set-up of the polynominal equations may be done by using conventional curvefitting software. The coefficients A-C of a following equations comprise the determined dependencies of the parameters. Accordingly, equations may be set up to calculate the average energy dissipation. The following simplifications have been presupposed: - transistor and diode switching times are neglected, - temporally constant junction temperatures (permissible if f out =..50 Hz), - linear modulation of the converter, - neglecting the switching frequency ripple of the AC-current. Forward power dissipation Including forward characteristic approximation of IGBT and diode according to y = A + Bx and considering the temperature coefficients of the forward on-state voltages, results in the following equations: IGBT T1: 1 t dead A fw/t Bfw/T 2 A fw/t Bfw/T 2 P fw/t1 = - î1 + î1 + m cosϕ î1 + î1 (3.1) 2 TS π 4 8 3π 142

142 3 Hints for application Diode D2: 1 t dead A fw/d Bfw/D 2 A fw/d Bfw/D 2 P fw/d2 = + î1 + î1 m cosϕ î1 + î1 (3.2) 2 TS π 4 8 3π Figure 3.6 explains the influence of switching deadtime t dead on forward energy dissipations (t dead determines the effective duty cycles) with the example of a 1200 V/50 A-IGBT-module. Especially if high pulse frequencies are involved, the arm-interlock-deadtime t dead has to be considered in the calculation of the average power forward dissipation. P fwreal -P fwideal P fwreal [%] IGBT Diode ,02 0,04 0,06 t dead /T S 0,08 Figure 3.6 Forward power dissipations versus switching deadtimes (i 1eff = 25 A; m = 0.8; cos ϕ = 0.8) Switching losses The following equations result from the approximation of the dependency of switching losses on the current according to y = Bx + Cx² in consideration of temperature and voltage coefficients of the switching losses: IGBT T1: Diode D2: Bon+ off/t Con+ off/t P on+ off/t1 = f s î1 + î1 π 4 (3.3) Boff/D Coff/D P off/d1 = f s î1 + î1 π 4 (3.4) Figure 3.7 shows one result of this calculation method with the example of a 1200 V/50 A- IGBT-dual module in an inverter. 143

143 3 Hints for application P fw [W] m * cosφ= IGBT Diode I RMS [A] P sw [W] V d =700 V 500 V IGBT Diode I RMS [A] Figure 3.7 a) Forward power dissipations (t dead = 5 µs, T j = 125 C) b) Switching losses (f s = 10 khz, T j = 125 C) The product of m * cos ϕ determines how the total power dissipation is divided up on IGBT and diode (see also chapter ). m * cos ϕ = 0.64 m * cos ϕ = 0.1 m * cos ϕ = represents an operating point in inverter mode (motor load) represents an operating point in motor starting mode represents an operating point in rectifier mode The procedure for calculation of IGBT and diode power dissipation described above shows very exact results, however the determination of parameters requires great efforts. Therefore, the following greatly simplified calculation mode to produce a rough calculation can be recommended. 2. Simplified, linear approach [274] Assumptions: - transistor and diode switching times as well as switching interlocking times are neglected, - temporally constant junction temperatures (permissible if f out =..50 Hz.), 144

144 3 Hints for application - linear modulation of the converter, - neglecting switching frequency ripple of the AC current (sinusoidal current), - f s >> f out. Forward on-state power dissipation: IGBT T1: If the output characteristics are linearized with y = A + Bx, the temporal dependency of the saturation voltage v CEsat may be expressed as follows: vcesat (t) = VCE0 + rce i C (t) = VCE0 + rce î1 sin ωt with: V CE0 = threshold voltage of the output characteristic with i C = 0 r CE = on-state resistance of the IGBT (rate of rise of the output characteristic) Considering the sinusoidal dependency of duty cycles versus time, the forward power dissipation of IGBT T1 may be calculated according to 1 VCE0 rce 2 VCE0 rce 2 P fw/t1 = î1 + î1 + m cosϕ î1 + î1 (3.5) 2 π 4 8 3π Diode D2: If the output characteristics are linearized with y = A + Bx, the temporal dependency of the foward on-state voltage v F may be expressed as follows: v F (t) = VF0 + rf i F (t) = VF0 + rf î1 sin ωt with: V F0 = threshold voltage of the forward characteristic with i F = 0 r F = on-state resistance of the diode (rate of rise of the output characteristic) Considering the sinusoidal dependency of duty cycles versus time, the forward power dissipation of diode D2 may be calculated according to 1 VF0 rf 2 VF0 rf 2 P fw/d2 = î1 + î1 m cosϕ î1 + î1 (3.6) 2 π 4 8 3π Switching losses IGBT T1: Provided that the energy dissipation during switching is linearly dependent on the collector current, the total power dissipation of an IGBT may be calculated with [ E on/t ( î1 ) E off/t ( î1 )] 1 P on+ off/t1 = f s + π Equation 3.7 is actually based on the assumption that the IGBT switching losses generated during one sine half-wave are about identical to the switching losses generated if an equivalent direct current is applied, which would correspond to the average value of the sine half-wave. IGBT switching losses are approximately convertible linearly to other DC-link voltages. (3.7) 145

145 3 Hints for application Diode D2: Provided that the energy dissipation during turn-off is linearly dependent on the diode current, the total power dissipation of a diode may be calculated with: P off/d2 1 = f π s E off/d ( î1 ) This equation is also based on the assumption that the diode switching losses generated during one sine half-wave are about identical to the switching losses generated, if an equivalent direct current is applied, which would correspond to the average value of the sine half-wave. Diode switching losses are approximately convertible linearly to other DC-link voltages. The results rendered by the explained simplified calculation process are sufficient for estimating the expected power dissipation during converter operation mode in practice. The decisive advantage that is offered to the user is that all necessary parameters can be taken directly from the corresponding module datasheets Calculation of the junction temperature General hints The calculation of junction temperatures is based on the simplified thermal equivalent block diagram of Figure 3.8. The designations used for transistor and diode are related to those in Figure 3.5. The equivalent block diagram is restricted to one transistor and its commutating diode in a power module, i.e. to those two components through which the load current is conducted during one sine half-wave (here T1 and D2). The equivalent block diagram for T2 and D1 can be drawn up in analogy. (3.8) 146

146 3 Hints for application T j/d2 T j/t1 Z thjc/t1 Z thjc/d2 P tot/d2 P tot/t1 T coup/d1 T coup/t2 T C Z thch T h Z thha T a T a Z thx (t) [ 1- exp( - t/t )] = Rthxν thxν ν ν = 4 R thx1 R thx4 τ thx1 τ thx4 R thx1 R thx4 Figure 3.8 Simplified thermal equivalent block diagram of IGBT and free-wheeling diode in a power module Explanation of designations: P tot Total power dissipation within transistor and free-wheeling diode T j Junction temperatures Z thjc Thermal impedance from junction to module case T c Case temperature Z thch Thermal impedance from module case to heatsink T h Heatsink temperature Z thha Thermal impedance from heatsink to ambient temperature (see chapter 3.3) T a Ambient temperature Transistors and inverse diodes are soldered on a common copper plate in a power module. Therefore, the elements T coup/d1 and T coup/t2 stand for the thermal coupling of T1 and D2 with their corresponding antiparalleled elements D1 and T2, which becomes effective especially at low fundamental frequencies. Exact determination of this coupling effect is subject to extensive thermal simulation of the module structure [194]. Therefore, this is usually neglected in simplified calculation processes. 147

147 3 Hints for application If transistor and free-wheeling diode are integrated in the same module, a common heatsink and case temperature may be presumed for simplification. If this simplifaction is no more permissible for high-power single switches, the values for Z thch have to be entered separately for transistor and diode. Efficient thermal parameters between case and heatsink are also dependent on the following factors: quality of the module base plate, contact pressure between module and heatsink, thermal paste, surface quality of the heatsink. Please pay attention to the data and recommendations given by the manufacturers (see chapter ). For computer-aided simulation of the temporal behaviour of the junction temperature thermal impedances may be divided up into a chain circuit of R-C components (see Figure 3.8). As a special service to the customer, SEMIKRON offers parameters of 4-6 R-C components for determining the Z thjc of power modules in the databook. Parameters of the cooling systems are also available on request (see chapter 3.3.6). Following the equivalent block diagram of Figure 3.8, the characteristics of the junction temperatures of transistor and diode versus time can be calculated according to the following equations based on the case temperature: n j/t1 (t) = TC + Tcoup/D1 + PT1(t) R thν/t1 t/ ν= 1 [ 1- exp (- τ )] T (3.9) n j/d2 (t) = TC + Tcoup/T2 + PD2 (t) R thν/d2 t/ ν= 1 thν/t1 [ 1- exp (- τ )] T (3.10) thν/d2 Often only the average junction temperatures and their ripples are decisive for the thermal layout of converters. Exemplary calculations for typical loads are explained in the following chapters Junction temperature during short-time operation Short-time operation allows for higher currents to be conducted in the power semiconductors than indicated in the datasheets for permanent operation. However, the highest junction temperature generated under the given conditions should not exceed the maximum rating of T j = 150 C. The junction temperature can be calculated using formulas 3.9 and 3.10 in chapter

148 3 Hints for application Examples: Single power dissipation pulse P T j T j0 T jmax t 0 t 1 0 t 1 t Figure 3.9 Power dissipation and junction temperature of single power dissipation pulse versus time Maximum value of the junction temperature alteration at t 1 : n jmax = Tj(t1) = P R thν 1/ ν= 1 [ 1- exp (- t τ )] T (3.11) thν Junction temperature during cooling periode: n n 1 thν thν thν 1 / ν= 1 ν= 1 ( t > t ) = P R [ 1- exp (- t/ τ )]- P R [ 1- exp (- ( t - t ) τ )] T (3.12) These formulas are based on a fixed case reference temperature. Single sequence of m power dissipation pulses thν P T j P 2 P 1 P 3 T j1 T j2 T j3 T j0 0 t 0 t 1 t 2 t 3 Figure 3.10 Power dissipation and junction temperature at single sequence of m power dissipation pulses versus time Junction temperature alteration at t 1 : n j1 = P1 R thν 1/ ν= 1 [ 1- exp (- t τ )] T (3.13) thν 149

149 3 Hints for application Junction temperature alteration at t 2 : n n j2 = P1 R thν 2 thν 2 1 thν 2 1 / ν= 1 ν= 1 [ 1- exp (- t / τ )] + ( P P ) R [ 1- exp ( ( t - t ) τ )] T (3.14) Junction temperature alteration at t m : m n ( Pµ Pµ -1 ) R thν [ 1- exp ( ( t m - t µ -1 ) τ thν )] T (3.15) j (t m ) = / µ= 1 ν= 1 These formulas are based on a fixed case reference temperature Junction temperature under pulse operation The transistor and diode Z thjc -characteristics under periodic pulse conditions indicated in the datasheets may be used for calculation of the average and maximum junction temperature under power dissipation load periodically repeated along with the pulse frequency. Figure 3.11 shows such a set of curves for the IGBT and the diode of a SKM100GB123D module and a typical current and junction temperature characteristic in the transistor under pulse operation. thν a) T, i j b) T jmax T javg T jmin i D = t T s c) t T s t Figure 3.11 Transient thermal impedance Z thjc of IGBT (a) and diode (b) of a SKM100GB123D module c) Current and temperature characteristic 150

150 3 Hints for application The average junction temperature T javg results from multiplication of the thermal resistance R thjc with the average power dissipation P totavg. The latter is calculated by averaging the energy dissipation per pulse over the whole pulse or switching duration T s. P totavg = f s * (E on + E off + E fw ) T javg = T c + P totavg * R thjc The maximum junction temperature T jmax results from multiplication of Z thjc under pulse operation with the maximum power dissipation P totmax. The latter is calculated by averaging the energy dissipation per pulse over the on-state time t of transistor or diode, respectively, within the pulse duration T s. P totmax = (E on + E off + E fw )/t T jmax = T c + P totmax * Z thjc Examples with a SKM100GB123D IGBT: Example 1: f s = 10 khz; T s = 100 µs; D T = 0.2; t = 20 µs T c = 80 C; E on + E off + E fw = 25 mj R thjc = 0.2 C/W, Z thjc = 0.04 C/W (see Figure 3.11a) Consequently: P totavg = 250 W; P totmax = 1250 W T javg = 80 C W * 0.2 C/W = 130 C T jmax = 80 C W * 0.04 C/W = 130 C Example 2: f s = 2 khz; T s = 500 µs; D T = 0.2; t = 100 µs T c = 80 C; E on + E off + E fw = 25 mj R thjc = 0.2 C/W, Z thjc = C/W (see Figure 3.11a) Consequently: P totavg = 50 W; P totmax = 250 W T javg = 80 C + 50 W * 0.2 C/W = 90 C T jmax = 80 C W * C/W = 90.5 C Example 3: f s = 2 khz; T s = 500 µs; D T = 0.2; t = 100 µs T c = 80 C; E on + E off + E fw = 125 mj R thjc = 0.2 C/W, Z thjc = C/W (see Figure 3.11a) Consequently: P totavg = 250 W; P totmax = 1250 W T javg = 80 C W * 0.2 C/W = 130 C T jmax = 80 C W * C/W = C Example 4: f s = 50 Hz; T s = 20 ms; D T = 0.5; t = 10 ms T c = 80 C; E on + E off + E fw = 5 J R thjc = 0.2 C/W, Z thjc = 0.12 C/W (see Figure 3.11a) Consequently: P totavg = 250 W; P totmax = 500 W T javg = 80 C W * 0.2 C/W = 130 C T jmax = 80 C W * 0.12 C/W = 140 C 151

151 3 Hints for application Example 1 is calculated based on a typical IGBT pulse frequency of 10 khz. The result shows that there is no deviation between the average and maximum values of the junction temperature due to the low thermal impedances at high frequencies. The pulse frequency in example 2 and 3 had been reduced to 2 khz, however keeping constant values for the amount of energy dissipation in example 2 and for the average and maximum total power dissipation in example 3. Both examples show a deviation between average and maximum junction temperature. Simply expressed, it may be presumed that a calculation based on average power dissipation and static thermal resistance is sufficient for pulse frequencies above about 3 khz. Example 4 shows the drastic difference between average and maximum junction temperature at very low pulse frequencies Junction temperature at fundamental harmonics frequency Calculation of the junction temperature determined by the fundamental frequency of the converter output current is only efficient, when it is computer-aided. The thermal system as well as the electrical system per pulse duration have to be calculated in detail in order to integrate the IGBT and diode junction temperature over a sine half-wave. Figure 3.12 shows a principal calculation scheme which had been elaborated in source [194]. Thermal Model Simulation of the Junction Temperature Thermal Parameters T (t) j Electrical Model P(t) Calculation of the Temperature Coefficients Calculation of the Losses per Switching Cycle Converter Parameters Figure 3.12 Principal calculation of the junction temperature in converters with sinusoidal output currents [194] The thermal model mainly corresponds to Figure 3.8 simulating the thermal impedances by means of RC-elements. Switching losses per pulse may be calculated based on stored characteristics, if the current converter parameters such as DC-link voltage and instantaneous load current are given. The 152

152 3 Hints for application instantaneous junction temperature is entered into the calculation via the temperature coefficients. Figure 3.13 shows the power dissipation time characteristic and the average power dissipation in an IGBT as well as the resulting junction temperature characteristics for different basic output frequencies as the result of a simulation according to [194]. T j/t [ C] f ourt ->0Hz 5Hz 50Hz 2π ϑ [rad] T javg 4π P tot/t [W] π ϑ [rad] P totavg 4π Figure 3.13 Simulated junction temperature and power dissipation characteristics of a 1200V/50A-IGBT under inverter operation for different fundamental output frequencies; [194] v d = 540 V; i 1RMS = 25 A, f s = 8 khz; cos ϕ = 0.8; m = 0.8; T h = 50 C In this example, the maximum junction temperature exceeds the average value by just about 4-5 K at a frequency of 50 Hz. For low frequencies the average junction temperature is no longer permitted to determine the thermal layout of the system because of its clearly increased maximum value. Consequently, the permissible output current RMS-Valuefor a defined power module will decrease at a given heatsink temperature and switching frequency. Corresponding performance characteristics (e.g. for SKiiPPACK) are available by SEMIKRON on request. Moreover, Figure 3.13 shows that no temperature ripples with righ pulse frequency arise. This is also confirmed by the calculations in chapter A very particular special case with regards to the thermal stress of power modules is the voltageand frequency-controlled starting procedure of a three-phase motor drive supplied by an inverter. Figure 3.14 shows a related simulation example. I 1RMS [A] 40 f out [Hz] 50 m , , , , ,5 1 1,5 t [s] ,5 1 1,5t [s]

153 3 Hints for application Tj [ C] IGBT Diode ,5 1 t [s] 1,5 Figure 3.14 Start-up of a three-phase motor drive (parameters as in Figure 3.13), [194] Evaluation of temperature characteristics with regards to module life Power dissipation alterations below a repetition frequency of about 3 khz will not be smoothed by the transient thermal impedance of the chips any longer and will lead to temperature fluctuations in the module (see chapter 3.2.2). As already mentioned in chapter , all internal connections of power modules are subject to wear and tear caused by temperature fluctuations. This fatigue of material is caused by thermal stress due to the different expansion coefficients of the connected materials. Therefore, it is important for thermal dimensioning to check, whether the chip temperature fluctuations generated during periodic power cycling (pulse frequency, fundamental frequency, power cycle) are so intensive that, in the worst case, the required number of cycles may not be reached. In this case, not the maximum chip temperature T jmax, but the temperature difference T j = T jmax - T jmin during given power cycles is considered as limit value for power losses of the module. The correlation between the possible number of power cycles n and the temperature cycling amplitude T j is subject to the influence of many parameters. Corresponding measurements require a lot of time and effort, see chapter 2.7 and [231]. In tests with active power cycles the lifetime of a power module depends not only on the temperature difference T j but also on the average (medium) temperature T m in the test procedure. This was confirmed clearly by the results of LESIT-research project [303]. LESIT results of power cycling lifetime tests with power modules by different manufacturers are shown in Figure The parameter adjustment was done by SEMIKRON. These results represent the state-of-the-art in Meanwhile, the lifetime was increased by improved solder connections and optimized wire bond connections. So, cycles at T=100 C and T j,min =40 C are achieved. Presently, updated characteristics for SEMIKRON power modules are in preparation. 154

154 3 Hints for application LESIT results for power cycling lifetime number of cycles N f = A T α Ea exp kb T m delta T [ C] Tj,max=const.=120 C Tj,medium=const.=80 C Tj,min=const.=40 C Figure 3.15 LESIT results for power cycling lifetime 3.3 Cooling of power modules Cooling devices, coolants and cooling methods The heat potential due to forward, switching and blocking losses in power modules has to be dissipated by means of heatsinks, which provide an expanded surface for convection and radiation, spreading the heat flow as well as reducing the intensity of transient thermal processes. Due to their isolation, all power modules of one system are mounted on to one common heatsink which may also serve as an element of the construction (case, chassis etc.). Heat dissipation in a heatsink works on the principle that the heat is dissipated to the coolant either by direct heat transmission or via a heat carrier. Heat carriers may be air, water or (more rarely) isolation oil, which is circulated by the effect of gravity or by fans or pumps. Air in natural and forced motion or coolant mixtures on the basis of water may serve as coolants. In the following we would like to emphasise only natural (free convection) and forced air cooling and water cooling systems with one coolant circuit each, since more sophisticated cooling methods, such as heatpipes or boiling cooling are normally extremely applicationspecific and oil cooling is not very commonly used with power modules. 155

155 3 Hints for application The heatsink material has to be constructed for optimal heat spreading (high heat transfer coefficient λ), with acceptable material and handling costs. Therefore, aluminum is often preferred (λ = 247 W/K * m for pure Al), in special cases copper is also used (λ = 398 W/K * m). The dependence of heat spreading on the production process and the alloy used is remarkable; practical heatsinks show λ-values between 150 W/K * m (Al-die cast alloy) and 220 W/K * m (AlMgSi-extruded material). Heat spreading has a considerable influence on the thermal efficiency of the heatsink. Therefore, optimized dimensioning of root thickness, number of fins, fin height and fin thickness is of importance: - The root of a heatsink is the unfinned part of the mounting surface for the power modules, where the temperature gradient to the module base plate is relatively low and where the heat is spread. - The fins of an air heatsink are used for dissipating the majority of the heat to the environment by radiation and convection. In water heatsinks this task is fulfilled by more or less structured water channels. R thha = T/P tot = 1/( α * A) results from Q = α * A * T = P tot (Q: dissipated heat quantity, α: heat transfer coefficient, A: heat transfer area, T: temperature difference to the environment, P tot : power dissipation, R thha : heat transfer resistance of the heatsink) It is recommended that a high number of fins is provided in order to increase the area of dissipation. But it has to be guaranteed that the flow conditions are set in a way which will not decrease α greatly. Consequent to this conclusion, the different optimization criteria for heatsinks with natural and forced air cooling may be deducted. The heatsink is heated more evenly when the power dissipation increases, i.e. the efficient heat exchange surfaces are enlarged; in Figure 3.16 the heat exchange surface is further extended by an increased heatsink length Thermal model of the cooling device When explaining the thermal characteristics of power modules in chapter , the heatsink in the thermal equivalent block diagram had been described by only one RC-element (R thha, Z thha ). However, with an increase of power dissipation at t = 0 from P = 0 to P = P m, the characteristic of the transient thermal impedance of the heatsink Z thha versus time t is split up into several time constants as shown in Figure 3.16 with an example. The total thermal impedance characteristic Z thja (t) of the assembly may be determined by graphic addition of the thermal impedance characteristics of the power module and the heat transition to the heatsink. The Z th (t)-curves may be plotted as the sum of ν exponential functions using the following equations: ν thν [ 1- exp (- τ )] T(t) = Pm R t/ and Z thha (t) = T(t)/Pm thν 156

156 3 Hints for application i.e. Z thha thν [ 1- exp (-t/ τ ] (t) = R ) thν The number of ν and the R thν - and τ ν -values are chosen so that a sufficient approximation of the characteristic can be produced without applying complicated calculation procedures, independent of the physical structure. One iteration method is described, for example, in source [266]. The ratings for simulations indicated by SEMIKRON and mentioned briefly in the following chapters are based on a 4-time-constants-model (ν = 4) Natural air cooling (free convection) Natural air cooling is applied in low power range applications up to 50 W as well as in high power range applications, if the use of fans is not possible or if extremely large cooling surfaces are available in the device. Since with free convection, the thermal transient resistance of the heatsinks usually exceeds the internal thermal resistance of the power modules, the temperature difference between chip (125 C) and cooling air (45 C) drops mainly over the heatsink. Near the modules, the heatsink temperature is usually higher than with forced air cooling, for example C. Because power losses are usually low with natural air cooling, heatsink root and fins do not have to be very thick, since heat conductivity has only a minor influence on the thermal features. The fin distances have to be selected sufficiently to obtain a favourable ratio between air uplift (drop of temperature / density) and air friction. Black coating of the heatsink will improve the radiation characteristics and, thus, the R thha -value by about 15 % at a temperature difference of 50 K between mounting surface and atmosphere [266]. The surface finish, however, does not impair heat transfer between module base plate and heatsink Forced air cooling In contrast to natural air cooling, forced air cooling can reduce the thermal heatsink resistance to 1/5...1/15. Figure 3.16 compares the Z thha (t) characteristics of natural and forced air cooling up to the final R thha -value with the example of different SEMIKRON P16/...-heatsinks. 157

157 3 Hints for application a) b) Figure 3.16 Z thha (t)-characteristics for different P16/...-heatsinks a) Free convection b) Forced air cooling Compared to free convection, α is much higher with forced air cooling. The rated surface temperature of forced air-cooled heatsinks should not exceed C at a supply air temperature of 35 C (condition for datasheet ratings). The heat conductivity of the heatsink has tremendous influence on the cooling effect, which requires a thick root and a maximum number of fins. Because convection is mainly responsible for the dissipation of heat, black coating of the heatsink will have almost no effects with forced air cooling. R thha is mainly determined by the rate of air flow per time V air /t, depending on the average cooling air velocity v air and the transfer cross section A: V air /t = v air * A Instead of the assumed laminar air flow, air whirlings on the fin surfaces will effect turbulent flow conditions between the fins, which will improve heat dissipation to the atmosphere, provided the fin surfaces are set out accordingly. The transfer cross section of the heatsink will be reduced by increased number of fins and fin width as well as by increased heatsink length (fin length L) and the cooling air-pressure drop p will rise. Consequently, heat dissipation is dependent on the characteristics of the fan, which are described in the fan characteristic p = f(v air /t) (Figure 3.17). 158

158 3 Hints for application 4 mbar FANS.XLS-2 SKF16A SKF16B SKF 16 B 2 SKF 16 A 1 p m 3 /h Figure 3.17 Fan characteristic p = f(v air /t) for SEMIKRON P16/... fans The thermal transient resistance of the heatsink assembly R thha depends on the rate of air flow shown in Figure 3.19, which may be determined by combining fan and pressure drop characteristics p = f(v air /t, L) or p = f(v air, L) of the heatsink. p [Pa] P16/...F with Fan A = 7368 mm 2 ; c=0,0377 x V air [m/s] Fan P16/400F P16/300F P16/200F Meas. Points V air [m 3 /h] Figure 3.18 Air flow of a P16/... heatsink profile at various heatsink length Apart from the air flow, R thha is dependent on distribution and position of heat sources (power modules) on the heatsink. Figure 3.19 explains these relationships with the example of a selected SKiiP-assembly. 159

159 3 Hints for application Figure 3.19 Thermal resistance of the heatsink R thha of a SKiiP-assembly versus air flow and position of the SKiiPPACK on the heatsink Figure 3.20 shows the standard assembly of a 3-fold SKiiPPACK on an air-cooled heatsink P16/280F. Figure 3.20 SKiiPPACK 3 standard assembly with SKF 16B fan To determine optimized conditions for forced air cooled heatsink profiles, heat conduction and convection can also be integrated by the fin height layout, which will result in the following formula on condition of some simplifications: 160

160 3 Hints for application R = 1 thha 1 1 n α U λ A 1+ exp 2κh 1 + exp2κh with κ = α U λ A (α: heat-transfer coefficient, U: fin circumference, λ: coefficient of thermal conductivity of heatsink, A: cross section of fins, h: fin height) Often, several heatsinks have to be cooled by only one fan, for which they are either arranged in parallel (heatsinks positioned side by side) or in series (heatsinks behind each other in direction of air flow). With regard to thermal stacking, which is preferred, for example, in three-phase inverter applications with standard GB-circuit SKiiPPACKs (halfbridge modules), special attention should be paid to the fact that the air is preheated for 2 of the 3 SKiiPPACKs, which has to be taken into consideration when determining the thermal layout. At an air flow rate of 300 m 3 /h, about 10 K temperature difference between supply and exhaust air is presupposed as a standard value per kw dissipated power. Thermal details are given in chapter Water cooling Water cooling of power modules can be used for special high power inverters (MW-range) as well as for small power devices, which already provide for a water circuit due to their working principles (e.g. car drives, galvanic plants, inductive heating). Mostly, the admission temperature of the coolant values is up to C when the heat of the coolant is directly dissipated to the atmosphere; in industrial plants with active heat exchangers the temperature is about C. The temperature difference between heatsink surface and coolant which is lower than with air cooling may be utilized in two ways: - increased energy exchange at a high dynamic T j of chip temperature per cycle (limits for module life see chapter 3.2.3) or - low chip temperature, long module life. Due to its capability for high heat retention (thermal capacity c p = kj/kg *K) water is principally preferred to oil or glycol for the dissipation of heat. Figure 3.21 shows a SEMIKRON standard assembly with a 3-fold SKiiPPACK on a watercooled base plate. 161

161 3 Hints for application ~ ~ ~ 11 Pin 2 Pin SKiiP U.S. Patent No:... xxxxxxxxxxxxxxx U.S. Patent No:... SK.No:... DATE:... Ord.No:... output Pin 1 Pin Figure 3.21 SKiiPPACK 3 standard assembly with water-cooled base plate Due to the corrosive effect of water and the mostly required frost-resistance, open or closed circuit with pure water are hardly used. By adding glycol, for example, the heat-retainability of the coolant will be diminished (e.g. 3.4 kj/(kg * K) at an addition of 50 % glycol and a coolant temperature of 40 C). As viscosity and specific gravity of the coolant will rise, the thermal resistance from heatsink to coolant R thhw will considerably increase together with the share of glycol. Compared to pure water, a 50 % addition of glycol will effect an increase of R thhw by approximately % and again by another %, if the glycol share is increased up to 90 %. To guarantee for corrosion protection, SEMIKRON water-cooled aluminum heatsinks contain a minimum share of glycol of 10 %. The hardness of the cooling water may not exceed a degree of 6. At least for coolant temperatures higher than 60 C we recommend to use a closed cooling circuit. Thermal stacking of heatsinks with power modules or SKiiPPACKs is also done in correlation with water cooling. A difference of about 1.7 K per kw dissipated power between inlet and outlet temperature of the coolant can be taken as a standard value for the preheating per heatsink (SEMIKRON water-cooled heatsinks for SKiiPPACKs) for a 50/50 % water-glycol-mixture at a coolant flow of 10 l/min. For detailed information on SKiiPPACKs on water-cooled heatsinks please see chapter Heatsink ratings for SKiiPPACKs on standard heatsinks Forced air cooling The following table contains the characteristics R ν and τ ν for thermal calculation according to the 4-time-constants-model for SKiiPPACKs on standard heatsink P16 with fan SKF 16B (GD 133-2k-40105). R thsa tot : stationary thermal resistance as a result of the temperature difference between temperature sensor (T s ) and supply air (T a ), with reference to the total power dissipation P tot of the assembly R thsa = R tot Z thsa tot : 4 ν= 1 ν transient thermal impedance as a result of the temperature difference between temperature sensor (T s ) and supply air (T a ),with reference to the total power dissipation P tot of the assembly 162

162 3 Hints for application Z thsa tot = 4 ν= 1 R [ 1- exp (-t/ ] ν τ ν thermal characteristics (4-constants-model) R 1 K/W R 2 K/W R 3 K/W R 4 K/W ΣR K/W τ 1 s τ 2 s τ 3 s τ 4 s 2-fold SKiiPPACK (V air /t = 310 m 3 /h) fold SKiiPPACK (V air /t = 305m 3 /h) fold SKiiPPACK (V air /t = 300m 3 /h) In the case of thermal stacking of SKiiPPACKs, the reduction of air flow resulting from the increased pressure drop and pre-heating of the backward SKiiPACKs by the cooling air passing the front SKiiPPACKs has to be considered in the calculations. Figure 3.22 explains the principle of thermal stacking: FAN SKiiP FAN FAN SKiiP SKiiP SKiiP SKiiP SKiiP P tot1 P tot1 P tot2 P tot1 P tot2 P tot3 Figure 3.22 Thermal stacking of SKiiPPACKs with forced air cooling Pre-heating is determined by total power dissipation of the SKiiPPACKs P totn, stationary thermal resistance R thaa and transient thermal impedance Z thaa (resistance R thaa /time constant τ aa ) between two adjacent heatsinks, see Figure The following formulas are valid for determining the transient thermal impedances Z thsatotn of every single SKiiPPACK: SKiiPPACK no. 1 Z 4 thsa tot1 = R ν τ ν ) ν= 1 SKiiPPACK no. 2 4 [ 1- exp (-t/ ] [ 1- exp (-t/ τ )] + ( P /P ) R [ 1- exp (-t/ τ )] Z thsa tot2 = R ν ν tot1 tot2 thaa1 2 aa1 2 ν= 1 163

163 3 Hints for application SKiiPPACK no. 3 4 [ 1- exp (-t/ τ )] + [( P + P )/P ] R [ 1- exp (-t/ τ )] Z thsa tot3 = R ν ν tot1 tot2 tot3 thaa2-3 aa2 3 ν= Liquid cooling The following table contains the characteristics R ν and τ ν for thermal calculation according to the 4-time-constants-model for SKiiPPACKs on a standard water-cooled heatsink S with mutual water inlet/outlet, 50/50 % water-glycol-mixture at a coolant temperature of 50 C. Since the temperature T s of the internal temperature sensor of the SKiiP is also available here as a reference point for the heatsink temperature T h, the following definitions are valid: R thsw tot : stationary thermal resistance as a result of the temperature difference between temperature sensor (T s ) and coolant (T w ), with reference to the total power dissipation P tot of the assembly. R thsw = R tot Z thsw tot : Z 4 ν= 1 ν transient thermal impedance as a result of the temperature difference between temperature sensor (T s ) and coolant (T w ),with reference to the total power dissipation P tot of the assembly. 4 thsw tot = R ν τ ν ) ν= 1 [ 1- exp (-t/ ] Coolant by-pass l/min R 1 K/W thermal characteristics (4-constants-model) R 2 K/W R 3 K/W R 4 K/W ΣR K/W τ 1 s τ 2 s τ 3 s τ 4 s 2-fold SKiiPPACK fold SKiiPPACK

164 3 Hints for application 4-fold SKiiPPACK Calculation of thermal stacking is basically made the same way as with air cooling. 3.4 Power design MOSFET, IGBT or SKiiP power circuits are designed in printed circuit board technology, or by means of cables or massive copper or aluminum bars, depending on the currents and voltages to be switched. Apart from the general specifications to be met, for example with regards to creepage and striking distances or current density, the short switching times within the nano to microsecond range demand a sophisticated power design, which also lives up to the requirements of highfrequencies Parasitic inductances and capacitances To analyse the effects of parasitic inductances and capacitances of converters, it will be sufficient to examine one commutation circuit. Figure 3.23 shows the commutation circuit of an IGBT-inverter with parasitic elements, consisting of DC-link voltage v d (corresponds to commutation voltage v K ) and two IGBT switches with driver and inverse diodes. Commutation voltage is impressed by the DC-link capacitance C d. The impressed current i L flows out of the commutation circuit. 165

165 3 Hints for application i K L 11 C 11 L 61 L 71 Driver ± V Dr L 21 T1 D1 R Gon R Goff C 31 C 41 C 21 L 31 E`1 C d V d (V K ) L 41 L 51 i L E 1 C 12 L 62 L 72 Driver ± V Dr L 22 T2 D2 R Gon R Goff C 32 C 42 C 22 L 32 E`2 L 42 L 52 L 12 E 2 Figure 3.23 Commutation circuit with parasitic elements The effects of parasitic elements / counter-measures Total commutation inductance In the commutation circuit with T1 and D2, the amount of L 11, L 61, L 31, L 41, L 72, L 52 and L 12 is effective as total commutation inductance. In analogy, the amount of L 11, L 71, L 51, L 62, L 32, L 42 and L 12 is effective in the commutation circuit with D1 and T2. During active turn-on of T1 or T2, respectively, the total commutation inductance becomes effective as turn-on relief, which will reduce turn-on power dissipation in T1 or T2 (see chapter 3.8). However, during active turn-off of T1 and T2 as well as during reverse-recovery-di/dt of D1 and D2, switching overvoltages are generated in the transistors and diodes due to high di/dt caused by the commutation inductances. This will increase turn-off power dissipation and voltage stress of the power semiconductors. This effect is especially critical with regards to short-circuits and overload (see chapter 3.6). Moreover, together with parasitic capacitances unwelcome high frequency oscillations may be generated. Therefore, it is of major importance to minimize inductances in the commutation circuit of hardswitching converters. Except for L 11 and L 12, all inductances are generated in the modules, which may not be influenced by the user. In this respect, it is up to the manufacturers of power 166

166 3 Hints for application modules, to keep on working on the minimization of internal inductances by improving module assembly technologies (see chapter 1.4). SEMIKRON datasheets indicate the internal inductances becoming effective at the module output terminals (Example: SKM100GB123D: L CE = max. 30 nh). In the case of single switch modules (1 IGBT/MOSFET + 1 inverse diode), the connection of both modules has to be made as low-inductive as possible in an converter phase. Low-inductance DC-link power busbars are of special importance. This goes for the connection busbars of the capacitor battery itself as well as for connection of the power modules to the DClink. In this respect, laminated busbar systems (tightly paralleled plate systems) adapted to the specific inverter layout have gained general acceptance in practice, achieving busbar inductances up to nh. Some examples of this are shown in Figure The effects of the remaining inductances L 11 +L 12 on the power semiconductors can still be reduced by connecting C-, RC- or RCD-circuits directly to the DC-link terminals of the power modules. In most cases, a simple C-circuit with film capacitors within the range of µf is connected. Inductances of emitter or source The elements L 31 or L 32 of the emitter/ source inductances are effective in the power circuit as well as in the driver circuit of the transistors. Due to the fast di/dt of the transistor current, voltages will be induced which will have the effect of inverse feedback in the driver circuit (emitter/source inverse feedback). This, however, will decelerate the charging process of the gate-emitter-capacitance during turn-on and the discharging of the gate-emitter-capacitance during turn-off, resulting in increased switching times and switching losses. The inverse feedback effect of the emitter may be utilized for limitation of the collector current di/dt in the case of short-circuits near the modules. To minimize the inductances L 31 and L 32, power modules are equipped with separate emitter control terminals. If several BOTTOM driver stages of a converter are supplied by a common operating voltage with negative DC-link reference, the parasitic inductances between the ground connectors of the drivers and the negative potential of the DC-link may cause unwelcome oscillations in the ground loops. This problem can be solved by HF-stabilization of the driver operating voltage near to the output stage or separate supply voltage potentials of the BOTTOM driver stages in high-power inverters. Inductance L 21 and L 22 Inductances L 21 or L 22, respectively, designate the inductance of the supply line between driver and transistor. Apart from increasing the impedance of the driver circuit, they may cause unwelcome oscillations with the input capacitance of the transistor. This may be remedied by a short, low-inductance connection between driver and transistor. Capacitances The capacitances C xx in Figure 3.23 stand for the intrinsic capacitances in the power semiconductors (voltage-dependent, non-linear) and cannot be influenced by the user. They indicate the minimum value of the commutation capacitance C K and, principally, effect a reduction of power dissipations during turn-off (see chapters 0 and 3.8). 167

167 3 Hints for application Additional power dissipations are generated during active turn-on due to the recharge process of the commutation capacitances; these have to be considered in many high-frequency MOSFETapplications ( khz...). C 11 and C 12 cause an inverse dv/dt-feedback to the gate (Miller effect, see Figure 3.35). In combination with the inductances near the switches, the intrinsic component capacitances may cause unwelcome oscillations EMI/mains feedbacks Processes in the converter Processes in a converter system will always produce unwelcome interference due to the switching operation of the power semiconductors on the one hand (Figure 3.24) and welcome energy transmission with the corresponding signal processing on the other hand. Processes in the Converter Power Conversion (Main Function) Noise Propagation (parasitic) Information Processing (necessary) Reactions to Mains and Load EMC Energy Transmission between Mains and Load Noise Source of Power Conversion Noise Source of Information Processing Control of Power Conversion - High Power - Middle Power - Small Power - Small Power - DC-Parameters, Fundamental Harmonics - Higher Harmonics - Higher Frequencies - Higher Frequencies High-Energy-Processes Low-Energy-Processes Figure 3.24 Energy processes in converters [299] These processes can be divided up into high-energy-processes, which may cause interferences in the mains and the load within a frequency range between fundamental frequency and about 10 khz, and low-energy-processes above 10 khz up to about 30 MHz, where noise radiation and, consequently, non-conducted current flow will start to be propagated. The frequencies mentioned originate more or less from possible measuring procedures, and not from physical effects. In the low-frequency range, these effects are called converter mains feedbacks, which are 168

168 3 Hints for application traditionally characterized by discrete harmonic current oscillations up to about 2 khz. Above 10 khz these oscillations are called radio interference voltages, which are indicated in db/µv and are designated as interference voltages due to selective measurements. For the interim frequency range, within which modern power semiconductors are switched, the first attempts are currently being made to introduce measuring procedures as well as limit ratings. Discussions on these disturbing side-effects are contradictory, since the same physical processes are described under different aspects. The difference between designations such as zero current, leakage current or asymmetrical interference voltage is only given by various frequency range classifications and by the frequency dependency of all switching parameters. Since this frequency dependency is continuous just as the transition to radio interference, the frequency transition ranges are inevitably very broad Causes of interference currents All interference is caused by the switching operation mode of power semiconductors. Causes of interference may be explained by the equivalent commutation circuit in Figure Network 1 i dm L K 2 Module Network 2 i cm1 S 1 C K 2 V K i L i dm i cm2 L K 2 S 2 C K 2 Baseplate i cm Z ch Z N1 Z N1 Z N2 Z N2 Heatsink Z hg GROUND Figure 3.25 Equivalent commutation circuit with noise propagation paths [299] In the case of inductive commutation switch S 1 will switch to the conducting switch S 2. In a hard switching process (L K = L Kmin, C K = C Kmin ) firstly the current will be commutated with a di/dt given by the semiconductor characteristics of switch 1. Commutation is finalized by the reverse-recovery-di/dt of switch 2, which determines voltage commutation and, consequently, dv/dt together with the current-carrying inductance and the effective capacitances C K. The effective capacitances comprise all capacitances C which are effective towards the neutral potential. Together with the impedances of the commutation voltage connections to the neutral potential parallel impedances of the commutation capacitances will become effective. At the 169

169 3 Hints for application beginning of the commutation process, the di/dt of switch 1 will cause a symmetrical current flow i dm within the commutation voltage capacitance and the parallel network 1. The dv/dt at the end of the commutation process caused by the reverse-recovery-di/dt of switch 2 and the inductance L, which serves as supply current, conducts the currents i cm asymmetrically via the ground line through the parallel lines to the commutation capacitances C K. Transition to soft turn-on by increase of L K (ZCS, chapter 3.8) will reduce the di/dt and, consequently, symmetrical current interferences. At the same time, the increased inductances L K will become effective in the circuit of the asymmetrical interference current. Dv/dt, at the beginning of the commutation process, is determined by the switching characteristics of S 1. The voltage leap at the end of the commutation process is determined by the reverse recovery current behaviour of switch S 2. Transition to soft switching in ZCS-mode will reduce current interferences and will change the frequency range of asymmetrical currents, without reducing them considerably, also see chapter The capacitive commutation process is started by active turn-off of switch S 1. In the hard switching procedure (C K = C Kmin ) the asymmetrical interference current is determined by the impedances towards the neutral potential which become effective parallel to the commutation capacitances and by the semiconductor characteristics of switch S 1. The current commutation following the voltage commutation and, thus, the symmetrical interference current is determined by the turn-off behaviour of S 1 and by the turn-on behaviour of S 2. An increase of C K will require a zero-voltage-switch with soft turn-off (chapter 3.8). The turn-off process starts with the first stage of current commutation with a di/dt, that is determined by switch S 1 at a reduced voltage. The delayed dv/dt will reduce the asymmetrical currents during voltage commutation. Passive turn-on of S 2 determines the di/dt during the second stage of current commutation. Asymmetrical current interference will be reduced by soft switching in ZVS-mode without changing symmetrical currents noticeably. Nevertheless, the increased capacitances C K will diminish the symmetrical interference current in network 1 in relation to the capacitive current divider. Soft switching converter circuits with turn-on or turn-off phase-shift control will reduce asymmetrical and symmetrical interference currents when using zero-voltage switches or zero-current switches, respectively. In converter circuits with auxiliary commutation arms, where ZVS and ZCS are switched alternately, interference currents will not be reduced considerably in comparison to hard switching circuits, see chapter Propagation paths In order to take measurements on radio interference voltages, voltage fluctuations at the mains connections of inverter to ground are selectively measured. The potential fluctuations refer to a defined point of ground, which is determined in standard measurements by connection of a line impedance stabilization network. Regarding symmetrical and asymmetrical interference currents within the frequency range of EMI, all simple low-frequency switching elements are equipped with additional inductances, resistances and capacitances, which will render a clearer simulation of their frequency dependency. Figure 3.26 shows the example of a simple step-down converter circuit, where network 1 is represented by the line impedance stabilization network (LISN) and network 2 by the applied load in contrast to Figure

170 3 Hints for application Module Wire Load DC-Link Wire LISN V S I S GROUND GROUND GROUND Figure 3.26 EMI-equivalent circuit of a step-down converter [193] The module simulates switches S 1 and S 2 including the commutation inductances and capacitances. The origins of interference currents described beforehand are illustrated in a simplified way, namely as current source I S for symmetrical interference currents and as voltage source V S for asymmetrical interference currents. In both sources the measured semiconductor characteristics are included as a function of time (Figure 3.27). Figure 3.27 Typical voltage and current characteristics of an IGBT-switch (top characteristic in V, bottom in A) [193] Figure 3.28 shows simulated results with the example taken from [193] based on the model of Figure 3.26; these results are almost fully in accordance with the measurements actually taken. 171

171 3 Hints for application EMI-Spectrum OP 450 V / 20 A / 5 khz +V Z -V Z Frequency Switch Current Switch Voltage Fourier-Analysis of Current Fourier-Analysis of Voltage V S Frequency Frequency Differential Mode Spectrum Common Mode Spectrum +V Z -V Z +V Z -V Z Frequency Frequency Figure 3.28 Simulation results of a 1200 V/50 A NPT IGBT dual module Operation parameters: DC-link voltage V DC = 450 V Load current = 20 A Pulse frequency = 5 khz The influence of additional paths of propagation via energy and information transmission lines of the driver circuits have been examined in [299]. 172

172 3 Hints for application EMI suppression measures Conventional interference suppression is based on the use of customised filters, which are attached to the mains supply of the device. According to the set limit characteristics for a certain type of device (see example tables) various filters are applied by means of the line impedance stabilization network and standardized test assemblies, until the limit values are kept in all frequency ranges [259]. Table of engineering standards GENERIC Engineering standard Application Interference factor EN /1 VDE 0839, part 82-1 Residential, commercial EMI immunity and trade applications, EN /1 VDE 0839, part 81-1 small businesses Interference emission EN /2 VDE 0839, part 82-2 Industry, EMI Immunity EN /2 VDE 0839, part 81-2 power stations etc. Interference emission Examples for existing product standards Classification of equipment Product Standards Interference factor ISM-devices (industrial, scientific and EN Interference emission medical HF-devices) Generic EN /2 EMI immunity Radio and television receivers and EN Interference emission connected equipment EN EMI immunity Household appliances EN Interference emission Generic EN EMI immunity Fluorescent lamps and EN Interference emission lights Generic EN EMI immunity Data processing EN Interference emission systems pren , EN EMI immunity In this mostly empirical procedure, often costly filters are used. It will be more effective to design and construct a circuit, which considers, from the beginning of any development processes, the effects of electromagnetic interference and the optimization of propagation paths with respect to their origins and to possible measuring points. Optimization means either to produce high-resistance propagation paths for interference currents by the application of selective blocking circuits or to create low-resistance short-circuit paths for interference currents by using selective suction filter circuits. In the following, selected measures are explained with regards to Figure Symmetrical interference current circuits will be closed via the capacitance of the commutation voltage source. Ideal capacitance connected to switches 1 and 2 without the influence of any line impedances would be required for the creation of a short-circuit path for interference currents. Measurable radio interference voltages will then be generated via the capacitive voltage ripple, which will effect a current flow over the paralleled effective circuits. Therefore, all measures that may be taken to reduce symmetrical inerference currents will aim at the arrangement of corresponding suction filter circuits parallel to the connection lines of the commutation voltage. All efforts in this respect can be reduced in relation to which extent the creation of a filter circuit as near as possible to the switch connections may be achieved by nearly ideal capacitances and active filters. Principally, asymmetrical interference currents will be propagated via the ground line. For interference suppression it seems to be important to have extremely high-resistance impedances 173

173 3 Hints for application in all switching points with steep potential increases versus ground potential and, at the same time, to limit the jumping potential to the non-avoidable switch connections. In the example of the equivalent circuit in Figure 3.25, firstly, interference suppression could be managed by reduced coupling capacitances of the drivers and capacitances effective via the module base plate and the heatsink. If the drivers do not receive switching information and are not supplied with auxiliary energy by the neutral potential, no shifted currents will be conducted via the earth line, i.e. the circuit will be closed within the appliance. There will be no flow of asymmetrical interference currents. Interference currents propagating over the base plate may be reduced by applying shielding measures and different isolation materials [193]. With application of the measures mentioned above (near to the semiconductor chips) a considerable reduction of interference currents can be achieved, as shown in Figure 3.29 with the example of an especially modified IGBT module [193]. dbµv 100 EMI-Spectra NPT-IGBT-Module Standard Modified Module ,01 0,1 f / MHz Figure 3.29 Comparison of interference spectra of a standard IGBT module and an EMI-optimized IGBT module; [193]; Operation parameters: DC-link voltage = 450 V Load current = 20 A Pulse frequency = 5 khz The connection to network 2 via the choke coil depicted in Figure 3.25 is not influenced by these measures. The coupling capacitance of this connection line can only be reduced by shortening the line as far as possible. Ideally, an L/C filter should be connected directly to the the jumping potential so that the inductance of which will attenuate the potential jumps to such an extent that all other coupling capacitances in network 2 will not be able to contribute considerably to the asymmetrical interference current. If network 2 is the supply point of the mains where the standard measurement using LISN is done then this measure will be inevitable, i.e. the L/C filter has to be part of the EMI filter Power units ready for installation SEMIKRON offers power units ready for installation both in module and MiniSKiiP or SKiiP product range, which are designed according to the above mentioned standards and optimized with respect to the characteristics of the applied power modules. The functional spectrum may comprise - input rectifiers with diodes, thyristors or transistors, 174

174 3 Hints for application - laminated DC-links with Cu- or Al-sandwich busbars, electrolytic or film capacitors, HFblocking capacitors, balancing and discharge resistors, - inverter legs with IGBT or MOSFET modules or SKiiPPACKS, - liquid coolant or forced air heatsinks; fan optional, - driver with protection functions, sensors, power supply and potential isolation. Before delivery, all power units have to pass application-specific functional testing. Powerboards with MiniSKiiP Figure 3.30 shows view and block diagram of a SKiiP025HAB powerboard with MiniSKiiP 8 layout for up to 15 kw power output at a line supply voltage of 400 V. Controller Interface Detections SCR-Driver Driver and Detection for DC-Link-Chopper V DC Detection IGBT-Sixpack Driver Current Detection Temperatur Detection a) Power Terminals b) Figure 3.30 Powerboard SKiiP 025HAB/NAB a) Block diagram b) View (without fan) MiniSKiiPs SKiiP 83 ANB15 (diode rectifier and brake chopper / version NAB) or SKiiP AHB15 (half-controlled thyristor rectifier and brake chopper / version HAB) as well as SKiiP 83 AC12I (three-phase inverter with IGBTs 25 C and AC current sensors), DC-link (700 µf), potential-separated driver, power supply, overcurrent, overtemperature and undervoltage protection and a DC-link charge circuit (for version HAB) are integrated into a central PCB of the powerboard. 175

175 3 Hints for application The PCB is mounted on to the heatsink via the MiniSKiiP components and additional support pins. SKiiP power units SKiiP power units are equipped with one or several integrated SKiiPPACKs (also connected in parallel), a sandwich DC-link and optional rectifiers, fans and additional snubber circuits, if required by the customer. Figure 3.31 shows different SKiiP-types with vertical or horizontal DC-link construction. a) b) c) Figure 3.31 Construction types of SKiiP power units a) Flat construction for wide switchboards b) Vertical standard DC-link c) SKiiP-RAC with IGBT rectifier and converter For power supply voltages from 230V up to 690V all available SKiiPPACKs may be integrated into SKiiP power units. Power outputs up to MW-range may be produced by paralleling SKiiPPACKs, using either SEMIKRON standard heatsinks or, optionally, nearly any other forced air or liquid coolant heatsinks supplied by the customer. Figure 3.32 shows the example of a SKiiP power unit for a rectified 690 V mains (DC-link voltage up to 1200 V), comprising 3 SKiiPPACKs SKiiP 1092GB CTV with fibre optic inputs, a sandwich DC-link construction totalling up to 8.8 mf /1350 V and a radial fan. At a pulse frequency of 3 khz and a supply air temperature of 35 C the effective output current (50 Hz) will value up to 250 A during continuous operation and to 375 A for operation period of 1 min/10 min. 176

176 3 Hints for application Figure kva inverter unit with SKiiPPACKs Power units with SEMITRANS IGBT- or MOSFET-modules For applications, where SKiiPPACK or MiniSKiiP power units will not be sufficient, assemblies with SEMITRANS modules, SEMIDRIVERs, standard heatsinks and laminated DC-links may be a solution. These can also be subjected to application-specific testing, if required. The power units described above, which are characterized as sub-systems by nature, require a different dimensioning by user and manufacturer compared to modules. In this respect, SEMIKRON offers their calculation programme SKiiPsel to SKiiP and MiniSKiiP customers as a tool for pre-selection and rough dimensioning, see chapter Further steps may then be co-ordinated by means of a checklist, which should consider, among other things, the following technical aspects: - application, power flow direction(s), circuit structure, required functions, - mounting dimensions (size, weight), special requirements (oscillations, shock load, etc.), - input (mains, generator, battery,etc.), input voltage range, cos ϕ, special requirements; for mains feedback: fundamental frequency, pulse frequency, DC-link voltage, - output (mains, transformer, DC-motor, AC-motor, reluctance motor, etc.), output voltage range, output current, cos ϕ, overload (value/duration/frequency), fundamental frequency (min./max.), current at min. fundamental frequency, pulse frequency, load cycles (current, voltage, frequency, cos ϕ as a function of time), - DC-link (electrolytic or film capacitors), rated voltage, min./max. capacitance, max. DC-link voltage, ambient DC-link temperature, - isolation test voltages, type of protection, - driver, driver interface (transformer, optical), options (sensors for current, temperature, DClink voltage), - cooling: ambient temperature/coolant temperature min./max; for natural air cooling: max. air volume, admissible noise level, - for liquid cooling: cooling medium (antifreeze, volume, rate of flow), 177

177 3 Hints for application - storage temperature, special requirements with respect to climate, extreme altitude over NSL, - required module life (power modules, DC-link capacitors). 3.5 Driver Gate voltage and gate current characteristics Driving process As already described in chapter the switching behaviour of MOSFET and IGBT modules can be greatly controlled by recharge the gate capacitance. In theoretical borderline cases, the gate capacitance recharge may be controlled by resistance, voltage or current (Figure 3.33). R G G G G C V GG V GG i G G E a) b) c) E E E Figure 3.33 Gate driving process for MOSFETs and IGBTs [194] a) Control by resistance b) Control by voltage c) Control by current The preferred variant is to drive the system via a gate resistor (or two separate resistors for turnon and turn-off) according to Figure 3.33a. Characteristic of this variant is the Miller plateau in the gate-source or gate-emitter voltage, respectively (Figure 3.34). The switching speed is adjusted by R G at a continuous supply voltage V GG ; the smaller the R G, the shorter the switching times. The disadvantage of resistance control is that the gate capacitance tolerances of the MOSFET or IGBT will have direct influence on switching times and switching losses. Impressed voltage at the transistor gate driven according to Figure 3.33b will eliminate this influence; the switching speed of the transistor is directly determined by the gate dv/dt. Thanks to this voltage no Miller plateau will be formed in the gate voltage characteristic. This requires sufficient driver current capacity. Current control by a positive and negative gate current generator, as shown in Figure 3.33c, determins the gate charge characteristics (see Figure 1.12 and Figure 1.13) and is comparable to resistance control with respect to gate voltage characteristics. Control voltage ratings Figure 3.34 shows the characteristics for gate current i G and gate-emitter voltage v GE in a resistance controlled circuit. 178

178 3 Hints for application v GE (5 V / Div) i G (0,4 A / Div) a) 0,2 µs / Div v GE (5 V / Div) i G (0,4 A / Div) b) Figure ,2 µs / Div Gate current and voltage characteristics during turn-on and turn-off a) Turn-on b) Turn-off The control voltage V GG for both polarities has to be dimensioned according to the electrical strength of the gate isolation, which is usually indicated as 20V for current power MOSFETs and IGBTs. This value may not be exceeded - not even transiently - which might require special measures during turn-off, see chapter and On the other hand, R DS(on) and V CEsat, respectively, will decrease when the gate voltage increases, and, therefore, we recommend applying a positive control voltage, which delivers a gate voltage of V GS = +10 V V GE = +15 V for power MOSFETs and for IGBTs during stationary on-state. Most datasheet ratings are based on these measuring parameters. As demonstrated in Figure 3.34, the gate voltage for IGBTs should be negative to the emitter potential during turn-off and off-state; recommended values are V. 179

179 3 Hints for application This will maintain a negative gate current during the complete turn-off procedure (even if V GE approaches V GE(th) ) sufficiently to draw the main share of positive charge carriers from the n - - drift zone by means of a high dv CE /dt during turn-off time and, thus result in a short tail current. Another, more serious disadvantage of blocking the IGBTs of a bridge circuit with V GE = 0 V will occur during the reverse-recovery of the parallel inverse diode of the turned off transistor because of the dv CE /dt (Figure 3.35). v GE1 v GE(th) Driver +15V/0V R G i C1 T1 i F1 D1 v GE2 t dead v GE1 i F2, v CE2 i L i C2 i L i F2 v CE2 Driver +15V/0V R G C GC2 iv v GE2 v CE2 T2 D2 i F2 i C1, i C2 i C1 = i L + i C2 -i F2 a) i L b) i C2 Figure 3.35 Cross current in an IGBT bridge arm due to turn-on by dv CE /dtfeedback of T 2 a) Switching principle b) Current and voltage characteristics The high dv CE /dt of the collector-emitter voltage v CE2 during the reverse-recovery-di/dt of D 2 will effect a displacement current i V through the gate-collector capacitance C GC2, also see chapter i V = C GC * dv CE /dt. This displacement current, in turn, will cause a voltage drop over the resistance R G (or R GE /R G ). If, as a result of this, v GE rises and exceeds the threshold voltage V GE(th), T 2 will be driven to its active region during the reverse-recovery-di/dt (cross current, additional power dissipation in T 1 and T 2 ). Other than with IGBTs, the application of a stationary negative gate-source voltage during offstate is not recommended for driving power MOSFETs. Parasitic turn-on with all consequences, as described above, is done within the MOSFET too at the same time. However, it will protect the transistor structure of the MOSFET, which is only limited resistant to dv/dt. The equivalent circuit of a power MOSFET (Figure 1.3) demonstrates the displacement current through C DS to the base of the parasitic npn-bipolar transistor as a result of dv DS /dt. If the voltage drop at the lateral p-well-resistor R W reaches threshold voltage level, the bipolar transistor will be turned on parasitically, which may lead to destruction of the MOSFET by power dissipation during periodic operation. 180

180 3 Hints for application Parasitic turn-on of the MOSFET channel at V GS = 0 V over C GD will reduce dv DS /dt during blocking state and will weaken the dangerous effect of bipolar transistor turn-on (see Figure 3.35). Control current ratings, driving power The total driving power P Gavg to be delivered by the driver circuit can be determined from the gate charge Q Gtot (see Figure 1.12 and Figure 1.13): P Gavg ( VGG+ + VGG ) Q Gtot f s with QGtot = CEquiv. ( VGG+ + VGG ) = Peak gate current values are calculated as follows: I I GMon GMoff ( V + GG+ VGG )/ R Gon = (ideal) ( V + GG+ VGG )/ R Goff = (ideal) Driver power is calculated as follows: P P ( VGG ) = VGG+ QGtot f s + f s = switching frequency ( VGG ) = VGG QGtot f s Example: Resulting in: V GG+ = 15 V, V GG- = -15 V, R G = 3.3 Ω Q Gtot = 2.3 µc (SKM500GB123DS) f s = 10 khz, V DC = 600 V I GMon = I GMoff = 9.09 A P Gavg = 0.69 W P( VGG + ) = P( VGG ) = W I( VGG + ) = I( VGG ) = 23 ma (average) Influence of driver parameters on switching features As already mentioned, important features of driven power MOSFETs or IGBTs are dependent on V GG+, V GG- and R G ratings. The following table shall give a first overview (<: increases, > decreases, -: remains): Rating/ characteristic V GG+ < V GG- < R G < see chapter R DS(on), V CEsat t on, E on t off E off turn-on peak current * ) turn-off peak voltage * ) dv/dt-sensitivity (MOSFET) ( IGBT) actively limited I D, I C ruggedness to load short-circuits > > > < - < - < < < > * ) during hard switching under ohmic-inductive load - < - > > - < < > < < < < > > > < < <

181 3 Hints for application Forward characteristics (R DS(on), V CEsat ) The dependences of the forward characteristics of power MOSFETs and IGBTs on the drive parameters can be read from their output characteristics (see chapter 1.2.2). In Figure 3.36 this is explained with one example each for SEMITRANS-MOSFETs and IGBTs taken from the current datasheets. a) b) Figure 3.36 Forward characteristics versus control voltage (gate voltage) a) Power MOSFET-module SKM 111 b) IGBT-module SKM100GB123D In SEMITRANS, SEMITOP and MiniSKiiP datasheets the recommended maximum ratings and characteristic values mentioned in chapter are indicated with V GG+ = 10 V for power MOSFETs and V GG+ = 15 V for IGBT modules which is an acceptable compromise in conventional applications between power dissipations, turn-on peak current and short-circuit behaviour. Switching times, switching losses (t on, t off, E on, E off ) Control voltages and gate resistances will affect the various parts of turn-on time t on = t d(on) + t r, turn-off time t off = t d(off) + t f and tail time t t of the IGBT in different ways: Since the gate capacitance amounts to absolute ratings of V GG+ and V GG- before switching, the recharge time will decrease (turn-on delay time t d(on), turn-off delay time t d(off) ) on condition of a given gate resistor R G if the recharge current or (V GG+ + V GG- ) increases. On the other hand, switching times t r and t f and, consequently, energy dissipations E on and E off may only be affected by the switching control voltages V GG+ or V GG-, since they determine the current flow through the gate resistor R G. SEMITRANS-IGBT datasheets include diagrams showing the dependences of switching times and energy dissipations on R G, measured for maximum current ratings I 80 C on condition of hard switching under ohmic-inductive load (Figure 3.37). 182