A Low Power 900MHz Superheterodyne Compressive Sensing Receiver for Sparse Frequency Signal Detection

Transcription

1 A Low Power 900MHz Superheterodyne Compressive Sensing Receiver for Sparse Frequency Signal etection Hamid Nejati and Mahmood Barangi EECS department, University of Michigan, Ann Arbor Abstract In this report, a full implementation of a compressive sensing receiver is introduced. The receiver is based on the superheterodyne receiver configuration. The systemlevel modeling and design of this structure as well as circuit level design and layout implementation of this structure are demonstrated. The narrowband receiver is designed for 900MHz frequency and can detect sparse signals in the frequency domain in the band of interest. In the superheterodyne topology, the local oscillator replaced with a linear feedback shift register(lfsr), the application of the mixer changes to multiplier, and finally the low pass filter, ideally an integrator, can do the summation. I. INTROUCTION compressive sensing has been attracted a lot of interest recently due to its ease of implementation and the rapid development of signal reconstruction algorithms. One of the most important advantages of the compressive sensing technique is that it can directly extract information from the input desired signal. In most analog and digital systems, we are dealing withahugesetofredundantdatathatcanbecompressed with signal processing methods without removing significant information[1]. Compressive sensing has been used in a lot of applications including: image processing, data processing, and object classifications. In the analog design world, different implementations of the compressive sensing algorithm has been introduced such as random demodulation, random sampling, and random filtering [2]. Among these systems, random demodulation technique has shown a great potential for future communication systems[3]. This configuration can be utilized in the transmitter design such as sensor nodes in awirelesssensornetworkoritcanbeusedinthereceiver architecture to reduce the complexity and power consumption ofthereceiver.inthereceiverdesign,whichisthefocusof this report, this configuration can reduce the burden of the analog to digital converters(acs) as well as reducing the overall power consumption of the system. Compressive sensing(cs) is a compression technique that can be utilized for sparse signals recovery. A sparse signal can be defined as any signal that can be expressed by a small number of components. As an example a sinusoidal signal is sparse in Fourier domain. The CS algorithm relies onthemultiplicationoftheinputsparsesignalbyarandom matrix known as random measurement matrix. The number of measurements should be less than the whole number of LNA x Mixer LFSR Φ Amp. AC Reset ata Recovery ata Recovery Fig. 1. System level configuration of ( superheterodyne compressive sensing receiver and( mathematic modeling of the compressive sensing based receivers topology. data points (Nyquist rate). Adding the measurement data can generate a single output data for each measurement. By sending the single data for each measurement, CS algorithm can recover the original data. A superheterodyne receiver can be interpreted as a random demodulation system by replacing the multiplication by mixing, local oscillator with a random number generator, and the summation operator by integrator/low pass filter. TheoverallsystemblockdiagramisshowninFig.1(. TheinputRFsignalincidenttotheantennaistheinputofthe system. This signal is amplified with a narrowband low noise amplifier(lna). The amplified signal is multiplied(mixed) with a random number string. The mixed signal passes through a low pass filter/integrator and the output data is digitally sampledwithalowrateac.thesampleddataisprocessed in the processing unit. In our implementation, we utilized a Matlab program to recover the input signal. This stage can also beimplementedonaspboardtomakeareal-timeanalysis and recovery of the data. In the following section, an overview of the whole system is explained and the system level design procedure is fully described. Then, a detailed design, modeling, and implementation of each block are separately demonstrated. In the following, the system level results as well as the circuit level results are illustrated. finally, we conclude the report.

2 II. SYSTEM LEVEL ESIGN AN IMPLEMENTATION OF COMPRESSIVE SENSING RECEIVER We developed an Analog to Information Converter(AIC)[2] using Compressive Sensing(CS)[3] to decrease the sampling rate of the AC leading to powerreduction of the whole system. High speed applications demand flash ACs, which consume huge power and require special cooling process. In this section, we plan to develop behavioral models for the whole system in Matlab/Simulink by considering the nonidealities of each building block. We also developed a link between Matlab and Cadence based on the ocean script to automatically validate the accuracy of our models compared to the transistor level design. The overall system is shown in Fig. 1 ( and (. As shown in Fig. 1 (, the system consists of a superheterodyne receiver topology. In this topology, The input signal enters an LNA and after desired amplification multiplies with a bipolar random number streams generated by a pseudo-random number generator. This pseudorandom number generator is based on linear feedback shift register(lfsr). The LFSR consists of ten -flip flops and two XOR gates. The input 2GHz clock signal is generated with the ring oscillator. The minimum clock cycle should satisfies the Nyquist condition. Since the frequency of the input signal is 900M Hz, the Nyquist condition dictates that the system must have the clock frequency more than 1.8GHz. In our setup, we set the input clock frequency to 2GHz. By integrating the multiplication of the random bit stream with the amplified input signal, we can extract the data required for compressive sensing signal recovery algorithm. The compressive sensing recovery algorithm is based on the recovery of a frequency sparse signal. The one tone signal is sparse in frequency domain/basis[1]. The Fourier basis is thematrix ψ j = n 1/2 e i2πjt/n,where ψ j isthe j th column ofthebasismatrix, nisthetotalnumberofpoints,and tis the sampling time, respectively. This matrix is complex and is not appropriate for practical real signal applications. By utilizing the Euler transformation and splitting the exponential into periodic harmonic sine and cosine functions and filling thebasismatrix,wecanhaveatwiceaslargematrixwith all the required information. For reconstruction algorithm, we utilized an orthogonal matching pursuit algorithm[4] to find thesignaloutofthemeasurementdata.thetotalnumberof measurementsislessthanthewholenumberofdatabyafactor of 8. III. CIRCUIT LEVEL ESIGN AN ANALYSIS OF THE WHOLE SYSTEM In this section, we discribe the overall receiver front end circuits in more details. A. Linear Feedback Shift Register and Clock Generator The linear shift register(lfsr) circuit consists of ten registers(-filpflops) as well as two XOR gates. the -flipflops areimplementedby C 2 MOS registerstructure.thelfsr structure,asshowninfig.2,cangenerateapseudorandom bit stream. For the recovery purposes, we require a bipolar Fig.2. (TheblockdiagramoftheLFSRusedtogeneratedpseudorandom bitstream.(theregisterimplementationbyac 2 MOStopology. random bit stream. The passive mixer can provide the bipolar random multiplication of bit stream into the RF input signal. Therandombitgeneratorcangeneratebitstreamsaslongas 1024clockcycles.Wecallthislengthoftheclockcyclesa frame. By initializing the -flip flops, the desired random bit pattern can be generated. The LFSR requires a clock signal thatcanbegeneratedonchipwithaseriescombinationof eleven invertors. The clock signal passes through three clock buffers. The overall power consumption of this stage is less than 600µW. B. Low Noise Amplifier and Buffer The first stage after antenna should provide high gain and low noise figure for a guaranteed high performance receiver system. We utilized an inductively degenerated low noise amplifier,asshowninfig.3.inordertoprovideimpedance matching between low noise amplifier and mixer, we are utilizing an RF buffer, as shown in Fig. 4. This buffer is a common drain structure loaded with an LC tank. The equivelent circuit of the output port is a parallel RLC tank. Theresistorinthissetupisequalto 1 g m.thestepbystep design procedure is as follows, we should appropriately size 1 thetransistorinawaythatits g m = R s.thenbysetting the output inductor and capacitor in resonance at our desired frequency 900M Hz, the narrowband matching is possible. This buffer can also provide high isolation. The isolation is an important factor in this design, because the random number oscilator is generating high power bit stream. The isolation of themixerbyitselfisnothighenoughtosuppressthereflected signal. By introducing the cascose stage and the buffer the required isolation can be achieved to satisfy low reflection of the signal back to the antenna. C. Mixer/Multiplier In order to implement the bipolar multiplication of the LFSR bit streams into the input amplified RF signal, we are utilizing

3 C IN M 1 V C V B L R S R B M 2 V LFSR - V LFSR C IN L G M 1 V RF V out V LFSR V LFSR - R S C P L S Port 0 Fig. 3. Inductively degenerated cascode amplifier utilized for high gain and low noise figure. Fig. 5. Passive mixer design for multiplication purpose. V B V R B L C S C S dec Fig. 4. Buffer stage to decouple/isolate the LNA from the Mixer and LFSR. a passive mixer. This mixer can provide a multiplication of ±1,setbytheoscilatorsignal,intotheRFsignal,whichis the exact functionality that we require. The ±1 multiplication is provided by commutatively switching the transistors in a bridgelikestructure,asshowninfig.5.. Integrator Inordertoprovidetheintegration,weareusingahigh bandwidth amplifier as well as a well known capacitor and resistor structure to implement the integration. The amplifier designisshowninfig.6.thisintegratororinabettersense low pass filter can implement the summation operator in the blockdiagram,showninfig.1(.wearealsousingan RClowpassfilteraftertheintegratortomakelowpassdata required for CS. Fig. 6. Wide bandwidth amplifier utilized to implement the integration. E. Analog to igital Converter Flash ACs are commonly utilized for high performance systems. Flash ACs are power hungary and implementing a low power structure is highly required[5]. We implemented alowpower 2.6mW,highspeed 200MSpsflashACto maintain the low power feature of the system. The encoder including thermometer to 1 in N converter and ROM are designed customly instead of synthesis tools to reduce the area and power consumption. The latched structure is chosen for the comparators to reduce the static power consumption, which ismorethan 80percentofthetotalpowerconsumptionofthe flash AC. IV. SIMULATION RESULTS The overall performance of the receiver is measured by block by block performance evaluation. The LNA performance metrics are S-parameters, noise figure, and linearity. The S- parametersaswellasthenoisefigureareshowninfig.8.

4 Vin Encoder ROM t power (dbm) Output - Input power (dbm) Fig bit Flash analog-to-digital converter topology. t power (dbm) Output Input power (dbm) ude (db) Amplitu Fig. 9. ( input refered 1-dB compression point and( input refered third order intercept point of the LNA. S11 NF S22 S12 S21 Frequency (GHz) Fig. 8. The scattering parameters including: input and output matching, gain andisolationaswellasthenoisefigureofthelna. Thenoisefigureisaslowas 1.2dB,gainisashighas 23dB, inputandoutputmatchingisaslowas 21dBand 14dB, respectively. The isolation is as low as 58dB. The stability ofthelnaisalsocheckedandtheamplifierisstable.the input refered 1 db compression point andthird order intercept pointareshowninfig.9(and(,respectively. The integrator response and the multiplier noise are shown in Fig. 10( and(, respectively. TheSNRoftheACatlowfrequenciesandthefrequency of operation (200M Sps) are and 34.2 respectively, leadingtotheenobof 5.87and 5.4.Thefigureofmeritofthe AC at the frequency of operation is 308f J/conversionstep. TheSNR,SFR,ENOB,andTHareshowninFig.11(, (, and(c), respectively. The response of the multiplication of the LFSR random bitstreamintotheamplifiedrfinputsignalaswellasthe generatedclocksignalisshowninfig.12 tude (db) Amplit itude (db) Ampli Frequency (GHz) Frequency (GHz) Fig. 10. ( Integrator frequency response.( The passive mixer noise figure.

5 ( ( (c) Fig. 11. Flash AC specifications including:( Signal-to-Noise istortion Ratio(SNR) and Spurious Free ynamic Range(SFR),( Effective Number of Bits(ENOB), and(c) Total Harmonic istortion(th). Amplified RF signal age (mv) Volta Multiplied signal Clock Amplitude Frequency (Hz) x 10 8 LFSR bit stream Time (ns) Fig. 12. The overall response of the clock, LFSR, amplified RF signal, and the multiplication of the random bit stream into the amplified RF signal. Amplitude The recovery algorithm could recover a single tone sinusoidalwaveandtherecoveredsignalisshowninfig.13( and(. TheoveralllayoutofthereceiverisshowninFig.14. TheoverallspecificationofthesystemislistedintableI Frequency (Hz) x 10 8 Fig.13. Thefrequencyspectrumof(asingletonesinewaveand(the recovered single tone sine wave. Clock & LFSR V. CONCLUSION In this report, we investigate a RF receiver frontend, which is operating optimized for the compressive sensing applications. CS technique can be utilized for recovery of sparse frequency signals. We demonstrated a system level as well as a detailed circuit level design, modeling, and implementation of the whole receiver system. LNA Multiplier Flash AC Integrator VI. ACKNOWLEGEMENT We wish to thank Professor avid Wentzloff for his advice and thoughtful suggestions. Buffer Fig. 14. The layout of the whole system.

6 TABLE I THE OVERALL SYSTAM SPECIFICATIONS Overall system Specification@ 900MHz LNABuffer S 11-21dB S 21 23dB S 12-58dB S 22-14dB Power 4.95mW NF 1.2dB 1dB compression -12.2dBm IIP3-3.9dBm Mixer NF 9.67dB LFSR clock Power 600µW clock 2GHz Integrator Power 1.5mW 3-dB cutoff 12MHz Flash AC Power 2.6mW Sampling 200MSps SNR 36.98dB ENOB 5.87 FOM 308fJ/conversion REFERENCES [1] E. Candes and M. Wakin, An introduction to compressive sampling, IEEE Signal Processing Magazine, vol. 25, no. 2, pp , [2] R. Baranuik, Compressive sensing, IEEE Signal Processing Magazine, vol.24,no.2,pp ,2007. [3] T.Ragheb,J.Laska,H.Nejati,S.Kirolos,R.Baraniuk,andY.Massoud, A prototype hardware for random demodulation based compressive analog-to-digital conversion, IEEE Midwest, pp , [4] J. TROPP and A. GILBERT, Signal recovery from random measurements via orthogonal matching pursuit, IEEE Transactions on Information Theory, pp. 1 9, [5] K.Yoon,S.Park,andW.Kim, A6b500msample/scmosflashadc with a background interpolated auto-zeroing technique, IEEE JSSC, pp , 1999.