NATIONAL RADIO ASTRONOMY OBSERVATORY Green Bank, West Virginia Electronics Division Internal Report No, 121 NRAO STANDARD CLOCK DIVIDER AND DISPLAY

Transcription

1 NATIONAL RADIO ASTRONOMY OBSERVATORY Green Bank, West Virginia Electronics Division Internal Report No, NRAO STANDARD CLOCK DIVIDER AND DISPLAY Ray Hallman AUGUST 97 NUMBER OF COPIES: 50

2 NRAO STANDARD CLOCK DIVIDER AND DISPLAY Ray Hallman A new standard clock has been completed comprising small circuit cards, power supplies, control switches, displays and chassis. The system keeps track of hours, minutes, seconds, tenths seconds, and hundredths seconds which are available on rear-mounted 56-pin Elco connectors in two formats:. TTL (0, +5), BCD on protected pin Elco.. 3-C (0, -6), BCD on exposed pin Elco. The clock divider requires an external standard oscillator that may be either solar or sidereal. MHz, V pp. A + or - trigger pulse of 6 volts may be applied to rear BNC connectors to provide sync when setting the clock. A day advance pulse is provided to advance the calendar system if one is used. (See Electronics Division Internal Report No. 0.) A switch selectable timing interrupt (00/50 ms) for the site computers is provided in the Elco' s. A picture of the front panel is presented showing the controls: NI RAO STANDARD CLOOK SECOROS LOGIC CARD CARD #/ :SET...; ET R:

3 Decade LED displays provide the time readout. The circuit cards are ccessible from the front panel. Several controls and display LED lamps are avail ble for setting the clock. The clock may be preset with automatic sync as follows. The desired time is set into the thumbwheels. With a one second tick provided by most precision time bases con nected to the proper trigger input and the setis c :fe switch to set, momentarily press and release the set arm push button about / second before the thumbwheel time setting. The red armed lamp will cycle on nd off when the system is properly armed. The green run LED comes on when the system has been properly triggered. Manual trigger is accomplished with no extern trigger att ched when the manu trigger button is depressed thereby extinguishing the armed lamp and igniting the run lamp to commence c unting time from the moment the button is pushed in The clock normally operates from a stand rd 5 V AC power line. A V store battery may be attached to the battery connector with pin ground and pin + V DC nominal. When the primary power fails, the battery will supply power to the clock. About / amp current with a minimum of 9. 5 V DC and a maximum 30 V DC is required to power the system. When primary power returns, the battery will recharge at a rate of about / amps until a voltage limit set by adjusting the AC powered supply output to 3. 5 vilts with the battery disconnected measure voltage at bøttery connector. Three other pictures show the front and l y.tck views presenting the pack ge in perspective.

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5 The four circuit cards are shown below. Note that the cards and are identical and may be interchanged. "A.,* miritt,7-7 If AraA. 7g, ff, * * Mt 0 MIR

6 - 5 - A schematic of the seconds logic card is shown in Figure L HOLD 0 +5 END PL K C A C A C A C A 880 I 880 A 880 B t 880 C 880 D I MHz INPUT K IX V pp f\d. K. K SA 0V F K I D C V90 5 A ID 6 K. 0 S +0V 0 DB s 0S TRIGGER PULSE J DC BUFFERED TRIGGER II Do 3 S R Ii 3 SPARES: NONE 3 08 S TEN CARRY SI 6 DAC' CA El.IS SET 0 0 HRS. D. S B H Dc C,S 0H II Do D 0. 8S S R 0H II 3.08SA 6 C C 5 A IS 9 SET B E 5 UNITS 880 SECONDS Dc S R 3 85 SET TENS SECONDS DG E 888 COLON ND SET REST SECONDS CARRY - U - Dc S R II g0 707 COMP. SIDE 3 ABCD EFH J KLMN A ALL CHIPS ARE PIN WITH Vcc PIN GND PIN 7 3 IOS 3 0 S 0S 80S II] 80M 0 H = 80H SECONDS AND FRACTIONAL SECONDS LOGIC CARD -# I

7 6 The MHz reference input is at pin V AC coupled into the level shifter buffer chip K which is an 880. The buffered output at pin 6 is divided by 880 decade counters chips A, B, C and D, providing 00 Hz to the clock input terminal (pin 8) of chip J, which is the. 0 seconds decade The 0 Hz output of this decade is coupled to the 0. second decade (chip H) providing the BCD drive logic sign s (via the non-inverting buffers, chip N) to the least signficant digit of the LED front panel display. Similarly the outputs of the higher order decades drive the respective digits of the display. Chip E is an 888 which is a divide by 6 counter providing states 0-5 for the tens of seconds decade. The output of this chip provides the seconds carry ( pulse/mm) to the minutes counter on card 3 discussed later Pins 3 through 8 of card also provide the TTL outputs to the rear panel Eico digital output connector. Pins M through U are connected to the thumbwheel switches providing the preset data

8 7 Chip K, pin 8 provides the buffered trigger to card 3 containing the arm/trigger/ hold logic. A schematic of card 3 is shown below. SECONDS CARRY Ell C c 5 DA A SET < B UNITS MINUTES 8 S R IK )8 6 m m m 8 m SET TENS MINUTES DCH 888 I F.,t DD 0m Orn 9 0 m 3 8 SET UNITS HOURS CI C C 3 0 DA A SR h Ej ti h 8 8 Ell TEN CARRY SET TENS I HOURS SET END PI L.08 SA El PL 00/50 ALs.05 SA SET HR. 3 0 C 700 SET 5 tio D D Q S 9 D B, Q _ 9 8 D B Q 3 77 _ 6 _ r- i +5 3 C> 707 W P 507 A WHP 68 8 I3 507 A ED 0 h 0 ha DATE ADVANCE 8-00 p.s RESET ARMED LAMP RUN LAMP SPARE UHP 507,3 IOHs PIL NOTE: ALL CHIPS ARE PIN WITH Vcc GND 7 EXCEPT CHIP L WHICH IS 6 PIN WITH Vcc 6 B GND 8 ; CHIP K IS 6 PI N. BUFFERED MANUAL TRIGGER TRIGGER 0 HOLD Vcc COMP, SIDE ABC() E FHJ K LMN Z - r" A HOURS AND MINUTES LOGIC CAR D. * 3

9 8 Chips J, H, and F are the ' s and 0' s of minutes and ' s of hours respectively. The 0' s and 0' s of hours comprises chip H of card 3 and chip E of card. Twentyfour hours is decoded by gate C-3 which sets flip-flop B-5 providing the reset pulse and day advance pulse via isolator slot K. The run/armed logic comprises flip-flop B-9 and gates A-3 and A-. Set provided by the set arm pushbutton sets the flip-flop thus lighting the red armed LED and applying the Hold signal to inhibit the time base buffer (chip K on card ), thereby stopping the clock until the buffered trigger or manual trigger button resets the flip-flop B on c rd 3 to commence measuring time. The PIL (interrupt logic) comprises chips C and D on card 3 providing the switch selectable 00/50 ms timing interrupt which is controlled by the PIL 00/50 ms signal present at flip-flop D-. Flip-flop D-5 produces a pulse with each. 08 S A signal ending with the end PIL signal -which occurs 0 As after S A. Likewise, flip-flop D-9 produces a negative 0 pts pulse with every. 05 S A signal. The pulses from the two flip-flops are logically ORed by NAND gate C to provide the PIL to the computer. Cards /, a schematic of which is shown below, are level shifting cards providing level shifting of the 0+5, TTL signals present at the digital output Elco (TTL) to 3-C, 0-6 logic levels which are then made available to the outside world at the 3-C digital output Elco connector. Power of -8 V from the computer is supplied through the Elco.

10 I 7-9 SLOT SLOT # # I M IN +5 I K D-I _. al 8K -8V N K N9 OUT I - 6 V + 5 V I GND I IK IN 53-6 SLOT SLOT # #.05 I M M.0 S.0 S M M. 05 C M.08S C S 8 0M..I S 0M 0M. S M. S M- 9. S 0 I H. 8S H I S H 5 B - 8H S 0H 8S - 0S 0 S PI L 0S - SPARE 05 0S SPARE IA B C D PLACE TWO CIRCUITS TO AN>. E F HJ IC SPACE K L MN Li r Z - A -I -8V +5V GND NRAO STANDARD TIME CLOCK COMPUTER BUFFER CARD -# / FIG.

11 - 0 - The main frame circuits schematic is shown below showing the control switch circuits and power supply circuits. A Lambda hybrid regulator drops the battery/charger voltage to +5 V DC for the logic. The Acopian 5 volt/3 amp supply is adjusted to about 3.5 V DC for charging the battery if one is used. When power interrupts the battery will discharge until power resumes. The Acopian supply current limits at about 3 amps until a battery terminal voltage of about 3. 5 volts results at which time the current tapers off to nearly zero current replacing only whatever current leaks due to self discharge. When adjusting the Acopian supply, the voltage must be measured at the battery connector. GND CARD 3 PIN A SET -I- -.T-- SET MANUAL 0 ARM SET TRIGGER SAFE CARD 3 PIN Y MV 50 5 / RED ARM CARD 3 PIN 00 GREEN CARD 3 0 RUN PIN -- : r 50 0 MV5 INTERRUPT SELECT I CARD 3 CARD 3 PIN V PIN U CARD 3 PIN LINE FUSE ACOPIAN or\p_ac ( +) OUT Al5MT300 BAT FUSE 5 VAC.5 AMP 5 AMP AC I5VDC 3 AMP GND ADJUT FOR OUT. VOLTS TO VOLT STORAGE BATTERY LAMBDA LAS 305 REGULATOR CARD PIN CARD < PIN A F > (+) >(-) 5V AUX. PWR, OUTPUT MAIN FRAME CIRCUITS

12 Conclusion The Acopian power supply has a current limit problem when power fails and is resumed after batteries have discharged to nearly zero volts, a start up problem results, since the "fold back" current limiter does not supply enough current to bring power back up. A fix was installed comprising a N 86 diode and 0 S/0 W resistor in series with the battery to limit the current to the battery during charging. In future designs a better AC power supply with less current limiting "fold back" may be employed. The PIL of 50 or 00 ms does not provide a fast enough interrupt to the computer to read the. 0 sec decade provided to the computer. Thus, a faster interrupt of about 0 ms should be considered. Credits Chassis Assembly and Wiring Dick Skaggs Circuit Card Assembly Randall Shears Gary Beverage John Hubbard Chassis Fabrication Boyd Wright

13 A BCDE F HJKL MNPR S TUVWXY CARD SLOT t\d I-. 00 W rn A B C D E FHJK LMNPRS TU CARD / SLOT A B C D E F He). K L MNPRS TUVWX CARD 3 SLOT t- A B C D E F H K LMNPR S TUVWXY Z CARD / SLOT

14 3 - WIRE LIST (HARNESS) Function Origin Hold Card 3 - Pin 0 Card - Pin 0 Reference Oscillator BNC V Trigger Pulse, +0 V BNC Ti-igger Pulse, -0 V BNC Buffered Trigger - Card -Pin Ten Carry J 0 ha L 3 7 gr a Y 3 Y Reset B H Seconds Carry Z. 08S A F 3 S. 05 S A E 3 T ENDPIL D 3 9 V CC - 3 Ground A, A 3 A, A Date Advance W BNC 0h C Card - Pin S Ground Lug A, Lug

15 - - WIRE LIST (THUMBWHEEL HARNESS) Function Orjita. To Unit Seconds Card Pin M Tens Seconds Unit Minutes Card 3 Pin C 3 D Tens Minutes Card 3 Pin H 3 J 3 K Unit Hours Card 3 Pin L 3 xi 3 N 8 3 P Tens Hours Card 3 Pin R All Decades Bussed Together s Card Pin X Y' s Ten Position, binary coded decimal, with s_epparate common to not-true bits Comms. X( 0) Y( 0) Dial Conn. to Terminals Positive Logic X = +5 thru R = 50 S

16 - 5 - WIRE LIST (TIME DISPLAY HARNESS - 3 AUGAT PLUGS) AB, CD, EFH (TWO WIRES ON ORIGIN PINS) Function 0 h 0 h 0 h +5 volts 80 h Colon D. P. Ground h h h +5 volts 8h Ground 0 m 0 m 0 m +5 volts 80 m Ground m m m +5 volts 8 m +5 volts s Ground 5 is 85 Ground D. P. 0 s 0. s 0. s 0. s 0 s 0. 8 S Ground 80 s 0 s To Augat AB Pin (Red) Aupt CD Pin (Red) Augat EFH Pin (Red) Card Pin C X Card 3 Pin

17 - 6 - WIRE LIST (TTL OUTPUT - ELCO HARNESS (38 PIN ELCO ) AND (PROTECTED PINS) (TWO WIRES ON ORIGIN PINS) Function Origin. 0 s Card Pin 3. 0 s. 0 s s 6. s. s 8. s 9. 8 s 0 s s s 3 8 s 0 s 5 0s 6 0s 7 80s 8 l m 3 3 m 3 m m m 3 7 0m 3 8 0m m 8 h 3 0 h 3 h 3 8 h 3 3 0h 3 0h C 0h 8 80h 8 PIL 6 Spare U +5 volts Elco Pin A J V X

18 - 7 - WIRE LIST (3-C LOGIC OUTPUT - ELCO HARNESS) (38 PIN ELCO (EXPOSED PINS) Function Qjg To. 0 s Card Pin 3 Elco Pin A. 0 s B. 0 s 5 C. 08 s 6 D. s 7 E. s 8 F. s 9 H.8 s 0 3 s K s L s 3 M 8 s N 0 s 5 P 0 s 6 R 0 s 7 S m Card Pin 3 T m U m 5 V 8 m 6 W 0 m 7 X 0m 8 Y 0m 9 Z h 0 a h b h c 8 h 3 d 0 h e 0h 5 f PIL 6 h Spare 7-8 volts Elco Pin p Card Pin Z 3 X Ground Eico Pin t Card A