Switched Capacitor Circuit Based Isolated Power Converters DISSERTATION

Transcription

1 Switched Capacitor Circuit Baed Iolated Power Converter DISSERTATION Preented in Partial Fulfillment of the Requirement for the Degree Doctor of Philoophy in the Graduate School of The Ohio State Univerity By Xuan Zhang Graduate Program in Electrical and Computer Science The Ohio State Univerity 6 Diertation Committee: Dr. Jin Wang, Advior Dr. ongya Xu Dr. Maheh S. Illindala Dr. Ajit Chaudhari, Graduate Faculty Repreentative

2 Copyright by Xuan Zhang 6

3 Abtract Power converter with galvanic iolation are ubiquitou in today world, covering a wide range of application. Traditionally, there are three general olution to achieve the galvanic iolation in power converter, including the magnetic field-baed iolation, electric field-baed iolation, and optic-baed iolation. Thi diertation tudie iolated power converter baed on witched capacitor (SC) circuit, aiming to achieve high power denity, high efficiency, and valid galvanic iolation performance that meet afety tandard. Thi work firt explore the integration of tranformer into SC circuit, in order to combine the benefit of both the tranformer and the SC circuit into a ingle circuit. A bidirectional quai-witched-capacitor (QSC) dc/ac circuit i therefore derived to replace traditional half bridge or full bridge circuit. The QSC dc/ac circuit feature galvanic iolation, oft-witching capability, and reduced voltage tre on paive and active component. The circuit operation principle and characteritic are dicued. Next, baed on the QSC dc/ac circuit, an iolated QSC pule-width-modulation (PWM) converter i propoed to erve a an auxiliary power upply in electric vehicle (EV) or hybrid electric vehicle (HEV), managing a bidirectional power flow between the high voltage (HV) battery and the low voltage (V) dc bu. Reduced voltage tre on witche and tranformer are reulted. A -kw converter prototype i built. The oft-witching peak ii

4 efficiency of the converter operating at 5 khz witching frequency i 96% for the buckmode operation, and 9% for the boot-mode operation. Then, the mall-ignal model and controller deign of the iolated QSC PWM converter are dicued. The mall-ignal model i derived by the method of tate-pace averaging, and it effectivene i howcaed by comparing it open-loop repone imulation reult to thoe of a detailed circuit model. For better line diturbance rejection, a cloed-loop voltage controller with feed-forward compenation i deigned. Experiment reult from the -kw prototype with digital control verified the effectivene of the cloed-loop voltage control. Next, an iolated QSC reonant converter i propoed for the iolated dc/dc converion in off-line power upply application. Full oft witching i achieved combining zero current witching (ZCS) on, near ZCS off, zero voltage witching (ZVS) on, and ZVS off within a wide load range, o the witching lo i minimized. A 9-W, 88-V/9-V, 7- khz prototype i built with -V enhancement-mode Gallium Nitride (egan) field-effect tranitor (FET). The prototype achieve a power denity of 7 W/inch3, and a flat efficiency curve with a peak value of 96 %. Furthermore, a 65-W, two-tage, off-line power adapter i deigned, where a 65-W, 38-V/9-V, -MHz iolated QSC reonant converter prototype i built with enhancement-mode GaN high electron mobility tranitor (HEMT). The 65-W QSC reonant converter prototype ha an etimated high efficiency of 97.5%, and a high power denity of 75 W/inch 3. At lat, a emiconductor-baed galvanic iolation olution for power converter i propoed. The iolation principle i fundamentally different from that of the traditional iii

5 olution, including the magnetic field-baed olution, electric field-baed olution, and optic-baed olution. It deliver the differential-mode (DM) load power via emiconductor witche during their ON tate, while utaining the common-mode (CM) voltage and blocking the CM leakage current with thoe witche during their OFF tate. Enabled by wide bandgap (WBG) power device and SC circuit, thi olution potentially reult in higher power denity compared with traditional galvanic iolation olution, and it can provide valid galvanic iolation performance that meet the afety tandard. The operation principle, reearch motive, deign challenge and olution are dicued in detail, repectively. A preliminary prototype i preented to howcae the DM power delivery performance and the CM iolation performance. Concluion and recommendation for future work are preented. iv

6 Dedication Thi document i dedicated to my family. v

7 Acknowledgment Firt of all I want to thank Prof. Jin Wang, my advior, for hi guidance, patience, encouragement, and upport during the coure of thi journey. Under hi guidance I have learned a lot in the field of power electronic, and I have learned how to conduct reearch. I really appreciate hi trut and upport for me to work on reearch freely. Above all, two key thing I learned from him will benefit my life and career forever: firt, alway be poitive and confident; and econd, alway be open minded and think out of box. My thank alo goe to the committee: Prof. ongya Xu, Prof. Maheh S. Illindala, and Prof. Ajit Chaudhari for their upport, advice, and direction. I would alo like to thank Prof. Fang uo for hi advice on my reearch and help in my life. Thank to Prof. Stephen Sebo for teaching me high voltage engineering and etting a role model a a life-long engineer and educator. My thank alo goe to Prof. Julia Zhang at the Oregon State Univerity, for her help, advice, and encouragement. I alo want to thank Dr. Jing Xu and Dr. iming iu at ABB Corporate Reearch Center, for their guidance and upport during my internhip in Raleigh. My thank alo goe to Dr. Chang Peng, M. Suxuan Guo, and Mr. Rui Gao at North Carolina State Univerity, for helping me in that ummer. Thank to Mr. Chengcheng Yao and Mr. He i for being my bet upport in both life and work throughout thee year. Thank to Dr. Cong i, Dr. Feng Guo, Dr. Mark Scott, vi

8 Mr. ixing Fu for accompanying me over the year a both cloe friend and colleague. I m very grateful to them all for helping me move forward, overcome the hardhip, and get through the darket day. I wouldn t have made it without them. Thank to my friend Dr. Ke Zou, Dr. Xiu Yao, Dr. ui Herrera, Mr. Mohammed Alolami, Mr. Jinzhu i, Mr. Da Jiao, Mr. Fanbo Zhang, M. Xintong v, M. Shuang Tan, Mr. Andong ang, Dr. inyu Zhu, Mr. Pengzhi Yang, M. Chaoran Han, Mr. Boxue Hu, M. Qing Jia, Mr. Zuo Wei, M. Gengyao i, Mr. Yingzhuo Chen, Mr. Karun Potty, Mr. John A. Brother, Mr. Ke Zhu, Mr. Mingzhi eng, Mr. ucheng Wen, Dr. Zhendong Zhang, Dr. Thoma Tai, M. Pu Xu, Mr. Cong Deng, Dr. Dakai Hu, Dr. Haiwei Cai, Dr. Yu iu, Mr. Miao Wang, Mr. Jianyu Pan, Mr. Feng Qi, Mr. Xiaotao Dong, Mr. Rachid Darbali Zamora, Mr. Marku Siever, Mr. Ernet Davidon, Mr. Hanning Tang, and Mr. Jizhou Jia for haring thi journey at the Ohio State Univerity. Thank you all for thoe joy and hared memorie. I will not forget all the day I wa embraced by your friendhip, help and upport. I would alo like to thank all the tudent who took ECE547 in 3, 4, and 5. Thank you all for making thi teaching experience fun, memorable, and rewarding. I own my deepet gratitude to my parent Gaoheng Zhang and in Zhang. Without your love and upport, I would not have been where I am today. vii

9 Vita June 8...B.S. Electrical Engineering, Huazhong Univerity of Science and Technology June...M.S. Electrical Engineering, Huazhong Univerity of Science and Technology Sept. to preent...ph.d. tudent, Electrical Engineering, The Ohio State Univerity Publication [] X. Zhang, C. Yao, C. i,. Fu, F. Guo, and J. Wang, "A Wide Bandgap Device- Baed Iolated Quai-Switched-Capacitor DC/DC Converter," IEEE Tran. Power Electron., vol. 9, no. 5, pp. 5-5, May 4. [] X. Zhang, C. Yao, and J. Wang, "A Quai-Switched-Capacitor Reonant Converter," IEEE Tran. Power Electron. (Accepted). [3] F. Guo,. Fu, X. Zhang, C. Yao, H. i, and J. Wang, "A Family of Quai-Switched- Capacitor Circuit baed Dual Input DC/DC Converter for Photovoltaic Sytem Integrated with Battery Energy Storage," IEEE Tran. Power Electron. (Accepted). viii

10 [4] M. J. Scott,. Fu, X. Zhang, J. i, C. Yao, M. Siever, and J. Wang, Merit of Gallium Nitride Power Converion, IOP Semiconductor Science and Technology, vol. 8, no 7, Jun. 3. [5] X. Zhang, H. i, J. A. Brother,. Fu, J. Wang, M. Perale, and J. Wu, A 5-kV SiC MOSFET Gate Drive with Power-over-Fiber baed Iolated Power Supply and Comprehenive Protection Function, IEEE Journal of Emerging and Selected Topic in Power Electronic (in review). [6] H. i, X. Zhang,. Wen, C. Yao, C. Han, J. Wang,. iu, and J. Puukko, " High Voltage Cacode GaN HEMT in Parallel Operation," IEEE Journal of Emerging and Selected Topic in Power Electronic (Accepted). [7] X. Zhang, C. Yao, M. J. Scott, E. Davidon, J. i, P. Xu, and J. Wang, A GaN Tranitor baed 9W Iolated Quai-Switched-Capacitor DC/DC Converter for AC/DC Adaptor Proc. IEEE Workhop on Wide Bandgap Power Device and Application (WIPDA 3), pp. 5-, Oct. 3. [8] X. Zhang, C. Yao, F. Guo, and J. Wang, Revere Power Flow Study of an Iolated Quai-Switched-Capacitor DC/DC Converter for Automotive Application Proc. IEEE Int. Midwet Sympoium on Circuit and Sytem (MWCAS 3), pp. 4-44, Aug. 3. [9] X. Zhang, C. Yao, F. Guo, C. i,. Fu, C. Deng, and J. Wang, "Soft Switching, Frequency Control, and Bidirectional Power Flow of an Iolated Quai-Switched- Capacitor DC/DC Converter for Automotive Application," Proc. IEEE Energy Converion Congre and Expo (ECCE 3), pp , Sep., 3. ix

11 [] X. Zhang, C. i, C. Yao,. Fu, F. Guo and J. Wang, "An Iolated DC/DC Converter with Reduced Number of Switche and Voltage Stree for Electric and Hybrid Electric Vehicle," Proc. IEEE Applied Power Electronic Conference and Expo (APEC 3), pp , March 7-, 3. [] X. Zhang, C. Yao, F. Guo, and J. Wang, Efficiency Improvement of the Quai- Switched-Capacitor Reonant Converter with Optimal Operation and Burt-mode Control Proc. IEEE Energy Converion Congre and Expo (ECCE 4), pp , Sep., 4. [] X. Zhang, F. Guo, C. Yao, P. Xu, and J. Wang, Small-ignal Modeling and Controller Deign of an Iolated Quai-Switched-Capacitor DC/DC Converter Proc. IEEE Appl. Power Electron. Conf. Expo. (APEC 4), pp. 3-38, March 6-, 4. [3] X. Zhang, C. Yao, M. Siever, P. Xu, M. J. Scott, E. Davidon, and J. Wang, A GaN Tranitor baed 9W AC/DC Adapter with a Buck-PFC Stage and an Iolated Quai-Switched-Capacitor DC/DC Stage Proc. IEEE Appl. Power Electron. Conf. Expo. (APEC 4), pp. 9-6, March 6-, 4. [4] F. Guo,. Fu, X. Zhang, and J. Wang, A Family of Dual-Input dc/dc converter baed on Quai-Switched-Capacitor Circuit Proc. IEEE Energy Converion Congre and Expo (ECCE 4), pp , Sep. 4-8, 4. [5] C. i, C. Yao, X. Zhang, F. Guo, A. ang, H. iu, S. Shan, and J. Wang, An Iolated Hybrid Switched -C dc-dc Circuit with High Step-up Ratio and Reduced Switch x

12 Voltage Stre Proc. IEEE Energy Converion Congre and Expo (ECCE 4), pp , Sep, 4. [6]. Fu, X. Zhang, M. Scott, C. Yao, and J. Wang, The Evaluation and Application of Wide Bandgap Power Device Proc. IEEE Tranportation Electrification Conference Aia-Pacific (ITEC 4), pp. -5, Sep, 4. [7] X. Zhang, C. Yao, F. Guo,. Fu, and J. Wang, A Family of Quai-Switched- Capacitor Converter Proc. IEEE Tranportation Electrification Conference Aia- Pacific (ITEC 4), pp. -6, Sep, 4. [8] X. Zhang,. Fu, M. eng and J. Wang, Dicuion on the Semiconductor-baed Galvanic Iolation Proc. IEEE Workhop on Wide Bandgap Power Device and Application (WIPDA 4), pp. 75-8, Oct, 4. [9]. Fu, X. Zhang, H. i, X. u, and J. Wang, The development of a high-voltage power device evaluation platform, Proc. IEEE Workhop on Wide Bandgap Power Device and Application (WIPDA 4), pp. 3-7, Oct, 4. [] F. Guo,. Fu, H. i, M. Alolami, X. Zhang, and J. Wang, A full-bridge currentource iolated DC/DC converter with reduced number of witche and voltage tree for Photovoltaic application, Proc. IEEE Workhop on Wide Bandgap Power Device and Application (WIPDA 4), pp , Oct, 4. []. Fu, X. Zhang, F. Guo and J. Wang, A Phae-hift Controlled Current-fed Quaiwitched-capacitor Dc/dc Converter with GaN HEMT for Photovoltaic Application, Proc. IEEE Applied Power Electronic Conf. and Expo. (APEC 5), pp. 9-98, Mar. 5. xi

13 [] M. Scott,. Fu, C. Yao, X. Zhang, R. Darbali, J. Wang, and. Xu Deign Conideration for Wide Bandgap Baed Motor Drive Sytem, IEEE International Electric Vehicle Conference (IEVC 4), pp. -6, Dec. 4. [3] F. Guo,. Fu, H. i, M. Alolami, X. Zhang, J. Wang, and J. Zhang, A dual-input full-bridge current-ource iolated DC/DC converter baed on Quai-Switched- Capacitor circuit for Photovoltaic ytem with energy torage, Proc. IEEE Applied Power Electronic Conference and Expo (APEC 5), pp , Mar. 4. [4] C. Yao, W. i, H. i, C. Han, M. Wang, Z. Qian, X. Zhang, F. uo, and J. Wang, Common-mode Noie Comparion Study for ateral Wire-bonded and Vertically Integrated Power Module, Proc. IEEE Energy Converion Congre and Expo (ECCE 5), pp , Mar. 4. [5] X. Zhang, H i, C. Yao, and J. Wang, Semiconductor-Baed Galvanic Iolation, IEEE Workhop on Wide Bandgap Power Device and Application (WIPDA 5), pp , Oct, 5. [6] H. i, C. Han, J. A. Brother, K. Zhu, X. Zhang, and J. Wang, Evaluation of 6 V GaN Gate Injection Tranitor Static and Dynamic Performance under Elevated Temperature, IEEE Workhop on Wide Bandgap Power Device and Application (WIPDA 5), pp. 85-9, Oct, 5. [7] X. Zhang, H. i, J. A. Brother,. Fu, and J. Wang, A 5-kV SiC MOSFET Gate Drive with Power-over-Fiber baed Iolated Power Supply and Comprehenive Protection Function, IEEE Applied Power Electronic Conference and Expo (APEC 6), Mar. 6. (Accepted) xii

14 [8] H. i, X. Zhang,. Wen, J. A. Brother, C. Yao, and J. Wang, Evaluation of High Voltage Cacode GaN HEMT in Parallel Operation, IEEE Applied Power Electronic Conference and Expo (APEC 6), Mar. 6. (Accepted) Field of Study Major Field: Electrical and Computer Engineering xiii

15 Table of Content Abtract... ii Dedication... v Acknowledgment... vi Vita... viii Publication... viii Field of Study... xiii Table of Content... xiv it of Table... xx it of Figure... xxii Chapter. Introduction..... Power Converter with Galvanic Iolation..... Tranformer Baed Iolated DC/DC Power Converter Switched-Capacitor Circuit Motivation of thi Work Outline of thi Diertation... Chapter. QSC DC/AC Circuit and Iolated QSC PWM Converter... 3 xiv

16 .. QSC DC/AC Circuit Circuit Decription and Operation Principle Dc Characteritic Iolated QSC PWM Converter Circuit Decription Buck-mode, Hard-witching Operation Principle Buck-mode, Hard-witching Operation Dc Characteritic Buck-mode, Soft-witching Operation Principle and Criteria Boot-mode, Soft-witching Operation Principle and Criteria Deign Guideline for the Key Circuit Parameter Capacitance of C and C Tranformer Dc-bia Flux Denity Average Current of and Simulation Verification, Prototype Deign and Experimental Reult Simulation Verification Prototype Deign and Tet Decription Experimental Reult Concluion xv

17 Chapter 3. Small-ignal Model and Controller Deign of the Iolated QSC PWM Converter Control Method Decription Small-ignal Model of the Iolated QSC PWM Converter Switching-mode Equivalent Circuit Decription and Small-ignal Modeling Simulation Verification of the Small-ignal Model Controller Deign of the Iolated QSC DC/DC Converter Controller Deign Cloed-loop Simulation Verification Experimental Verification Experimental Setup Decription Experimental Reult Concluion... 6 Chapter 4. Iolated QSC Reonant Converter Application Background Circuit Decription and Operation Principle Circuit Feature and Operation Principle Optimal Duty Ratio and Switching Frequency... 7 xvi

18 4..3. Burt-mode Operation for Improved ight-load Efficiency Prototype Deign Planar Tranformer Deign PCB ayout Output Rectifier W Prototype Gate-drive Circuit Power Supply Simulation and Experimental Verification Simulation and Experimental Reult of the 9-W Prototype Preliminary Simulation Reult of the 65-W Prototype Concluion Chapter 5. Semiconductor-baed Galvanic Iolation Galvanic Iolation Requirement in the Safety Standard IEC Inulation Voltage Requirement Touch Current and Protective Conductor Current Requirement Background of Exiting Galvanic Iolation Solution and Reearch Motive imitation of Magnetic Field-Baed Galvanic Iolation imitation of Electric Field-Baed Galvanic Iolation imitation of Optic-Baed Galvanic Iolation xvii

19 5..4. imitation of Tranformerle Grid-tied Inverter Semiconductor-baed Galvanic Iolation Baic Circuit Structure and Potential Benefit: Challenge CM eakage Current Analyi Iolation Voltage Stre in Off-line Power Supplie Generation mechanim of the CM leakage current Quantitative analyi of the TC TC Reduction Approache Increaing the CM Impedance Bypaing the TC Preventing the TC Generation Partially Compenating the Switch Co Charging Current Extended Topologie with Semiconductor-baed Galvanic Iolation Iolated DC/DC Converter with a High Voltage Tranfer Ratio Iolated DC/DC Converter with Extended Iolation Voltage Iolated DC/DC Converter with a Voltage Regulation Function Iolated AC/DC converter and Iolated DC/AC converter Deign toward High Efficiency and High Power Denity xviii

20 5.7.. Switche Switching Frequency Paive Component Preliminary Prototype and Experimental Verification DM power delivery tet TC Meaurement Tet of the TC Reduction Circuit Concluion Chapter 6. Concluion and Future Work Concluion Recommendation for Future Work... 5 Reference xix

21 it of Table Table.. Converter pecification for the buck-mode, hard-witching operation imulation of the iolated QSC PWM converter... 3 Table.. Converter pecification for the boot-mode, hard-witching operation imulation of the iolated QSC PWM converter... 3 Table.3. Sepcification of the kw prototype of the iolated QSC PWM converter.. 33 Table 3.. Circuit parameter for the open-loop imulation of the iolated QSC PWM converter in repone to a input voltage diturbance Table 3.. Circuit parameter for the open-loop imulation of the iolated QSC PWM converter in repone to a witching frequency diturbance Table 3.3. Circuit parameter for the cloed-loop imulation of the iolated QSC PWM converter Table 4.. Specification for the imulation model and experimental prototype of the 9- W, 88-V/9-V, 7-kHz, iolated QSC reonant converter... 8 Table 5.. Power denitie and energy denitie of the tate-of-the-art capacitor and inductor Table 5.. Simulation parameter for tudying the impact of Co on ITC (embodied a the output votlage of ZTC) in the baic SC iolation cell circuit.... xx

22 Table 5.3. Simulation parameter for tudying the impact of fw on ITC (embodied a the output voltage of ZTC) in the baic SC iolation cell circuit.... Table 5.4. Simulation parameter for tudying the impact of fw on the ITC (embodied a the output voltage of ZTC) in the baic SC iolation cell circuit Table 5.5. Simulation parameter for the hunt current ource olution to reduce the TC of the baic SC iolation cell circuit Table 5.6. Comparion between critical parameter of tate-of-the-art SiC MOSFET v. Si MOSFET/IGBT Table 5.7. Specification of the preliminary SC iolation cell circuit prototype xxi

23 it of Figure Figure.. Magnetic field-baed galvanic iolation olution.... Figure.. Electric field-baed galvanic iolation olution Figure.. Propoed QSC dc/ac circuit Figure.. Operation waveform of the QSC dc/ac circuit Figure.3. Steady-tate Idc_ of the propoed QSC dc/ac circuit... 7 Figure.4. Schematic of the propoed iolated QSC PWM converter Figure.5. Equivalent circuit of the propoed iolated QSC PWM converter Figure.6. Buck-mode, hard-witching operation waveform of the iolated QSC PWM converter.... Figure.7. Switching mode diagram of the Buck-mode, hard-witching operation in one witching cycle: (a) Mode : Current path between t-t, (b) Mode : Current path between t-t3, (c) Mode 3: Current path between t3-t4, (d) Mode 4: Current path between t4-t5, (e) Mode 5: Current path between t5-t6, (f) Mode 6: Current path between t6-t7, (g) Mode 7: Current path between t7-t8, (h) Mode 8: Current path between t8-t9. (one cycle complete).... Figure.8. Buck-mode, oft-witching operation waveform of the iolated QSC PWM converter xxii

24 Figure.9. Boot-mode, oft-witching operation waveform of the iolated QSC PWM converter Figure.. Steady-tate imulation waveform of the buck-mode, hard-witching operation of the iolated QSC PWM converter Figure.. Steady-tate imulation waveform of the boot-mode, oft-witching operation of the iolated QSC PWM converter Figure.. kw prototype of the iolated QSC PWM converter Figure.3. (a) Experimental reult of the buck-mode, hard-witching operation, (b) Experimental reult of the boot-mode, oft-witching operation Figure.4. Experimental reult of the buck-mode, oft-witching operation. (a) Drainto-ource voltage of S and S, the voltage and current of the tranformer HV-ide winding, (b) Gate ignal and drain-to-ource voltage of S and S Figure.5. Experimental drain-to-ource voltage waveform of S, S, S3 and S4 in the (a) buck-mode, oft-witching operation, and (b) boot-mode, oft-witching operation. 37 Figure.6. (a) Efficiency curve with unfixed HV-dc-bu voltage. (b) Hard-witching operation efficiency curve with fixed HV-dc-bu voltage. Continued Figure 3.. The t witching-mode equivalent circuit during the interval t4-t Figure 3.. The nd witching-mode equivalent circuit during the interval t-t Figure 3.3. The 3 rd witching-mode equivalent circuit during the interval t-t Figure 3.4. The 4 th witching-mode equivalent circuit during the interval t3-t Figure 3.5. Open-loop imulation reult from the mall-ignal model built in Matlab and the detailed circuit model built in PSIM in repone to an input voltage diturbance xxiii

25 Figure 3.6. Open-loop imulation reult from the mall-ignal model built in Matlab and the detailed circuit model built in PSIM in repone to a witching frequency diturbance Figure 3.7. Pole-zero map of the tranfer function: (a) Gvg(), and (b) Gvδ() Figure 3.8. Block diagram of the iolated QSC PWM converter Figure 3.9. Cloed-loop imulation reult from the mall-ignal model and the detailed circuit model in repone to an input voltage diturbance Figure 3.. Simulation reult of the open-loop repone, cloed-loop repone with and without feed-forward compenation of the mall-ignal model in repone to a diturbance of the input voltage Figure 3.. Function block of the digital control implemented in DSP Figure 3.. Cloed-loop experiment waveform with a -V input voltage tep change Figure 3.3. Zoomed-in cloed-loop experiment waveform of Fig. 8 at t=-43. m, Vin=9 V, f=8 khz Figure 3.4. Zoomed-in cloed-loop experiment waveform of Fig. 8 at t=34 m, Vin= V, f=5 khz Figure 4.. Equivalent circuit of the iolated QSC reonant converter. C, C3 and C4 are the witched capacitor; and m are the tranformer leakage inductance and magnetizing inductance; and o and Co compoe the output filter. To analyze all witching tranient within one witching cycle, the output capacitance of all the witche (Co and Co) mut be taken into conideration xxiv

26 Figure 4.. Operation waveform of the iolated QSC reonant converter. Two type of reonance are utilized in operation, which exit in the active witching mode and deadtime mode repectively. A reult, ZCS on and near ZCS off are achieved during the active witching mode, while ZVS on and off are achieved during the dead-time mode Figure 4.3. The witching-mode diagram of the continou operation in one witching cycle, including: (a) Mode : current path between t - t, (b) Mode : current path between t - t, (c) Mode 3: current path between t - t3, (d) Mode 4: current path between t3 - t4, (e) Mode 5: current path between t4 - t5, (f) Mode 6: current path between t5 - t6, (g) Mode 7: current path between t6 t7, (h) Mode 8: current path between t7 t8 (one witching cycle complete). Continued Figure 4.4. The equivalent reonant path after aplace tranformation to denote the firt type of reonance happening during the active witching mode, including (a) Mode and, and (b) Mode 5 and 6. Such reonance caue reonant withcing current and thu reult in ZCS on and near ZCS off for all the witche Figure 4.5. The equivalent reonant path after aplace tranformation to denote the econd type of reonance during the dead-time witching mode, including Mode 3 and 7. Such reonnace recycle the energy in witch output capacitance which otherwie would be lot in the ZCS operation, and thu reult in ZVS on and off for all the witche Figure 4.6. (a) Normal-mode operation and (b) burt-mode operation for the light-load condition Figure 4.7. The two-tage trucutre of the 65-W power adapter for laptop xxv

27 Figure 4.8. (a) ANSYS Maxwell 3D imulation model of the ideal planar tranformer without termination and (b) the interleaving winding tructure Figure 4.9. (a) Detailed imulation model of the planar tranformer built in ANSYS Q3D Extractor for termination inductance analyi, (b) Interleaving via of the palanr tranformer Figure 4.. Optimal PCB layout of the witched capacitor and witche for reduced high frequency paraitic inductance and reitance in the power loop of the converter Figure 4.. A 9-W, 88-V/9-V, 7-kHz, iolated QSC reonant converter prototype Figure 4.. (a) PCB layout and (b) prototype of a 65-W, 38-V/9-V, -MHz iolated QSC reonant converter erving a the dc/dc tage of the 65-W power adapter for laptop Figure 4.3. Auxilary winding configuration to provide power for the gate-drive circuti in continou operation of the power adatper Figure 4.4. (a) The imulation waveform and (b) the experimental waveform of the voltage acro the witche (Vd_S, Vd_S, Vd_S3), the tranformer primary-ide winding voltage (Van), the tranformer primary-ide winding current (I_), and tranformer primary-ide-referred magnetizing inductor current (I_m). All waveform are recorded in the operation condition: Vin=88 V, Po=9 W, Dw=.47, and fw=9 khz. Baed on the analyi, in thi cae the Dw and fw are not optimized, o ZVS on and off are not achieved xxvi

28 Figure 4.5. (a) The imulation waveform and (b) the experimental waveform of the voltage acro the witche (Vd_S, Vd_S, Vd_S3), the tranformer primary-ide winding voltage (Van), the tranformer primary-ide winding current (I_), and tranformer primary-ide-referred magnetizing inductor current (I_m). All waveform are recorded in the operation condition: Vin=88 V, Po=9 W, Dw=.3, and fw=7 khz. Baed on the analyi, in thi cae the Dw and fw are optimized, o ZVS on and off are achieved Figure 4.6. Burt-mode operation imulation reult of the iolated QSC reonant converter Figure 4.7. Burt-mode operation experimental reult of the iolated QSC reonant converter Figure 4.8. Power lo and efficiency reult of the prototype, in comparion between the operation with and witout optimized Dw and fw Figure 4.9. Steady-tate imulation waveform of the 65-W, 38-V/9-V, iolated QSC reonant converter Figure 5.. Touch current from a floating circuit (with unearthed output) [4] Figure 5.. TC meauring intrument an impedance network to roughly imulate a human body [4] Figure 5.3. (a) Baic idea of the emiconductor-baed iolation; and (b) an example of the ac witch with bidirectional blocking capability Figure 5.4. The SC iolation cell circuit -- a baic topology of the dc/dc converter with emiconductor-baed galvanic iolation (all witche are ac witche with bidirectional blocking capability).... xxvii

29 Figure 5.5. DM and CM current flow in the SC iolation cell circuit in (a) Phae I, and (b) Phae II.... Figure 5.6. An off-line power upply application of the emiconductor-baed iolation.... Figure 5.7. Iolation voltage acro the iolated dc/dc tage in off-line power upplie with a Boot PFC circuit. (a) and (b) are during the poitive half line cycle where the line input voltage i poitive; (c) and (d) are during the negative half line cycle where the line input voltage i negative. Continued... 4 Figure 5.8. Iolation voltage acro the iolated dc/dc tage in a Boot-PFC baed, Cla- I, off-line power upply with an earthed output negative rail Figure 5.9. Iolation voltage acro the iolated dc/dc tage in off-line power upplie with a Totem-pole PFC circuit. (a) and (b) are during the poitive half line cycle where the line input voltage i poitive; (c) and (d) are during the negative half line cycle where the line input voltage i negative Figure 5.. Iolation voltage acro the iolated dc/dc tage in a Totem-Pole PFC baed, Cla-I, off-line power upply with an earthed output ground Figure 5.. CM leakage current generation mechanim at every turn-on event (of S3 for example) Figure 5.. TC equivalent circuit and the accumulated TC profile, in a Boot-PFC baed off-line power upply, when a human body touche the output ground (the circuit parameter are extracted in thi cae tudy, auming.7-kv SiC MOSFET CM7D) xxviii

30 Figure 5.3. The calculated ITC at a ingle turnning-on event with different value of Co and tray at VTC=7 Vdc.... Figure 5.4. RMS value of the ZTC output voltage in the imulation of the baic SC iolation cell circuit. The equivalent circuit i hown in Fig. 5. and the circuit parameter etting lited are in Table Figure 5.5. RMS value of the ZTC output voltage in the imulation of the baic SC iolation cell circuit. The equivalent circuit i hown in Fig. 5. and the circuit parameter etting are lited in Table Figure 5.6. RMS value of the ZTC output voltage in the imulation of the baic SC iolation cell circuit. The equivalent circuit i hown in Fig. 5. and the circuit parameter etting are lited in Table Figure 5.7. Unymmetrical CM conduction path caued by the diagonal connection between the CM voltage ource and the ZTC, with Y capacitor added at the output. Thi reult in additional TC caued by the DM power delivery Figure 5.8. Adding a hunt current ource in parallel with the converter to bypa the ITC from the ZTC Figure 5.9. Simulation reult (a) before and (b) after adding a hunt current ource to bypa the TC from the ZTC Figure 5.. Operation waveform (a) before and (b) after implementing the ZVS operation to prevent the TC generation Figure 5.. The olution to manually force ZVS operation by adding bidirectional current-ource circuit in the gate drive to charge or dicharge the witch Co xxix

31 Figure 5.. Equivalent circuit to manually force ZVS operation with bidirectional current-ource circuit in the gate drive to charge or dicharge the witch Co.... Figure 5.3. The firt cae tudied to implement forced ZVS operation. It i only to charge two witche (S3 and S4) during the deadtime, without charging or dicharging any other witche. The imulation reult how that additional TC i generated.... Figure 5.4. The econd cae tudied to implement forced ZVS operation. It i to charge two group of witche together, without dicharging any other witche. The reult how additional TC i generated.... Figure 5.5. The third cae tudied to implement forced ZVS operation. It i to charge two group of witche together, while dicharging their complementary witche. The reult how the voltage acro the witche i fully tranferred, and the TC i eliminated Figure 5.6. Example of a witching-type current ource circuit, baed on a bidirectional boot converter Figure 5.7. Example of a unidirectional, linear-type current ource circuit Figure 5.8. Example of a witching-type current ource circuit baed on the buck-boot converter, with the current flow ignified at the S turn-on event Figure 5.9. Operation of waveform of the buck-boot current ource circuit Figure 5.3. Operation waveform of the buck-boot current ource circuit Figure 5.3. (a) A 3X iolated boot dc/dc converter (where all witche are ac witche with bidirectional blocking) and (b) the two witching phae of the converter xxx

32 Figure 5.3. (a) A 4X iolated Dickon converter, and (b) the equivalent circuit of the two witching phae Figure (a) Iolated dc/dc converter with extended iolation voltage and the inulation tet chematic; (b) enabling ignal of the SC iolation cell (n=3, for example) Figure An iolated buck-boot dc/dc converter with a voltage regulation function (all witche are ac witche with bidirectional blocking capability) Figure Two-tage tructure of an ac/dc converter Figure Two-tage tructure of a dc/ac converter Figure Two DM current pattern including (a) the hard-witching current pattern, and (b) the reonant current pattern with ZCS on and off Figure A preliminary 4-V, 4-W prototype of the SC iolation cell circuit Figure Experimental waveform of the DM power delivery at -W output power Figure 5.4. Experimental DM power delivery efficiency of the prototype Figure 5.4. TC tet of the ioaltion cell circuit prototype in an off-line power upply application Figure 5.4. Experimental reult of the TC meaurement with a -Vrm CM voltage ource. The weighted touch current reult i.4 ma, which meet the IEC695 tandard requirement (.5 ma) Figure Auxliary current-ource circuit to partially compenating the current for charging the witch Co at the turn-on tranient xxxi

33 Figure Tet waveform of the auxliary current-ource circuit xxxii

34 Chapter. Introduction.. Power Converter with Galvanic Iolation Since the 83 when Michael Faraday and Joeph Henry dicovered electromagnetic induction independently, which laid the foundation for the following invention of the tranformer in the 87, the hitory of reearch on power converion with galvanic iolation ha progreed. After over a century of evolution, power converter with galvanic iolation have become ubiquitou in today world, covering a wide range of application. Typical example include variou off-line power upplie for laptop and dektop, ED driver, vehicle on-board charger, photovoltaic inverter, wirele power tranfer, energy torage ytem and micro grid, and power converter for utility application uch a olidtate tranformer. Galvanic iolation i the principle of iolating functional electrical ubytem to prevent common-mode (CM) current flow. However, in the meantime, the differentialmode (DM) energy or information till can be exchanged between the ubytem. The reaon for galvanic iolation are manifold, including: ) uer afety - preventing accidental current from reaching ground through a human body; ) breaking the ground loop when connecting electrical ubytem with different ground reference; and 3) confining and uppreing the CM noie, which caue malfunction in the DM energy or information exchange. Mot off-line power converter are enforced to provide galvanic

35 iolation according to the indutry afety tandard (e.g., IEC695), where the tet method with emphai on CM iolation voltage and CM leakage current are well defined. Traditionally, there are three general olution to achieve the galvanic iolation in power converter, including: ) Magnetic field-baed galvanic iolation: Thi olution achieve galvanic iolation by an air/magnetic-core tranformer. In thi olution, a hown in Fig.., the DM load power i delivered via the magnetic field etablihed between the eparate tranformer winding. Meanwhile, the tranformer effectively block the CM leakage current, with high CM impedance provided by the low paraitic CM capacitance acro the winding. Mot power converion ytem achieve galvanic iolation with thi olution, and a well-known example i the iolated dc/dc power converter widely applied in variou application. Tranformer Galvanic Iolation Barrier Sytem Section Sytem Section CM Source DM Power or Information Flow Winding Paraitic Capacitance CM eakage Current Ground-loop Impedance Figure.. Magnetic field-baed galvanic iolation olution. ) Electric field-baed galvanic iolation: Thi olution achieve galvanic iolation by employing ac-coupling iolation capacitor with low capacitance (in the pf~nf range)

36 to replace the tranformer [-3]. Thee capacitor can be either dicrete capacitor, or electrode pair with an inulator or emiconductor a the dielectric. A hown in Fig.., thee iolation capacitor reonate with connected inductor to provide low impedance at high reonance frequency, o the DM load power flow around uch frequency i delivered efficiently via the electric field etablihed within the capacitor. Meanwhile, a thee iolation capacitor perform high impedance at low frequency, the dc or line-frequency CM leakage current are effectively blocked. Thi olution ha been applied in grid-tied power converion application including the ED driver [-4], battery charger [5-7], and power upply for liquid terilization [8]. Traditionally, electric field-baed galvanic iolation i alo applied in iolated data tranfer application, uch a the digital iolator [9- ] and iolated gate drive [-3]. In uch application, high CM impedance i required and embodied a a CM tranient immunity (CMTI) ratio to block CM noie in the preence of high CM dv/dt (e. g. 5 kv/µ). Sytem Section Reonant Inductor Galvanic Iolation Barrier Sytem Section DM Power or Information Flow Iolation Capacitor CM Source CM eakage Current Ground-loop Impedance Figure.. Electric field-baed galvanic iolation olution. 3

37 3) Optic baed galvanic iolation: Thi olution achieve galvanic iolation by decoupling the electrical ytem with optic. It deliver the DM load power via light from the light emitter to the light receiver. Superior CM impedance and CM noie immunity can be achieved becaue of the low paraitic capacitance (multi-pf) coupling the light emitter and receiver. Thi olution i applied primarily in low-power (up to hundred of mw) iolated data tranfer over fiber optic or optocoupler [4-5]. Recently, it application ha extended to the iolated power tranfer within the power range up to 7 W [6], for iolated gate-drive power upply [7] and power upply for conumer quadcopter [6]... Tranformer Baed Iolated DC/DC Power Converter To date, tranformer baed iolated dc/dc power converter are till the mot widely employed olution to achieve galvanic iolation. For grid-tied application, a linefrequency tranformer can be added at the grid interface, but it large volume and heavy weight caue low power denity. To improve the ytem power denity and reduce the ytem cot, iolated dc/dc converter with high-frequency tranformer are employed in increaingly in application. Magnetic-core tranformer with high permeability material (e.g., Mn-Zn ferrite) generally are applied in iolated dc/dc converter in the witching frequency region between multi-khz and multi-mhz. Typical application example include: iolated dc/dc power converter [8-9]; energy torage ytem and dc micro grid [-]; ac-ac converter [3-4]; olid-tate tranformer [5-7]; off-line power upplie [8-9]; ED driver [3-3]; vehicle on-board charger [33-36]; photovoltaic inverter [37-4]; iolated enor [4-43]; digital ignal iolator [44-46]; iolated gate 4

38 drive [47-49]; wirele power tranfer [5-5]; and iolated PCB-mount dc/dc converter [53-55]. Air-core tranformer have low permeability and thu are le effective to confine the magnetic field within a limited pace. For thi reaon, it i ued primarily for longditance wirele power tranfer application. However, in the very-high-frequency (VHF) (i.e., 3-3 MHz) witching-frequency region, air-core inductor or magnetic-core inductor with low-permeability radio-frequency (RF) magnetic material (for core lo reduction) are built to achieve improved converter power denity [56-58]. The development of the iolated dc/dc power converter i driven continuouly by the ever-ecalating market demand for further improvement in efficiency, reduction of phyical ize and weight, and increae in maximum operating temperature. Wide bandgap (WBG) power device, uch a Silicon Carbide (SiC) and Gallium Nitride (GaN) device, are developed and applied to fulfill thee emerging market need. Compared with Silicon device, the 3X wider bandgap of WBG device enable them to operate under greater voltage tre per channel length, at higher temperature, while witching at fater peed and cauing lower power lo. All of thee attribute indicate that, by uing WBG device, maller and more efficient power converter can be realized [59-63]. To maximize the benefit of WBG device, low-voltage rating of the device i preferred. Thi i becaue low-voltage rated device are more efficient, a they have better figure of merit, which i the product of the on-reitance and the total gate charge [64-65]. However, mot iolated dc/dc power converter in off-line power upplie and grid-tied inverter are built with traditional topologie, which impoe high voltage tre ( dc-bu 5

39 voltage) on witche. For low-power application with the power rating below 9 W (e.g., the 65-W ac/dc power adapter), flyback converter and VHF reonant converter (e.g., the Φ reonant converter) are the main-tream topologie employed [66-76]. For application with higher power rating between 9 W and a few hundred of kw (e.g., the level-ii vehicle on-board charger, the off-line power upplie above 9 W, and the olid-tate tranformer for utility application), half-bridge or full-bridge circuit baed dual-activebridge (DAB) PWM converter and C reonant converter are the tandard topologie mot widely employed [8-4]. In practice, off-line power upplie and grid-tied inverter are commonly deigned with a 4 V dc-bu voltage, o all the aforementioned traditional topologie require high-voltage (e.g., 6 V) rated device, which i neither energy efficient nor power-denity optimized. Multi-level converter (in particular the modular multi-level inverter [77]) feature reduced voltage tre on witche, and they have been ued with good ucce in highefficiency, high-voltage utility application. However, they typically have not been employed in lower voltage (i.e., < 6 V) application uch a grid-tied inverter and rectifier, or dc-dc converion, becaue of their control complexity, limited power denity due to a large number of active witche and paive component. To enable the wider ue of low-voltage WBG device within a imple tructure of the tranformer baed iolated dc/dc power converter, new circuit topologie that can reduce the witch voltage tre are needed. 6

40 .3. Switched-Capacitor Circuit Switched-capacitor (SC) circuit contain only witching device and capacitor. The abence of magnetic component help to hrink the ytem volume and cot. To date, magnetic component till perform energy denitie that are order of magnitude lower than thoe of capacitor [3] [56-57] [78-8], a dicued in more detail in Chapter 5. A a reult, there have been increaed tudie of SC circuit and electric field-baed galvanic iolation. Another benefit that SC circuit provide i that they can reduce the witch voltage tre, and thu enable the ue of low-voltage witche. For example, in the baic Marx cell tructure of a multi-level SC converter [83-84], the voltage tre on all witche equal the cell capacitor voltage, which i multiple time lower than the converter output voltage. Thi enable the high-voltage SC converter to be deigned uing all low-voltage witche. However, traditional SC circuit provide no galvanic iolation. To enable galvanic iolation, electric field-baed galvanic iolation uing iolation capacitor alo ha been demontrated in SC circuit [3-4]. However, it till require magnetic component (i.e. reonant inductor) together with an inverter circuit and a rectifier circuit, o limited power denity reult. A an alternative approach to eparate and decouple the DM power flow, the SC iolation cell circuit ha been introduced [85-86]. Thi circuit eliminate the magnetic component, and feature a imple tructure, mall number of component, and eay control. However, the iolation capability of the circuit ha not been evaluated in the literature. The circuit mut be teted according to the indutrial afety tandard uch a the 7

41 IEC695, to validate it iolation performance uch a the CM iolation voltage and CM leakage current. Challenge for SC circuit alo exit in achieving a high voltage tranfer ratio and voltage regulation. Power converter generally achieve a high voltage tranfer ratio by mean of a high turn-ratio tranformer. Thi i another reaon why a tranformer i uually preferred. In SC dc/dc converter, a high voltage tranfer ratio i achieved by cacading multiple SC tage. Typical example include the Marx generator [83-84], the Cockcroft Walton generator [87], the Dickon converter [88], and the SC iolation cell circuit-baed voltage quadrupler [83-84]. By increaing the number of tage, the voltage tranfer ratio increae, although a larger number of component and higher control complexity reult a well. On the other hand, voltage regulation remain a challenge for SC dc/dc converter [89-9]. The exiting method of voltage regulation in SC converter are to adjut the converter equivalent reitance uch that the converter function a a linear regulator [9-9]. A a reult, the SC converter efficiency uffer and it i alway equal to or lower than the normalized voltage tranfer ratio. Recent development of WBG emiconductor have yielded power tranitor with greatly reduced on-tate reitance, reduced paraitic capacitance, enhanced breakdown voltage, increaed witching peed, and increaed operating temperature. To date, WBG device have primarily erved a drop-in replacement for their Si counterpart in conventional architecture, yielding only partial improvement compared to the ultimate potential of GaN, SiC, and other WBG device. However, to further the improvement of 8

42 ytem power denity, the unprecedented characteritic of WBG device are bringing new opportunitie for SC circuit..4. Motivation of thi Work Thi diertation tudie the iolated power converter baed on SC circuit, aiming to achieve high power denity, high efficiency, and high CM iolation performance. Reearch in thi work i performed in two direction a follow: On one hand, thi work further explore the integration of a tranformer into SC circuit, and derive new circuit topologie of iolated dc/dc converter to combine the benefit of both the tranformer and the SC circuit within a imple tructure. In uch topologie, the tranformer provide galvanic iolation and a high voltage tranfer ratio, while the SC circuit provide reduced voltage tre on active and paive component. Thi part of the reearch i preented in Chapter, 3, and 4. On the other hand, thi work explore the galvanic iolation directly provided by SC circuit, without integrating magnetic component. Recent development of WBG emiconductor have yielded power tranitor with greatly reduced on-tate reitance, reduced paraitic capacitance, enhanced breakdown voltage, increaed witching peed, and increaed operating temperature. To date, WBG device have primarily erved a drop-in replacement for their Si counterpart in conventional architecture, yielding only partial improvement compared to the ultimate potential of GaN, SiC, and other WBG device. However, to further improve ytem power denity, the unprecedented characteritic of WBG device are bringing new opportunitie for SC circuit, which are 9

43 impractical for Si device. They potentially enable the SC circuit to achieve valid CM galvanic iolation that meet the indutrial afety tandard, while having high power denity and high efficiency for DM power delivery. Thi part of the reearch i preented in Chapter 5. A witche play critical role in SC circuit, the unprecedented propertie provided by the emerging WBG power device are bringing new opportunitie for the SC circuit..5. Outline of thi Diertation Thi diertation i divided into ix chapter a follow: In Chapter, a quai-witched-capacitor (QSC) dc/ac circuit i propoed to replace the traditional half/full-bridge dc/ac circuit in iolated dc/dc power converter. The circuit integrate a tranformer into an SC circuit, combining the benefit of both part. The circuit operation principle, feature, and dc characteritic are analyzed and dicued. Then, baed on the QSC dc/ac circuit, an iolated QSC pule-width-modulation (PWM) converter i propoed to erve a an auxiliary power upply in electric vehicle (EV) or hybrid electric vehicle (HEV), managing a bidirectional power flow between the high voltage (HV) battery and the low voltage (V) dc bu. Deign guideline are given, and a -kw, 5-kHz, 4-V/-V, SiC/Si-baed converter prototype i built and demontrated. The experimental reult are preented to validate the converter feature and performance. In Chapter 3, the mall-ignal modeling and controller deign for the iolated QSC PWM converter are preented. The converter output power i regulated by witchingfrequency modulation. A mall-ignal model of the converter in buck-mode operation i

44 derived by the method of tate-pace averaging. Open-loop imulation reult from the derived mall-ignal model and a detailed circuit model are compared to highlight the effectivene of the mall-ignal model. A cloed-loop voltage controller with feedforward compenation for the witching frequency i deigned to improve the dynamic performance. Cloed-loop imulation reult from both the mall-ignal model and the detail circuit model, and the experiment reult from a -kw prototype are provided to verify the cloed-loop control. In Chapter 4, an iolated QSC reonant converter i propoed for iolated dc/dc converion in off-line power upply application. Similar to the Φ reonant converter, the propoed converter operate mot efficiently at a fixed witching frequency and duty ratio, and it feature trapezoidal voltage waveform on all witche. Full oft witching combining zero current witching (ZCS) on, near ZCS off, zero voltage witching (ZVS) on, and ZVS off i achieved within a wide load range, and therefore the witching lo i minimized. A 9-W, 88-V/9-V, 7-kHz prototype i built with -V enhancementmode Gallium Nitride (egan) field-effect tranitor (FET). The tranformer deign and PCB layout are preented to minimize the tranformer leakage inductance and tray inductance. The prototype achieved both a power denity of 7 W/inch 3, and a flat efficiency curve with a peak value of 96%. In Chapter 5, the tudy of the emiconductor-baed galvanic iolation i preented. Thi olution deliver the DM power via emiconductor power witche during their on tate, while utaining the CM voltage and blocking the CM leakage current with thoe witche during their off tate. While it i impractical to implement thi olution with Si

45 device, the latet SiC device and the coming vertical GaN device, however, provide unprecedented propertie and thu, can potentially enable the practical implementation. An iolated dc/dc converter baed on the witched-capacitor circuit i tudied a an example. The CM leakage current caued by the line input and the reultant CM touch current (TC) are quantified and compared with the limit in the afety tandard, IEC695. To reduce the TC, a low witch output capacitance and low converter witching frequency are neceary. Then, dicuion are preented of the TC reduction approache and the deign conideration to achieve high power denity and high efficiency. A 4-V, 4-W prototype baed on.7-kv SiC MOSFET i built to demo the DM power delivery performance and howcae the CM leakage current problem. Chapter 6 ummarize the diertation and provide an outlook of the future work.

46 Chapter. QSC DC/AC Circuit and Iolated QSC PWM Converter.. QSC DC/AC Circuit... Circuit Decription and Operation Principle A QSC dc/ac circuit i propoed to replace the traditional half/full-bridge dc/ac circuit in iolated dc/dc power converter. The circuit diagram i hown in Fig.., and the operation waveform are hown in Fig... The circuit combine a tranformer (embodied a the tranformer leakage inductance and tranformer magnetizing inductance m) with two witched capacitor C and C3 that have identical capacitance. Thi circuit i derived by applying the traditional voltage tripler ac/dc circuit [93] in a revere power-flow direction, and replacing the 3 diode with 3 controllable witche. A pair of witche turn on and off ynchronouly, o they are both referred to a S. For an iolated dc/dc converter, the tranformer leakage inductance cannot be ignored becaue: ) it i unavoidable; ) it limit the active output power capability; and 3) it caue freewheeling tranient which lead to the ZVS on of the witche. V in +V DS(S)- +V DS(S)- S S b + C V C C 3 - C a + V C - i S m + V m - R load S n Figure.. Propoed QSC dc/ac circuit. 3

47 T w T w / T w / S S ON ON ON t t i I dc_ V an V in /3 V DS(S) V DS(S) -V in /3 V in /3 V in /3 t t t t 3 t 4 t t t t Figure.. Operation waveform of the QSC dc/ac circuit. At teady tate, there are 4 witching mode within one witching cycle (Tw). The brief decription of each witching mode are a follow: Mode. (t-t): The input voltage ource, C, C3, and tranformer are connected in erie. C and C3 are charged. Vin=VC-Van; Mode. (t-t3): C and C3 are connected in parallel with the tranformer and load. releae it energy back to C and C3 via S. VC=Van; Mode 3. (t3-t4): C and C3 are till connected in parallel with the load, and they are now dicharged. VC=Van; Mode 4. (t-t): The input voltage ource, C, C3, and the tranformer are connected in erie. releae it energy back to the input voltage ource via S. Vin=VC-Van. The Mode and 4 are the freewheeling mode where S and S operate in ynchronou rectification mode. Becaue of the freewheeling current, S and S have ZVS on. 4

48 ... Dc Characteritic When the QSC dc/ac circuit i operated at high witching frequency, at teady tate, the voltage ripple of C and C3 are mall compared to their dc offet voltage, o VC i aumed to be contant. Becaue of the teady-tate volt-econd balance of m and, the voltage tre on C, C3 and tranformer are V C Vin VC3 Van. (.) 3 Accordingly, the voltage tree on S and S are The ac output voltage Van i V S(max) Vin VS (max). (.) 3 V an V in, 3 ( t) Vin, 3 Tw t Tw t T w. (.3) At teady tate, C and C3 are charged in erie in one half witching cycle and dicharged in parallel in the next half witching cycle. Becaue of the ampere-econd balance of C and C3, there exit a dc-offet current (Idc_) in both m and. To implify the calculation of Idc_, the zero-tate-repone (ZSR) of the circuit branch compoed of m, and R i tudied. In time domain, in each half witching cycle, the current change of in repone to an applied unit-tep voltage Vin/3 i I ( t) V 3 in Vin 3( m R R m ) [ e R ( R m ) t Vin ] t 3( ), m T w t. (.4) 5

49 6 Aume I=I(t4) at t and t4, the ampere-econd balance of C or C3 within one witching cycle i expreed a )] ( ) ( ) ( [ )] ( - ) ( [ 4 4 w T w w T dt t I T I t I dt t I t I. (.5) Baed on (.4) and (.5), the intantaneou value of I at t and t4 can be calculated, and thu Idc_ i derived a 6 ) ( ) 8( ) ( ) 9( 4 4 ) 9( ) ( _ w m w in T R R w m m in in m m in in dc T I T V e T R R V V R R V V I w m. (.6) The voltage acro m i w w T t R R in in w t R R in in m T t T e V V T t e V V t V m m, 3 3, 3 3 ) ( ) )( ( ) (. (.7) Baed on (.7), the active output power i calculated a ) ( ) ( ) ( w m w T R R w m m in in w T m o e T R V R V RT dt t V P w m m in T R R w m m in T R V e T R V w m ) ( 9 4 ) ( 9 4 ) (. (.8) To help undertanding the Idc_, a calculation example baed on Matlab i preented. Aume Vin=3 V, m=5 μh, and =.5 μh, which are the typical value for a 5 khz

50 iolated dc/dc converter for the vehicle on-board auxiliary power upply application. The value of Idc_ at different output power and witching frequency i plotted in Fig..3. Steady-tate dc offet current of and m (A) (A) Switching Frequency (Hz) Output power (W) Figure.3. Steady-tate Idc_ of the propoed QSC dc/ac circuit. In practical deign, like in the flyback converter cae, a dc-offet current in m either lead to a large flux wing range which caue a bulky core, or introduce an air gap which caue extra fringing-effect lo, lower coupling coefficient, and increaed. Thi problem i uccefully olved in the propoed iolated QSC PWM converter, with an appropriate econdary-ide rectifier circuit choen to minimize thi dc-offet current in m. 7

51 .. Iolated QSC PWM Converter... Circuit Decription Baed on the propoed QSC dc/ac circuit, an iolated QSC PWM converter i propoed. The converter chematic i hown in Fig..4. The econdary-ide circuit of the converter i a ynchronou-rectifier, current-doubler circuit. Thi circuit function a interleaving buck converter, which lead to the following benefit: ) minimized output current ripple due to the ripple-cancelling effect of and ; ) low witch conduction loe due to the ynchronou-rectification operation; 3) elimination of high-ide witch driver for S3 and S4; 4) balanced current tree in S3 and S4; and 5) minimized dc-offet current in m. S S a i N :N S 4 C 4 C C 3 V in C m V out S n S 3 Figure.4. Schematic of the propoed iolated QSC PWM converter. In the propoed converter, the erie-connected and are in parallel with m. The dc-offet current generated from the primary-ide circuit exit in both m and thi econdary-ide branch. However, ince the dc reitance (DCR) of and i much maller than that of m, the major part of the dc-offet current of m i hifted to and. Thi attribute of the converter help to prevent the tranformer core aturation without requiring any air gap. Alo, a a reult, m can be ignored in the equivalent circuit, and thu 8

52 the circuit analyi can be implified. Fig..5 how the converter equivalent circuit where all component are referred to the high-voltage (HV) ide. The converter operate in buck mode when power flow from the HV ide to the low-voltage (V) ide, and vice vera in boot mode. V in +V DS(S) - +V DS(S) - S S C C a I I C 3 I - V + + V DS(S4) - V S 4 C 4 V out S S 3 V DS(S3) Figure.5. Equivalent circuit of the propoed iolated QSC PWM converter.... Buck-mode, Hard-witching Operation Principle In the buck mode, the converter operate with a ymmetrical duty ratio (D), and a variable deadband ratio (δ). In order to maximize the duration of ynchronou rectification, S and S4 are controlled a a complementary pair, while S and S3 are controlled a another complementary pair. To be more general, the hard-witching operation i decribed firt. The interval t-t9 of Fig..6 decribe the variou tage of buck-mode, hard-witching operation during one witching cycle (Tw). One complete witching cycle i divided into 8 mode. In order to implify the circuit analyi, the circuit paraitic parameter uch a the output capacitance of the witche and the tray inductance in the circuit are not conidered. and are aumed to have identical inductance. δ, δ, δ3 and δ4 are the 9

53 duration ratio of the hort tranient caued by toring and releaing energy. I i the current of. I and I are the current of and. S S S 3 S 4 T w T w (.5 δ) T w (.5 δ) T w δ ON ON ON ON T w δ V an V in /3 -V in /3 T w δ 4 T w δ T w δ ON ON T w δ 3 t t t t t I I dc_ V in /3 t V DS(S) t V DS(S) V in /3 t V DS(S3) t V DS(S4) t I dc_ I I dc_ t I t t t t 3 t 4 t 5 t 6 t 7 t 8 t 9 t Figure.6. Buck-mode, hard-witching operation waveform of the iolated QSC PWM converter. To help undertanding each mode, a et of correponding annotated buck-mode circuit diagram i given in Fig..7 with a brief decription of each mode a follow:

54 S a S b V in C C C 3 c C 4 R oad (a) n S 3 S a S b S 4 C C 3 c C 4 R oad S (b) n S 3 b S 4 c C 4 R oad n S 3 (c) Figure.7. Switching mode diagram of the Buck-mode, hard-witching operation in one witching cycle: (a) Mode : Current path between t-t, (b) Mode : Current path between t-t3, (c) Mode 3: Current path between t3-t4, (d) Mode 4: Current path between t4-t5, (e) Mode 5: Current path between t5-t6, (f) Mode 6: Current path between t6-t7, (g) Mode 7: Current path between t7-t8, (h) Mode 8: Current path between t8-t9. (one cycle complete). Continued

55 Figure.7:. Continued S a S b S 4 C C 3 c C 4 R oad S n S 3 (d) S a S b S 4 C C 3 c C 4 R oad S n (e) S a S b S 4 V in C C C 3 c C 4 R oad (f) n S 3 b S 4 c C 4 R oad n S 3 (g)

56 Figure.7:. Continued S a S b S 4 V in c C C C 3 C 4 R oad (h) n S 3 Mode. (t-t): The input voltage ource, C, C3,, and are connected in erie. C and C3 are charged. and tore energy, while releaing it energy to the load; Mode. (t-t3): releae it energy back to C and C3, via S3, S4 and the body diode of S. and releae their energy to the load; Mode 3. (t3-t4): The energy of i completely releaed at t3. The body diode of S i revere biaed. and continue to releae their energy to the load; Mode 4. (t4-t5): C and C3 are connected in parallel and they are dicharged. and continue to releae their energy to the load. Both V and V are clamped to the output voltage, o I increae quickly, tranferring the current from S3 to S4. The body diode of S3 conduct becaue the current of (I) i larger than I; Mode 5. (t5-t6): I i equal to I at t5, o the current of S3 reache at t5. After t5, the body diode of S3 i revere biaed; Mode 6. (t6-t7): releae it energy back to the input voltage ource and C, via S3, S4 and the body diode of S. and releae their energy to the load; 3

57 Mode 7. (t7-t8): The energy of i completely releaed. The body diode of S i revere biaed. and continue to releae their energy; Mode 8. (t8-t9): The input voltage ource, C, C3,, and are connected in erie. Both V and V are clamped to the output voltage, o I increae quickly, tranferring the current from S4 to S3. During thi mode, the body diode of S4 conduct becaue the current of (I) i larger than I. At t9, the current of S4 reache and it body diode become revere biaed...3. Buck-mode, Hard-witching Operation Dc Characteritic ) Voltage Stree on the Tranformer, S and S Benefited from the primary-ide QSC dc/ac circuit, the converter feature reduced voltage tree on the tranformer and the witche S and S. Due to the volt-econd balance for, m, and in one witching cycle, the voltage tree on the tranformer and the witched capacitor C and C3 are approximately Vin VC VC. (.9) 3 Van(max) 3 Accordingly, the voltage tree on the witche S and S are V S(max) V in VS (max). (.) 3 ) Output Voltage A a reult of the volt-econd balance of at teady tate, the integration of the voltage acro (V) in mode equal to the integration of V in the other 7 mode. In order to 4

58 implify the analyi, δ4 i ignored ince it i much maller than δ, o the output voltage (Vout) i derived a V out (.5 ) (.5 ) S Vin 3N, (.) where N i the tranformer turn ratio...4. Buck-mode, Soft-witching Operation Principle and Criteria The converter ha the capability to realize ZVS in the primary-ide QSC dc/ac circuit and ZCS in the econdary-ide rectifier circuit. To achieve the ZVS on of S and S, the freewheeling current mut continue to flow till the deadband interval are over, which mean the witching Mode 3 and Mode 7 mut be kipped. Fig..8 how the major waveform of the buck-mode, oft-witching operation. T w / T w T w / S &S 3 S &S 4 V an V I T ON wδ 5 T w δ 5 ON V in /3 (t 6 ) -V in /3 t -V in /3 I dc_ V in /3 t t 5 t 6 ON t t t t t Figure.8. Buck-mode, oft-witching operation waveform of the iolated QSC PWM converter. 5

59 In Fig..8, Twδ5 i the freewheeling interval where releae and tore it energy. During Twδ5, either S or S i turned on to enable ynchronou rectification which reduce the conduction lo. Baed on the volt-econd balance of, δ5 i derived a ( Vin 3N Vout ) N 3N Vout ( N ) 5. (.) [3N V ( N ) ( V 3N V ) N ] out In one witching cycle, the integration of I equal to the integration of Idc_ derived in (.6). Therefore, the intantaneou value of I are derived a in out I I I I ( t ( t ( t ( t 6 5 ) I ) I ) I ) I dc_ dc_ dc_ dc_ VinTw 5 6 VinTw 5 6 VinTw 5 6 VinTw 5 6 ( V 3 ( V 3 ( V 3 ( V 3 in in in in NV ( N NVout ) Tw ( 5 ) ( N ) NV ( N NV ( N out ) T ) out ) T ) out ) T ) w w w ( 5 ) ( 5 ) ( 5 ). (.3) Conequently, the output power (Po) i derived, and it i controlled by changing the witching frequency (fw). Po can be calculated a P o T w W o V i dt. (.4) T T f Vin ( Vin 3NVinVout ) [ ] ( 5 ) 5 9 9( N ) w In the buck mode, the ZVS criteria for S and S are: I I ( t ( t 6 ). (.5) ) 6

60 The ZCS on and off of S3 and S4 can be achieved, by applying ufficient to uppre the lew rate of the current tranferring between S3 and S4 during Twδ5. However, large will limit the converter output power capability, and caue voltage overhoot on the witche due to the reonance between and the output capacitance of the witche...5. Boot-mode, Soft-witching Operation Principle and Criteria Fig..9 how the major operation waveform of the boot-mode, oft-witching operation. In the boot mode, the duty ratio of S and S are fixed at 5%. The duty ratio of S3 and S4 need be extended over 5%, to create on-tate interval overlapped with thoe of S and S (i.e., the t-t4 and t5-t7 interval in Fig..9). In the overlapped interval, the tranformer leakage inductance tore and releae energy which i required for bootmode power delivery. S S S 3 S 4 V I V an T w T w / T w / I dc_ ON ON -V out /3 T w δ 6 T wδ 6 -V out /3 ON ON V out /3 V out /3 t t t 3 t 4 t 5 t 6 t 7 ON ON t t t t t t t Figure.9. Boot-mode, oft-witching operation waveform of the iolated QSC PWM converter. 7

61 Similarly, in the boot mode operation, the voltage and current of during one witching cycle can be analyzed, and baed on thoe information the converter output power in the boot mode operation can be derived a P o ( Vout 3NVinVout ) Vout [ ] ( 6 ) 6 9( N 9 ), (.6) f w where δ6 i ( Vout 3N Vin ) N 3N Vin ( N ) 6. (.7) [3N V ( N ) ( V 3N V ) N ] in The ZVS criteria for S and S in the boot-mode operation are derived in a imilar way to that of the buck mode, and can be written a: I I ( t ( t 4 out in ). (.8) ).3. Deign Guideline for the Key Circuit Parameter.3.. Capacitance of C and C3 A implified method i preented here to etimate the capacitance of C and C3, baed on the allowable voltage ripple and the peak current of the two capacitor. The interval t5-t6 of the buck-mode, oft-witching operation i tudied, becaue the current of C (ic) reache it peak value at t6, and the voltage fluctuation acro C i maximum during thi interval. Auming ic i contant and it i equal to I(t6)/ throughout the interval, and the ripple of VC i 5%, the capacitance of C and C3 i calculated a 8

62 C C 3 t t t 5 t i C dv dt C T w I ( t 6 ). (.9) 4 V 5% in To help undertand, an example i preented here. If f=5 khz, Vin=3 V, Vout= V, N=8/3, =3.5 µh, =.5 µh, the calculated reult i C=C3=.56 µf..3.. Tranformer Dc-bia Flux Denity The tranformer dc-bia flux denity, together with the flux wing, decide whether the core will be aturated. Although the major part of the dc-offet current generated from the primary-ide QSC dc/ac circuit i hifted from m to and, there till exit ome reidual dc-offet current in m (Idc_m), which i I N ( ) dc_ m I dc_. (.) N ( ) m Accordingly, the dc-bia flux denity of m (Bdc_m) can be calculated a B dc_ m NI dc_ mr, (.) I e where N i the number of turn on the HV-ide; µ i the abolute permeability; µr i the relative permeability of the material; Ie i the effective length of the magnetic path Average Current of and In the propoed converter, and have unbalanced average current becaue of the dc-offet current generated from the primary-ide QSC dc/ac circuit. Conider the buck- 9

63 mode operation for example, following the reference direction of and ignified in Fig. 5, the average current of and (Idc_ and Idc_) are written a I I dc_ dc_ I I oad oad NI NI dc_ dc_ N N ( ( m m ) m ) m, (.) where Ioad i the load current in the buck-mode operation..4. Simulation Verification, Prototype Deign and Experimental Reult.4.. Simulation Verification A imulation model i built in PSIM to verify the circuit analyi. For the buck-mode operation, the imulation parameter are lited in Table.. The on-reitance and the bodydiode forward voltage of the MOSFET are et according to the dataheet. In order to imply the analyi, the paraitic capacitance and paraitic inductance are not included in the imulation model. Fig.. how the buck-mode, hard-witching teady-tate imulation waveform at Po= kw (Road=.44 Ω). Table.. Converter pecification for the buck-mode, hard-witching operation imulation of the iolated QSC PWM converter V in V out C, C 3 C 4, m N f w 3 V V µf 3 µf 3.5 µh.5 µh 45 µh 8:3 5 khz 3

64 Figure.. Steady-tate imulation waveform of the buck-mode, hard-witching operation of the iolated QSC PWM converter. The aforementioned imulation model i ued to verify the boot-mode operation capability. The imulation parameter are lited in Table.. In the boot-mode operation imulation, the N i changed to 8:, and the fw i changed to 3 khz, while all other converter parameter remain the ame. The V ide i powered by a voltage ource, and the HV ide i loaded with a reitor. Fig.. how the boot-mode operation teadytate imulation waveform at δ6=.8 and Po= kw (Road=9 Ω). Table.. Converter pecification for the boot-mode, hard-witching operation imulation of the iolated QSC PWM converter V in V out C, C 3 C 4, m N f w V 3 V µf 3 µf 3.5 µh.5 µh 45 µh 8: 3 khz 3

65 Figure.. Steady-tate imulation waveform of the boot-mode, oft-witching operation of the iolated QSC PWM converter. The imulation reult how that: ) the voltage tree on S and S are reduced to /3 of the HV-dc-bu voltage; ) the voltage tre on the tranformer HV-ide winding i reduced to /3 of the HV-dc-bu voltage; 3) S and S operate in hard witching in Fig..; 4) S3 and S4 have reduced witching lo becaue of the low lew rate of witching current; 5) the dc-offet current in m i very mall, and the unbalanced average current in and match the analyi..4.. Prototype Deign and Tet Decription A kw prototype i built, a hown in Fig... The pecification of the prototype are hown in Table.3. In the primary-ide QSC dc/ac circuit, the CREE Silicon Carbide (SiC) MOSFET (CMFD) i applied for S and S. In the econdary-ide current- 3

66 doubler rectifier circuit, becaue of the high current rating, two Infineon Si OptiMOS (IPP75N5N3) FET are applied in parallel for both S3 and S4. Primary-ide QSC DC/AC Circuit Planar Inductor & Planar Tranformer Secondary-ide Current Doubler Rectifier Circuit Total Height: 3 mm 9 mm Figure.. kw prototype of the iolated QSC PWM converter. Table.3. Sepcification of the kw prototype of the iolated QSC PWM converter. Item Rating Decription VHV =3-4 V, VV = V, Pout = kw, f =5 khz S, S SiC MOSFET (CREE CMFD) S3, S4 Si OptiMOS FET (Infineon IPP75N5N3) Planar Tranformer N=8:, m=45 µh, =.8 µh for the buck mode, N=8:, m=45 µh, =.5 µh for the boot mode. Planar Inductor ==3.5 µh Capacitor C=C3= µf/45 V The planar tranformer i built with no air gap. Two planar inductor were built for and. The core elected for the tranformer and inductor i ER4/7.6/3-3F3. For C and 33

67 C3,.-µF/5-Vdc ceramic capacitor are elected, and C=C3= µf. In the teting, a 8- µf film capacitor i added on the HV-dc-bu, and a -µf film capacitor i added on the V-dc-bu. Thi etup i valid for the cenario of HEV/EV application, where both the HV and V dc bue have large capacitance. In the experiment, power for the buck-mode tet i provided by a Magna DC Power Supply TSA8-6, and power for the boot-mode tet i provided by a NHR 9 battery tet ytem. Reitor bank are ued a the load. The control i implemented with a Texa Intrument digital ignal proceor (DSP) (TMS3F88). Tet waveform are recorded with two Tektronix ocillocope, and the efficiency i meaured uing a Yokogawa WT3 power meter with a EM Danfyik IT 7-S current tranducer on the V-ide and an external current-hunt reitor on the HV-ide Experimental Reult Fig..3 (a) how the experimental waveform of the buck-mode, hard-witching operation, at the operation point where fs=5 khz, Vin=3 V, Vout= V, and Po=97 W. Fig..3 (b) how the experimental waveform of the boot-mode operation, at the operation point where fs=5 khz, Vin= V, Vout=3 V, and Po=6 W. It can be een from Fig..3 that: ) the teady-tate voltage tree on S and S are reduced to /3 of the HV-dc-bu voltage; ) the teady-tate voltage tre on the tranformer HV-ide winding i reduced to /3 of the HV-dc-bu voltage; 3) hard-witching i reulted in the buck-mode becaue the deadband make I dicontinuou; 4) during the deadband, reonance exit between the tranformer leakage inductance and the paraitic capacitance 34

68 of the witche. The reonance caue circulating current, voltage ringing on the witche, EMI iue, and extra power lo. V DS(S) V/div V DS(S) V/div 4 n/div V DS(S) V/div V DS(S) V/div 4 n/div V an V/div I A/div V an V/div I A/div (a) (b) Figure.3. (a) Experimental reult of the buck-mode, hard-witching operation, (b) Experimental reult of the boot-mode, oft-witching operation. Soft-witching operation i preferred to improve the efficiency and alleviate the aforementioned reonance. For the teting of the buck-mode, oft-witching operation: ) a fixed 5% duty ratio with neceary deadband i applied for S and S to prevent hootthrough; ) the output voltage i fixed at V, and the output power increae with the input voltage. Fig..4 how the experimental waveform at the buck-mode, oft-witching operation point where f=5 khz, Vin=35 V, Vout= V, Po=939 W. It can be een from Fig..4 that the reduced voltage tree on the witche and the tranformer are achieved, and ZVS on i achieved for both S and S. In addition, Fig..4 (a) how that average current of i 3.35 A, and the tranient ratio δ i.83. Both of thee value matched the analyi. 35

69 V DS(S) V/div V DS(S) V/div 4 n/div V GS(S) V/div V DS(S) V/div 4 n/div I A/div V DS(S) V/div V GS(S) V/div V an V/div (a) (b) Figure.4. Experimental reult of the buck-mode, oft-witching operation. (a) Drainto-ource voltage of S and S, the voltage and current of the tranformer HV-ide winding, (b) Gate ignal and drain-to-ource voltage of S and S. Fig..5 how the drain-to-ource voltage of S, S, S3 and S4 at: (a) the buck-mode, oft-witching operation point where fs=5 khz, Vin=35 V, Vout= V, and Po=939 W; and (b) the boot-mode, oft-witching operation point where fs=5 khz, Vin= V, Vout=8 V, and Po=46 W. It can be een from Fig..5 that: ) between the off tate of S3 and S4, there exit about n tranient which reduce the witching lo of S3 and S4; ) the ringing and voltage overhoot of VDS(S3) and VDS(S4) are caued by the reonance between the tranformer leakage inductance and the paraitic capacitance of S3 and S4. To protect S3 and S4 from breakdown damage, RCD nubber are added to S3 and S4, which introduce extra power lo. 36

70 Efficiency (%) V DS(S) 4 n/div 5 V/div V/div V DS(S4) 5 V/div V DS(S3) 5 V/div V DS(S) 4 n/div V DS(S3) 5 V/div V DS(S) V/div V DS(S4) 5 V/div V DS(S) 5 V/div (a) (b) Figure.5. Experimental drain-to-ource voltage waveform of S, S, S3 and S4 in the (a) buck-mode, oft-witching operation, and (b) boot-mode, oft-witching operation. The efficiency curve of the converter with unfixed HV-dc-bu voltage in teting are hown in Fig..6 (a), and the hard-witching efficiency curve of the kw prototype with fixed HV-dc-bu voltage in teting are hown in Fig..6 (b) Output Power (W) (a) Soft-witching, buck-mode, f=5 khz Soft-witching, boot-mode, f=5 khz Hard-witching, buck-mode, f=3 khz Hard-witching, buck-mode, f=5 khz Figure.6. (a) Efficiency curve with unfixed HV-dc-bu voltage. (b) Hard-witching operation efficiency curve with fixed HV-dc-bu voltage. Continued 37

71 Figure.6.: Continued Efficiency (%) Output Power (W) (b) Buck-mode, Vin=3 V, f=5 khz Buck-mode, Vin=4 V, f=5 khz Boot-mode, Vout=3 V, f=5 khz Boot-mode, Vout=4 V, f=5-6 khz Fig..6 (a) howcae the converter potential to achieve high efficiency with oft witching. The efficiency curve in Fig..6 (b) are not optimized, ince the deign i not optimized and the converter operate in hard witching. However, it can be improved by better tuning of the circuit parameter, improving the circuit layout to reduce the circuit paraitic inductance, applying better magnetic component deign and better control..5. Concluion In thi chapter, a QSC dc/ac circuit i propoed to replace the traditional half/fullbridge dc/ac circuit in iolated dc/dc power converter. The circuit combine a tranformer and two witched capacitor, and therefore have the following feature: ) The voltage tree on the witche are reduced to /3 of the dc-bu voltage; 38

72 ) The voltage tre on the tranformer i reduced to /3 of the dc-bu voltage, and thu the tranformer turn ratio i reduced by /3; 3) ZVS on can be achieved for all the witche; 4) A teady-tate dc-offet current flow through the tranformer. Baed on the QSC dc/ac circuit, an iolated QSC PWM converter i propoed, to erve a an auxiliary power upply in EV/HEV, managing a bidirectional power flow between the HV battery and the V dc bu. The converter operation principle, oft-witching analyi, and imulation verification are preented. The feature of the reduced voltage tre on the witche and the tranformer are verified, and the dc-offet current in the tranformer magnetizing inductance i minimized. Guideline are given to etimate the key circuit parameter, including the capacitance of the witched capacitor, the tranformer dc-bia flux denity, and the average current of the pot-tage inductor. WBG device are elected for the propoed converter in order to hrink the ize of paive component, provide high efficiency, and decreae the cooling requirement. A - kw prototype i built with SiC MOSFET on the primary ide and Si MOSFET on the econdary ide. The oft-witching peak efficiency of the converter operating at 5 khz witching frequency i 96% for the buck-mode operation, and 9% for the boot-mode operation. The advantage of reduced voltage tree make the propoed iolated QSC PWM converter attractive to low-voltage rated witche, which are more efficient becaue of better figure of merit. Additionally, advantage of the new converter including reduced tranformer turn ratio, reduced device count, high voltage tranfer ratio, high efficiency, 39

73 and le control need, make the propoed converter promiing for high power application with high power denity. 4

74 Chapter 3. Small-ignal Model and Controller Deign of the Iolated QSC PWM Converter 3.. Control Method Decription To regulate the output voltage of the propoed iolated QSC PWM converter, the dutyratio control, witching-frequency control, and the phae-hift control are conidered a tandard approache [94-]. The witching frequency control keep a fixed duty ratio of 5% for HV-ide witche, but regulate the converter output power by modulating the witching frequency. Thi control technique i eentially adjuting the duration of the witching interval, and it enable oft witching over a wide load power range [96]. For reonant-type converter where witching frequency i ued to control the output voltage, the method baed on Extended Decribing Function (EDF) are ued to derive the tranfer function in [-4]. Thee method are applicable for reonant-type converter rather than PWM converter. The reaon i that, the ratio of the witching period to the ytem time contant i typically mall for fat witching PWM converter, but not for reonant type converter [5-6]. In reonant-type converter the ac behavior i dominant [7]; however, in PWM converter, with the mall ripple approximation, the Fourier erie expanion for a finite length egment of a circuit waveform hould be dominated by it dc term [6]. The tate-pace averaging method, whoe baic principle i introduced in [8-9], i applied in the mall-ignal modeling of PWM converter in [- 4

75 4 4]. In thi chapter, the mall-ignal model of the iolated QSC PWM converter in buckmode operation i derived with the tate-pace averaging method. A cloed-loop voltage controller with feed-forward compenation for the witching frequency i deigned to improve the dynamic performance. 3.. Small-ignal Model of the Iolated QSC PWM Converter 3... Switching-mode Equivalent Circuit Decription and Small-ignal Modeling A hown in Fig..8, the iolated QSC PWM converter in oft-witching, buck-mode, teady-tate operation ha 6 witching mode within one witching cycle (Tw). Thee 6 witching mode are mapped into 4 witching-mode equivalent circuit, a hown in Fig. 3.-Fig The HV-ide current of the tranformer (i), the current of the pot-tage inductor (i and i), the voltage of the witched capacitor (vc3), and the V-dc-bu voltage (vc4) are defined a tate variable, which can be written a a vector ) ( ) ( ) ( ) ( ) ( ) ( 4 3 t v t v t i t i t i t x C C. (3.) The differential equation that decribe the ytem can be written a ), ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( t i D t v B t v t v t i t i t i A t v t v t i t i t i dt d C C t x K out n in n C C n C C S

76 n,,3,4. (3.) Fig. 3. how the t witching-mode equivalent circuit of the converter during the interval t4-t. i v v C3 C C 3 vin v C4 C 4 R i C3 v v ic4 i i i out Figure 3.. The t witching-mode equivalent circuit during the interval t4-t. The matrice decribing the t witching-mode equivalent circuit are A, B, D. (3.3) R Fig. 3. how the nd witching-mode equivalent circuit of the converter during the interval t-t, with all the component referred to the HV ide. i v Nv i /N N C C 3 v C3 v Nv N Nv C4 N C 4 N in R i out /N i C3 i /N ic4/n Figure 3.. The nd witching-mode equivalent circuit during the interval t-t. The matrice decribing the nd witching-mode equivalent circuit are 43

77 44,, N N N B R N N N N N N N N A. D (3.4) Fig. 3.3 how the 3 rd witching-mode equivalent circuit of the converter during the interval t-t3. C C 3 C 4 R v C4 v C3 i i i v v v i C4 i C3 i out Figure 3.3. The 3 rd witching-mode equivalent circuit during the interval t-t3. The matrice decribing the 3 rd equivalent circuit are.,, D B R A (3.5)

78 45 Fig. 3.4 how the 4 th witching-mode equivalent circuit of the converter during the interval t3-t4. v C3 i v i C3 i /N C C 3 N Nv Nv N Nv C4 i /N i C4 /N N C 4 N R i out /N Figure 3.4. The 4 th witching-mode equivalent circuit during the interval t3-t4. The matrice decribing the 4 th equivalent circuit are,, 4 4 B R N N N N N N N N A. 4 D (3.6) A hown in Fig..8, in one witching cycle, the duration of both the t and the 3 rd witching-mode equivalent circuit i δ5tw, and the duration of both the nd and the 4 th witching-mode equivalent circuit i (.5-δ5)Tw. In the iolated QSC PWM, the ratio δ5 work a the duty ratio of traditional PWM converter. The control method i eentially

79 adjuting the duration of the witching interval. The δ5 i adjuted indirectly by changing the witching frequency fw, according to equation (.) and (.4). Therefore, the ratio δ5 i elected a the control variable in the modeling, wherea the fw till contribute to the dc term of the output voltage. Introduce the diturbance v where I I I V V T X C3 C4 x( t) X x( t), in T S ( t) V v ( t), T S in in 5( t) D 5( t), T S i ( t) i ( t), (3.7) out T S out, which are the teady-tate dc term of the tate variable that can calculated according to Chapter ; D i the teady-tate dc term of δ5, which can be calculated baed on (.) and (.4); and Vin i the teady-tate dc term of the input voltage. The ac mall-ignal (linear) tate equation i derived a d x( t) K D dt 3 4 in t A A D A A x( t) D B D B v ( ) A A A A X B B V t)) D i ( ) 3 4 in 5( out t (3.8) The ac mall-ignal model of the iolated QSC PWM converter i decribed in equation group (3.9). 46

80 47 ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( 3 ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( 3 ) ( ) ( i v R i i v C i i i v C v v i v v v i v v i out C C C C C in C C in C, (3.9) where C in I N I N I V N V N N N D D N N D N N D D. Baed on the derived mall-ignal model, the repone of the tate variable can be expreed a a linear combination of each perturbation. In particular, the tranfer function of vc4 can be derived from (3.9) a ) ( ) ( ) ( ) ( ) ( ) ( ) ( 5 4 i Z G v G v out out v in vg C, (3.)

81 48 where the input-to-output tranfer function Gvg() i vg R C C C R C C C C G ) ( (3.), the control-to-output tranfer function Gvδ() i v R C C C R C C C C G ) ( (3.), and the output impedance Zout() i out R C C C R C C C C Z ) ( (3.3) 3... Simulation Verification of the Small-ignal Model To verify the derived mall-ignal model, analyi reult baed on (3.) are compared with the imulation reult from a detailed circuit. To tudy the open-loop ytem repone to an input voltage diturbance, a mall-ignal model baed on the derived tranfer function i built in Matlab with the circuit parameter lited in Table 3. and a detailed circuit model i built in PSIM with the ame circuit parameter lited

82 in Table 3.. The input voltage tep from 3 V to 35 V, and the imulation reult from the two model are preented and compared in the ame plot in Fig Table 3.. Circuit parameter for the open-loop imulation of the iolated QSC PWM converter in repone to a input voltage diturbance. f V C4 C, C 3 C 4, R N 5 khz V µf 6 µf 3.5 µh.5 µh.36 Ohm 4 (V) v in (V) v C4 Small-ignal Model (in Matlab) Detailed Circuit Model (in PSIM) Time () Figure 3.5. Open-loop imulation reult from the mall-ignal model built in Matlab and the detailed circuit model built in PSIM in repone to an input voltage diturbance. To tudy the open-loop ytem repone to a witching frequency diturbance, the aforementioned mall-ignal model built in Matlab and the detailed circuit model built in PSIM are aigned with the circuit parameter lited in Table 3.. The witching frequency 49

83 tep from 3 khz to 6 khz, and the imulation reult from the two model are compared again and hown in the ame plot in in Fig It can be noted that the imulation reult from the mall-ignal model are in line with thoe from the detailed circuit. Therefore, the mall ignal model i verified [5], [5-6]. Table 3.. Circuit parameter for the open-loop imulation of the iolated QSC PWM converter in repone to a witching frequency diturbance. V in V C4 C, C 3 C 4, R N 3 V V µf 6 µf 3.5 µh.5 µh.36 Ohm 4 (Hz) f w (V) v C4 Small-ignal Model (in Matlab) Detailed Circuit Model (in PSIM) Time () Figure 3.6. Open-loop imulation reult from the mall-ignal model built in Matlab and the detailed circuit model built in PSIM in repone to a witching frequency diturbance. 5

84 3.3. Controller Deign of the Iolated QSC DC/DC Converter Controller Deign It can be inferred from (.4) and (.4) that, the range of the f wing in the cloedloop control can be hrunk by increaing. A maller range of the f wing i preferred for the following reaon: ) it i eaier to deign the tranformer ince the lower limit of the f wing i determined by the tranformer aturation flux denity, while the upper limit of the f wing i determined by the tranformer elf-reonance frequency; ) when f increae in light-load condition, the increaed witching lo will lead to lower efficiency. Therefore, i increaed for the cloed-loop control verification, and the aforementioned mall-ignal model built in Matlab i aigned with the circuit parameter lited in Table III for analyi. Table 3.3. Circuit parameter for the cloed-loop imulation of the iolated QSC PWM converter. V in V C4 C, C 3 C 4, R N 3 V V µf 3 µf 3.5 µh.8 µh.45 Ohm 8/3 Uing the circuit parameter lited in Table 3.3, the pole-zero map of the tranfer function Gvg() and Gvδ() are plotted in Fig It can be een from Fig. 3.7 that: ) the ytem i table ince there i no right-half-plane (RHP) pole; ) the Gvδ() ha a pair of RHP zero, which indicate that the ytem i a non-minimum-phae ytem. Becaue of thi pair of RHP zero, the ytem dynamic repone may be limited; 3) a pair of left-halfplane (HP) pole i located very cloe to the imaginary axi, which mean that the ytem 5

85 doen t have enough damping to uppre the input voltage diturbance, and the ocillation may occur. (a) (b) Figure 3.7. Pole-zero map of the tranfer function: (a) Gvg(), and (b) Gvδ(). Baed on the previou analyi, a cloed-loop voltage controller with feed-forward compenation for the witching frequency i propoed. The control purpoe i to tabilize the output voltage. Becaue of feed-forward loop, the performance of the input voltage diturbance rejection can be greatly improved [5] [7]. The control tructure of the iolated QSC PWM converter i hown in Fig

86 i out () v in () Plant G v G 5( ) G vg () V C 4, f () G v () Z out v C 4( ) f w () G c () G f v C 4 ( ) Figure 3.8. Block diagram of the iolated QSC PWM converter. Inide the control plant, the function Gδ update the ratio δ5, baed on (.). The function Gv generate part of the dc term (VC4,f) of vc4. It i derived baed on (.) and (.4), and expreed a G v b b 4ac VC4, f, (3.4) a where a 8N f b 6N f V 3 c Vin N R in (6N 4 3N ) V in R. 53

87 Outide the control plant, the function Gf generate a feed-forward-compenation witching frequency fff, baed on the input voltage and the reference output voltage. It i derived from the equation (.4), and expreed a: G f f FF in V [ 9 in C4 ( V 3NVinV ) ] ( 9( N ) R ), (3.5) V C4 where Vc4 * i the reference output voltage. The frequency-to-output tranfer function Gvf() i not uccefully derived, becaue the input voltage vin and witching frequency f are not fully decoupled in the generation of the δ, a hown in (.4) and Fig So the PI compenator Gc() i not deigned baed on the Gvf(), but intead it i deigned by the trail-and-error method, which i a common practice in indutry. In the Gc(), increaing Kp will add more damping into the ytem, and the repone time will be reduced. However, a large Kp might caue tability iue, becaue of the preence of the RHP zeroe in the Gvδ(). On the other hand, increaing Ki will reduce the repone time, but caue more ringing Cloed-loop Simulation Verification In the cloed-loop control imulation, the aforementioned mall-ignal model built in Matlab and the detailed circuit model built in PSIM are aigned with the circuit parameter lited in Table 3.3. A 5-V tep change of vin i introduced, and the imulation reult from the two model are compared and hown in the ame plot in Fig

88 V in V C4 Small-ignal Model (in Matlab) Detailed Circuit Model (in PSIM) f Small-ignal Model (in Matlab) Detailed Circuit Model (in PSIM) δ Small-ignal Model (in Matlab) Detailed Circuit Model (in PSIM) Figure 3.9. Cloed-loop imulation reult from the mall-ignal model and the detailed circuit model in repone to an input voltage diturbance. To highlight the improved dynamic performance due to the feed-forward compenator, a group of imulation i conducted and compared. In the imulation, a tep change in the input voltage i introduced. The open-loop repone, cloed-loop repone with and without feed-forward compenator are compared, a hown in Fig. 3.. The PI parameter are the ame in the cloed-loop imulation with and without the feed-forward compenation. 55

89 V in V C4 Open-loop repone Cloed-loop repone without feed-forward compenation Cloed-loop repone with feed-forward compenation f δ With Feed-forward Compenation Without Feed-forward Compenation With Feed-forward Compenation Without Feed-forward Compenation Figure 3.. Simulation reult of the open-loop repone, cloed-loop repone with and without feed-forward compenation of the mall-ignal model in repone to a diturbance of the input voltage. Fig. 3.9 and Fig. 3. how that: ) the cloed-loop voltage control baed on witching frequency regulation i realized; ) it i proved that with the feed-forward compenation, the ocillation in the ytem i ignificantly damped and the repone time i reduced. It i hown in Fig. 3.9 that there exit dicrepancie between the ytem repone of the two model. Poible reaon for thee dicrepancie include that there exit paraitic circuit parameter in the detailed circuit model, the dc term of the tate variable which can be affected by vin are not updated in the mall-ignal model, and the numerical algorithm of 56

90 the oftware PSIM and Matlab are different ince PSIM i baed on the nodal analyi [8], wherea Matlab i baed on the tate-pace analyi [9] Experimental Verification Experimental Setup Decription The -kw iolated QSC PWM converter prototype preented in ection.4 i ued for the experimental verification. In the tet etup, the input voltage ource i a Magna dc Power Supply (TSA8-6). Thi power upply ha limited output dynamic performance and cannot provide a fat tep change in it output voltage becaue of it output capacitance. Alo, in the prototype, there exit circuit paraitic uch a the tray inductance and the tray reitance in the circuit, and thee paraitic are affecting the dynamic repone of converter. The cloed-loop control i implemented with a digitalized PI compenator in DSP (TMS3F88). The diagram i hown in Fig. 3.. The converter output voltage i meaured uing a voltage tranducer which provide iolation. The ampling circuit i an analog circuit that provide ignal amplification. The ADC module i the integrated in the DSP. The digital nd-order Butterworth filter ha a cutoff frequency at khz. The Gc(z) i a dicrete PI compenator. The fff i the feed-forward-compenation witching frequency. The digital pule frequency modulation (DPFM) generate the gate ignal for the power witche, with fixed 5% duty ratio but varying witching frequency. The iolator and gate driver are the IC that provide ignal iolation and amplification for the gate driving current. 57

91 V ref G c (z) f FF f DPFM Iolator & Driver The Power Stage V out Digital nd -order Butterworth Filter ADC Sampling Circuit Voltage Tranducer DSP (TMS3F88) Figure 3.. Function block of the digital control implemented in DSP Experimental Reult A cloed-loop experiment with an input voltage diturbance i conducted. The initial operation condition are a follow: Vin=9 V, R=.4 Ohm, the duty ratio for the witche i.5 with a 7 n deadband. A -V diturbance i introduced to the input voltage. The experiment reult are hown in Fig. 3., and the zoomed-in waveform before and after the diturbance are hown in Fig. 3.3 and Fig V in 5 V/div 4 m/div V out.5 V/div V g(s) I 5 V/div 5 A/div Figure 3.. Cloed-loop experiment waveform with a -V input voltage tep change. 58

92 V in 5 V/div µ /div Zoom Poition = -43. m V out.5 V/div V g(s) 5 V/div I 5 A/div Figure 3.3. Zoomed-in cloed-loop experiment waveform of Fig. 8 at t=-43. m, Vin=9 V, f=8 khz. µ /div Zoom Poition = 34 m V in 5 V/div V out.5 V/div V g(s) 5 V/div I 5 A/div Figure 3.4. Zoomed-in cloed-loop experiment waveform of Fig. 8 at t=34 m, Vin= V, f=5 khz. The cloed-loop experiment waveform with a diturbance of the load current i hown in Fig The initial operation condition are a follow: Vin=5 V, N=8/3, 59

93 R=.67 Ohm, Iload= A, the duty ratio for the witche i.5 with a 7-n deadband. A 6- A load current diturbance i introduced when the load i uddenly reduced to R=.4 Ohm. V in 5 V/div 4 m/div V out.5 V/div I load I 5 A/div 5 A/div Figure 3.5. Cloed-loop experiment waveform with a load current tep change from A to 8 A. It can be een from Fig that: ) to maintain a table output voltage, the f changed from 8 khz to 5 khz, and the cloed-loop voltage control baed on witching frequency regulation i verified; ) there exit ringing in the tranformer current waveform, and it i caued by the reonance between the and the output capacitance of S3 and S4. It can be een from Fig. 3.5 that the output voltage i tabilized in pite of a load current diturbance, and the witching frequency variation i mall becaue of the low output impedance of the converter. 6

94 3.5. Concluion In thi chapter, the mall-ignal model and controller deign of the iolated QSC PWM converter are preented. To maintain ZVS operation, the output power of the converter i regulated by the witching frequency modulation. Thi control method i eentially adjuting the duration of the witching interval. A mall-ignal model of the converter i derived by the method of tate-pace averaging. Open-loop repone imulation reult from the derived mall-ignal model and a detailed circuit model are provided and compared. The imulation reult howcae the effectivene of the derived mall-ignal model. For better performance of the input voltage diturbance rejection, a cloed-loop voltage controller with feed-forward compenation for the witching frequency i deigned to regulate the output voltage. Comparion of cloed-loop imulation reult from the mallignal model and the detailed circuit model verified the effectivene of the cloed-loop controller. With feed-forward compenation, the ocillation in the ytem can be ignificantly damped and the repone time i reduced. Experiment reult from a -kw prototype with digital control implemented in DSP verified the effectivene of the cloedloop voltage control baed on witching-frequency control. 6

95 Chapter 4. Iolated QSC Reonant Converter In Chapter, the iolated QSC PWM converter i propoed and demontrated. Though the turn-on lo of the converter i minimized with ZVS on, the turn-off lo till limit the capability of the converter to operate at higher witching frequency. In thi chapter, an iolated QSC reonant converter i propoed to further reduce the witching lo and thu improve the efficiency. It erve a a dc-dc tranformer (DCX) in off-line power upply application, operating in open loop at it fixed but optimal witching frequency and duty ratio. Thi chapter i divided into five ection. Section 4. dicue the application background. Section 4. preent the decription and operation principle of the iolated QSC reonant converter. Section 4.3 preent the prototype deign. Section 4.4 preent the imulation reult and experimental reult. Section 4.5 conclude thi chapter. 4.. Application Background Conumer electronic (CE) uch a laptop, mart-phone, and mart-pad are indipenable information-technology tool in today world. CE product require an external off-line ac/dc power adapter to power up the device or charge it internal battery with a univeral line input. The outlook for the external ac-dc power upply market i expected to remain trong over the next everal year increaing from $.7 billion in 4 6

96 to $4.9 billion in 9, a compounded annual growth rate (CAGR) of 6.9% []. In thi market, there exit ever-increaing demand for high power-denity and highly energy efficient power upplie. Currently, available commercial product are baed on the Silicon (Si) device. For example, the tate-of-art, Si-baed, commercially available 9-W ac/dc power adapter product from AcBel i in the ize of 5.7 inch 3, and the meaured peak efficiency i 9 %. However, the growing conenu in the power electronic community i that Si device cannot meet the need of the future of power electronic [-5]. Thi i driven by market demand for further improvement in efficiency, reduction of phyical ize, and an increae in maximum operating temperature. The WBG power device, uch a the GaN high electron mobility tranitor (HEMT), are poed to atify thee emerging market need. The 3X wider bandgap of the GaN device enable them to operate under greater voltage tre per channel length, at higher temperature, while witching at fater peed and cauing lower power lo. All of thee attribute indicate that by uing GaN device, maller and more efficient ac/dc power adapter can be realized. For example, FINix ha announced a tate-of-art, GaN-baed, pre-order available 65-W ac/dc power adapter Dart, meauring.5 inch 3 and weighing 6 gram, which i 6~75% maller than it conventional counterpart [, 6, 7]. To maximize the benefit of GaN device, low-voltage rating of the device i preferred. Thi i becaue low-voltage rated device are more efficient, a they have better figure of merit which i the product of on-reitance and total gate charge [64-65]. Currently, mot power adapter product are baed on traditional circuit topologie, including: ) ingletage Flyback Power Factor Correction (PFC) circuit [66-68], ) two-tage topology 63

97 compoed of a Boot-PFC circuit and a Half-bridge C reonant converter [69-7], and 3) topologie baed on Φ reonant converter [73-76]. All thee topologie impoe high voltage tre ( dc-link voltage) on witche, and thu require high-voltage (e.g. 6-V) rated device, which i neither energy efficient nor power-denity optimized. For the twotage topology, Buck-PFC circuit can be applied to lower the dc-link voltage to 8~9 Vdc, o a to reduce the voltage tre on witche in the downtream dc/dc tage [8-9]. It i demoed that a Buck-PFC baed 9-W ac/dc power adapter achieved the ize of 5.93 inch 3 and the efficiency of 9.5 % [8]. For the downtream iolated dc/dc tage, to enable the ue of low-voltage GaN device, a QSC dc/ac circuit i propoed in Chapter. Comparing to half/full-bridge circuit, it reduce the voltage tre on witche by /3, and reduce the tranformer turn ratio by /3. Baed on it, a QSC PWM converter i derived in Chapter. However, even though with ZVS on, the turn-on lo of the converter could be minimized, the turn-off lo till limit the capability of the converter to operate at higher witching frequency. In thi chapter, a QSC reonant converter i propoed to addre the aforeaid challenge. It erve a an iolated dc/dc converter, downtream to a PFC circuit, in offline power adaptor application. The converter i baed on the QSC dc/ac circuit that provide reduced voltage tre on witche and tranformer. It alo feature full oft witching combining both ZCS and ZVS within a wide load range, and it i operated mot efficiently at fixed but optimal witching frequency and duty ratio. A 9-W, 88-V/9-V, 7-kHz prototype i built with -V enhancement-mode Gallium Nitride (egan) fieldeffect tranitor (FET). The tranformer and PCB layout are deigned to minimize the 64

98 leakage inductance and loop tray inductance. Thee circuit deign and method yield high power denity a well a high efficiency over a wide load range. 4.. Circuit Decription and Operation Principle 4... Circuit Feature and Operation Principle The propoed iolated QSC reonant converter chematic i hown in Fig. 4.. The operation waveform are hown in Fig. 4.. A hown in the operation waveform, the converter ha the following feature: ) Similar to the Φ reonant converter, the voltage waveform of all witche in the iolated QSC reonant converter are trapezoidal, featuring ZVS on and off [3]. However, a the Φ reonant converter impoe the voltage tre on witch X higher than the input voltage, the iolated QSC reonant converter reduce the voltage tre on HV-ide witche to /3 input voltage, and thu enable more choice of low-voltage GaN HEMT. ) Compared to half/full-bridge converter (e.g. the C reonant converter and the dual-active-bridge converter), the tranformer turn ratio of the iolated QSC reonant converter i reduced by /3, which enable le number of turn of the winding, lower winding lo and lower tranformer leakage inductance. 3) A dicued in detail in the following content, by utilizing two type of circuit reonance, the converter achieve full oft witching combining both ZCS and ZVS within a wide load range, and therefore ignificantly reduce the witching lo. 65

99 C o C o a N:: S 4 o V in S S C C 3 m C o C 4 C o R V out S C o n S 3 C o Figure 4.. Equivalent circuit of the iolated QSC reonant converter. C, C3 and C4 are the witched capacitor; and m are the tranformer leakage inductance and magnetizing inductance; and o and Co compoe the output filter. To analyze all witching tranient within one witching cycle, the output capacitance of all the witche (Co and Co) mut be taken into conideration. T w / T w / T on_w T on_w S &S 3 S &S 4 ON T db_min ON V in /3 T db_min ON t t V an t -V in /3 I m I dc_m t I V DS(S) I dc_ V in /3 t V DS(S) t V in /3 t t t 3 t 4 t 5 t 6 t 7 t 8 t t Figure 4.. Operation waveform of the iolated QSC reonant converter. Two type of reonance are utilized in operation, which exit in the active witching mode and deadtime mode repectively. A reult, ZCS on and near ZCS off are achieved during the active witching mode, while ZVS on and off are achieved during the dead-time mode. 66

100 At teady tate, the converter ha 8 witching mode within one witching cycle (Tw), a hown in Fig. 4.3 (a)-(h). In the figure, the red loop ignify the current path of which the reonance i determined by ; the blue loop ignify the current path of which the reonance i dominated by m. C o C o a S 4 V in S C S C 3 m C o C 4 I R S S 3 n C o (a) C o C o C o a S 4 V in S C S C 3 m C o C 4 I R S S 3 n C o (b) C o C o C o a S 4 V in S S C C 3 m C o C 4 I R S C o (c) n S 3 C o Figure 4.3. The witching-mode diagram of the continou operation in one witching cycle, including: (a) Mode : current path between t - t, (b) Mode : current path between t - t, (c) Mode 3: current path between t - t3, (d) Mode 4: current path between t3 - t4, (e) Mode 5: current path between t4 - t5, (f) Mode 6: current path between t5 - t6, (g) Mode 7: current path between t6 t7, (h) Mode 8: current path between t7 t8 (one witching cycle complete). Continued 67

101 Figure 4.3: Continued C o C o a S 4 V in S S C C 3 m C o C 4 I R S n S 3 C o (d) C o C o C o a S 4 V in S C S C 3 m C o C 4 I R S S 3 n C o (e) C o C o C o a S 4 V in S C S C 3 m C o C 4 I R S S 3 n C o (f) C o C o C o a S 4 V in S C S C 3 m C o C 4 I R S C o n (g) S 3 C o 68

102 Figure 4.3: Continued C o C o a S 4 V in S S C C 3 m C o C 4 I R S n S 3 C o (h) C o There are two type of reonance identified in operation. The firt type caue reonant witching current. It reult in ZCS on and near ZCS off, and therefore ignificantly reduce the witching loe. Such reonance exit between the C, C3, C4, and, and it happen in the active witching mode, including the Mode,, 5, and 6. The equivalent reonance path for Mode and are hown in Fig. 4.4 (a), and the equivalent reonance path for Mode 5 and 6 are hown in Fig. 4.4 (b). C R S S C R S S V S N C 4 V S N C 4 (a) (b) Figure 4.4. The equivalent reonant path after aplace tranformation to denote the firt type of reonance happening during the active witching mode, including (a) Mode and, and (b) Mode 5 and 6. Such reonance caue reonant withcing current and thu reult in ZCS on and near ZCS off for all the witche. The econd type of reonance exit between the Co, Co, and m. It happen in the dead-time witching mode, including the Mode 3 and 7. The equivalent reonance path i 69

103 hown in Fig Thi type of reonance tranfer the energy tored in the output capacitance of one witch to it complementary witch, recycling that energy which otherwie would be lot in the ZCS operation. Thi reonance lead to ZVS on and off of the witche, which furthermore improve the efficiency. It alo help low down the dv/dt of the witche, eliminate the voltage overhoot, and reduce the EMI noie. 3C OSS C OSS m N Figure 4.5. The equivalent reonant path after aplace tranformation to denote the econd type of reonance during the dead-time witching mode, including Mode 3 and 7. Such reonnace recycle the energy in witch output capacitance which otherwie would be lot in the ZCS operation, and thu reult in ZVS on and off for all the witche. The converter i operated mot efficiently when both aforeaid type of reonance are implemented. Thi require the right timing of witching, which lead u to derive the optimal duty ratio and witching frequency Optimal Duty Ratio and Switching Frequency To find the optimal duty ratio and witching frequency, the optimal duration of the active witching mode and the dead-time witching mode mut be derived repectively, and the derivation i preented a follow. A hown in Fig. 3.4, in the equivalent reonant path for the active witching mode, m i ignored ince it i much larger than. Depite the initial voltage on C and C4, the current I equal to at both t and t4, o a lumped voltage ource repreent all the initial condition for each cae. In Mode 5 and 6, where 7

104 S i turned on, the um of the voltage drop acro the (V) and the loop paraitic reitance R (VR) i V ( ) C C R C 4 4 VR ( ) VS. (4.) CC4 RCC4 C.5C 4 The loop current reonate to when the derivative of V(t)+VR(t) reache, o the V(t)+VR(t) i derived with Invere aplace Tranformation baed on (4.) a V at at V ( ) V ( ) V e cobt e in bt ( t) VR ( t) R S C a b, (4.) where a R b C.5C 4 C C 4 R 4. According to (4.), the derivative of the V(t)+VR(t) i derived a d V ( t) VR ( t) a VS b e dt b at in bt. (4.3) By equating (4.3) with, the optimal duration of the active mode (Ton_w) i derived a T on _ w. (4.4) b The minimum deadtime (Tdb_min) i required to complete Mode 3 and Mode 7. To implify the analyi, the current of m i aumed to have a triangular waveform, and the dc-offet current i ignored ince it i very mall compared to the ripple current. Then, the following equation are derived I _ pk V Ton_ w T in db_ min, 3 m 7 T db_ min 4V outco V inco N. (4.5) I _ pk

105 Baed on (4.5), the Tdb_min can be derived a T db_ min VoutC o VinCo m N Ton_ w Ton_ w. (4.6) V 4 in Baed on (4.4) and (4.6), the optimal duty ratio (Dw) and optimal witching frequency (fw) can be derived a D w Ton_ w, ( T T ) on_ w db_ min f w ( T T ). (4.7) on_ w db_ min Burt-mode Operation for Improved ight-load Efficiency The converter efficiency i the loe compared to the output power delivered. In general, of the majority of loe, there are fixed loe like the driving loe and conduction loe that vary with the quare of output power. In light-load condition, the proportion of the fixed loe over the delivered power become large. Therefore for the light-load condition, burt-mode control i employed to decreae the loe by periodically blocking the driving ignal, a hown in Fig. 4.6, and thu improve the efficiency. Moreover, to achieve a high efficiency a poible, during the burt-on time (Ton_br), the converter i deired to operate under the teady tate of the highet efficiency load condition current (Iopt) [3]. D burt T T on_ br burt T T on_ br on_ br T off _ br I I R opt. (4.8) 7

106 During the burt-off time (Toff_br), C4 releae it energy to the load through the output filter (o and Co), and the C4 begin to reonate with o and Co, which create a periodical ripple in VC4. The period of the ripple (Tro) i derived a T ro C C ( C ). (4.9) o o 4 o C4 To optimize the witching tranient during Ton_br, the Toff_br mut be integer (n) time of Tro, o that VC4 reonate back to the average output voltage (Vo) at the end of the Toff_br. Baed on (4.8) and (4.9), the burt period i derived a T burt T ni T opt ro on_ br Toff _ br. (4.) Iopt I R T w V g_s V g_s (a) T burt T on_br T off_br V g_s V g_s T ro V o V c4 V c4 (b) Figure 4.6. (a) Normal-mode operation and (b) burt-mode operation for the light-load condition. The burt-mode control alo enable the output voltage control when the converter i operating at optimized duty ratio and witching frequency. 73

107 4.3. Prototype Deign To verify the circuit analyi, two prototype of the QSC reonant converter are built, including a 9-W, 88-V/9-V, 7 khz prototype, and a 65-W, 38-V/9-V, MHz prototype. Thee iolated QSC reonant converter erve a the DCX in a power adapter with a two-tage tructure, a hown in Fig In thi tructure, the DCX i operated at fixed but optimal witching frequency and duty ratio, while the Boot-PFC tage provide the voltage regulation. AC input (9 ~ 64 V rm ) EMI Filter Diode- Bridge Rectifier Boot- PFC Stage DC link (38 V) Iolated QSC Reonant Converter DC output (9 V) Figure 4.7. The two-tage trucutre of the 65-W power adapter for laptop. High witching frequency i preferred to hrink the paive component and increae power denity, o high reonant frequency of the circuit i required. To enure underdamped witching current for the ZCS operation during the active witching-mode interval, in practical deign, it require: ) low tranformer leakage inductance, and ) minimized tray inductance and tray reitance in power-loop layout Planar Tranformer Deign The 9-W prototype deign i dicued here a the example. In order to reduce the tranformer leakage inductance, a center-tapped planar tranformer with an interleaving 74

108 winding tructure i deigned, a hown in Fig. 4.8 (b). Aiming initially at a witching frequency at MHz, the Ferrite material 3F45 from Ferroxcube i choen for the magnetic core. Baed on the material permeability and voltage tre on winding, the tranformer turn ratio i deigned a N=3::. A dicued in [3], the leakage inductance can be etimated a: leak lw h h 4 h b, (4.) w where lw i the length of each turn, bw i the width of each turn, h and h are the layerthickne of the primary and econdary winding, and hδ i the height of inulator layer. A (4.) implie, in order to reduce the tranformer leakage inductance, the winding trace are preferred to be deigned with horter length, larger width, and maller thickne per turn. Meanwhile, the inulation layer i preferred to have maller thickne. A hown in Fig. 4.8 (a), an ideal model without termination i analyzed firt in ANSYS Maxwell 3D. The imulation reult are: m=9 µh, = nh. I ec I pri I pri / (reerved for I ec ) I ec I pri / (reerved for I ec ) I pri (a) Figure 4.8. (a) ANSYS Maxwell 3D imulation model of the ideal planar tranformer without termination and (b) the interleaving winding tructure. 75 (b)

109 Then, a detailed tranformer model with via connecting different layer, a hown in Fig. 4.9 (a), i built in ANSYS Q3D Extractor for termination inductance analyi. Two part of tray inductance contribute to the total reonance inductance, including the tray inductance of the via connecting different layer of the winding, and the reulted extra winding trip between the via. Thee inductance are etimated repectively. The tray inductance of the extra winding trip can be etimated by the following equation [33] trip W H.[ln.35.5] H, (4.) W H where i the length of the trip, W i the width of the trip, and H i the thickne of the trip. For example, the etimated tray inductance of the trip highlighted in purple in Fig. 4.9 (a) i 6.3 nh. In addition, to reduce the tray inductance caued by the via connecting different layer of the tranformer winding, an interleaving tructure of the via i applied, a hown in Fig. 4.9 (b). For each tranformer winding, at place where different layer of the winding connect, interleaving row of via carrying oppoite current are placed with enough clearance ditance for breakdown prevention. The paralleled via in a row provide reduced reitance and reduced conduction lo. The interleaved row of via allow for reduced eddy and proximity effect, reducing the ac conduction loe. The tray inductance of the interleaving via can be etimated by the following equation [34] via 3 h[ ln ln ] H r, (3.3) 76

110 where i the ditance between adjacent row of via, r i the via-hole radiu, and h i the via length. For example, the etimated tray inductance of the via hown in Fig. 4.9 (b) i.6 nh. tray inductance of thi trip: 6.3 nh (a) (b) Figure 4.9. (a) Detailed imulation model of the planar tranformer built in ANSYS Q3D Extractor for termination inductance analyi, (b) Interleaving via of the palanr tranformer. 77

111 4.3.. PCB ayout Again, the 9-W prototype deign i dicued here a the example. An 8-layer PCB i deigned, where the power-loop trace and the planar tranformer winding are integrated. The pacing between the PCB layer need to be large enough to meet the iolation requirement in the indutrial afety tandard. However, maller pacing i preferred in order to reduce both the tranformer leakage inductance and the tray inductance in layout. To meet the afety tandard uch a IEC695, the pacing i required to be at leat 4 µm. However, according to the tandard IPC, the electric trength of the FR4 material i 39.4 kv/mm, o a 4-mil pacing i elected in thi preliminary deign, which i enough to withtand 4-kV iolation. The power-loop tray inductance i alo part of the reonance inductance. It low down the witching peed, cauing more witching lo [35-36], and thu need to be minimized. In the PCB layout, the optimal layout for reduced tray inductance and reitance, a propoed in [36], i followed. Take the layout of S, C and C3 for example (hown in Fig. 4.): ) S, C and C3 are all placed on the top layer, with minimal pacing in between; ) the tranformer primary-ide winding tart from the top layer and end on the nd layer; 3) the witch current flow to the tranformer on the top layer, and return on the nd layer. The current return path i located directly underneath the top layer power loop, allowing for the mallet phyical loop ize combined with field elf-cancellation. 78

112 Tranformer C S S C 3 Gate Driver On the top layer On the nd layer Figure 4.. Optimal PCB layout of the witched capacitor and witche for reduced high frequency paraitic inductance and reitance in the power loop of the converter Output Rectifier The witche S3 and S4 operate a ynchronou rectifier (SR) to reduce the conduction lo. However, due to the high ource-drain forward voltage of egan FET, the propagation delay before turning on the device would lead to high conduction lo, which can be minimized by Schottky diode in parallel [37]. In the deign, S3 and S4 are paralleled with Si Schottky Diode PDS76, which are elected for it low forward voltage. The 9-W prototype of the iolated QSC reonant converter i hown in Fig. 4.. The circuit parameter are lited in Table 4.. It include the main circuit and gate-drive circuit, but doen t include the controller, the iolated power upplie for the gate-drive circuit, and the output filter. The power denity of thi preliminary prototype ha reached 7 W/inch 3. 79

113 4 mm 47 mm Height: 7.6 mm Figure 4.. A 9-W, 88-V/9-V, 7-kHz, iolated QSC reonant converter prototype. Table 4.. Specification for the imulation model and experimental prototype of the 9- W, 88-V/9-V, 7-kHz, iolated QSC reonant converter Item Decription Specification Vin/Vout Input voltage/output voltage 88 V/9 V fw Optimal witching frequency 7 khz Dw Optimal duty ratio.3 C, C3, C4 Switched capacitor. µf, ceramic V, m S~S4 Planar tranformer (integrated in the PCB) Switche R Power-loop reitance. MHz Ferrite 3F45 from Ferroxcube, m=6 µh, =5 nh, N=3::, EPC6 ( V/ A). S3 & S4 are in paralleled with chottky diode PDS W Prototype A 65-W, 38-V/9-V, -MHz, iolated QSC reonant converter prototype i built for the power adapter dc/dc tage. It ha an etimated high efficiency of 97.5%, and a high power denity of 75 W/inch 3. The PCB layout and prototype are hown in Fig. 4.. Enhancement-mode GaN HEMT from EPC are employed for it low but ufficient voltage 8

114 and current rating, mall package, and high figure of merit. A the QSC dc/ac circuit reduce the voltage tre on the witche, the teady-tate voltage tre on the primaryide witche i only 67 V, o the 45-V, 4-A rated EPC7 i choen a the primaryide witche. The EPC7 i with a.95 mm.95 mm footprint, which i much maller than the 6-V Si CoolMOS FET and 6-V GaN HEMT with imilar or available, lowet current rating ( A or o). The QSC dc/ac circuit in uch power rating i a niche application for the EPC7, becaue uch device don t have enough voltage margin when applied in half/full-bridge circuit with a 4-V dc bu. Unfortunately, thi device i called off by EPC in Dec. 5, after the prototype i built. On the econdary ide, the 8- V, 3-A rated EPC9 i choen a the witche, operating a ynchronou rectifier to reduce the conduction lo. (a) (b) Figure 4.. (a) PCB layout and (b) prototype of a 65-W, 38-V/9-V, -MHz iolated QSC reonant converter erving a the dc/dc tage of the 65-W power adapter for laptop. 8

115 Gate-drive Circuit Power Supply The gate-drive circuit power upply for the witche in the power adapter i deigned a follow: ) auxiliary winding in the boot inductor and the iolation tranformer are deigned a hown in Fig. 4.3, to upply the gate-drive power during the continuou operation. The power from the auxiliary winding are rectified by chottky diode, and then tored in the ource capacitor (Caux, Caux, and Caux3) of the gate-drive circuit power upply; and ) during the tart-up, large reitor are ued to charge up Caux, Caux, and Caux3, uing the energy from the dc-bu capacitor or the witched capacitor C and C3. EMI Filter S boot + - C aux3 + - C + - C aux S S D C aux S 3 C C 3 C 4 - D C o o V out S S 4 Figure 4.3. Auxilary winding configuration to provide power for the gate-drive circuti in continou operation of the power adatper Simulation and Experimental Verification Simulation and Experimental Reult of the 9-W Prototype Two experiment are conducted to compare the operation with and without optimized duty ratio and witching frequency. The firt experiment i conducted under the condition: Vin=88 V, Po=9 W, Dw=.47, and fw=9 khz. Both the imulation and experimental waveform are hown in Fig Since the witch current and tranformer current couldn t be monitored in the prototype, only the voltage waveform are recorded. 8

116 n/div V d_s (5V/div) V d_s (5V/div) V d_s3 (5V/div) V an (5V/div) (a) Figure 4.4. (a) The imulation waveform and (b) the experimental waveform of the voltage acro the witche (Vd_S, Vd_S, Vd_S3), the tranformer primary-ide winding voltage (Van), the tranformer primary-ide winding current (I_), and tranformer primary-ide-referred magnetizing inductor current (I_m). All waveform are recorded in the operation condition: Vin=88 V, Po=9 W, Dw=.47, and fw=9 khz. Baed on the analyi, in thi cae the Dw and fw are not optimized, o ZVS on and off are not achieved. (b) V d_s (5V/div) V d_s (5V/div) n/div V an (5V/div) V d_s3 (5V/div) (a) Figure 4.5. (a) The imulation waveform and (b) the experimental waveform of the voltage acro the witche (Vd_S, Vd_S, Vd_S3), the tranformer primary-ide winding voltage (Van), the tranformer primary-ide winding current (I_), and tranformer primary-ide-referred magnetizing inductor current (I_m). All waveform are recorded in the operation condition: Vin=88 V, Po=9 W, Dw=.3, and fw=7 khz. Baed on the analyi, in thi cae the Dw and fw are optimized, o ZVS on and off are achieved. 83 (b)

117 Following that, the econd experiment i conducted, under the tet condition: Vin=88 V, Po=9 W, Dw=.3, and fw=7 khz. Both the imulation and experimental waveform are hown in Fig A hown in the Fig. 4.4 and Fig. 4.5: ) the voltage tre on S and S are reduced to Vin/3, and the voltage tre on the tranformer i reduced to Vin/3 on the primary ide; ) ZVS on and off are not achieved in Fig. 4.4, but achieved in Fig 4.5. With optimized Dw and fw applied, the witching lo i minimized; 3) In Fig. 4.4, the voltage overhoot and ringing on the witche at turning off are ignificant, which increae the rik of breakdown failure and the EMI noie. However, uch ringing and overhoot are eliminated when optimized Dw and fw are applied, a hown in Fig 4.5, which indicate more reliable operation and reduced EMI noie. To verify the burt-mode control, imulation i conducted on the ame circuit model in PSIM, and experiment are conducted on the 9-W prototype. The tet condition are: Vin=75 V, Dburt=.5, fburt=4 khz, Po= W. The imulation and experimental reult are hown in Fig. 4.6 and Fig. 4.7, repectively. 84

118 Figure 4.6. converter. Burt-mode operation imulation reult of the iolated QSC reonant 4 µ/div V g_s (.5V/div) V g_ (.5V/div) V C4 (5V/div) V an (5V/div) Figure 4.7. Burt-mode operation experimental reult of the iolated QSC reonant converter. 85

119 Efficiency (%) Power o (W) A hown in the Fig. 4.7: ) the trategy of electing the Toff_br to be integer time of Tro i verified, and it matched the imulation reult in Fig. 4.6; ) in the Van waveform, it exhibit damping during the burt-off time, which i caued by the loop paraitic reitance. Thi damping gradually deplete the energy tored in the magnetic, o the converter will experience a tart-up tranient when witching back to the normal-mode operation. Further analyi and the delicate control to moothly get through thi tranient need to be dicued in future work. The converter power lo and efficiency curve are hown in Fig It i hown that the power lo and efficiency are ignificantly improved with optimized Dw and fw applied, a reult a flat efficiency curve with a peak value at 96 % i achieved Output Power (W) Normal-mode operation efficiency w/ optimized Dw and fw Normal-mode operation efficiency w/o optimized Dw and fw Efficiency of preliminary burt-mode teting Normal-mode operation power lo w/ optimized Dw and fw Normal-mode operation power lo w/o optimized Dw and fw Figure 4.8. Power lo and efficiency reult of the prototype, in comparion between the operation with and witout optimized Dw and fw. 86

120 4.4.. Preliminary Simulation Reult of the 65-W Prototype The imulation reult of the 65-W prototype are hown in Fig Similar to the 9-W prototype preented in ection 3..4, thi 65-W prototype achieve reduced voltage tre on the witche and the tranformer, a well a full oft witching combining ZVS and ZCS within in a wide load range. In the tranformer winding deign, inner hielding layer are added in between the primary ide and econdary, to block the CM noie tranmitted acro the tranformer winding [38-39]. In thi way, le CM noie i een at the line input, and thu the EMI filter ize can be reduced. The teting of thi prototype i till in progre. Figure 4.9. Steady-tate imulation waveform of the 65-W, 38-V/9-V, iolated QSC reonant converter. 87

121 4.5. Concluion The iolated QSC reonant converter i propoed to erve a a DCX for the iolated dc/dc converion in off-line power upply application, offering high power denity and high efficiency. Similar to the Φ reonant converter, the converter i operated mot efficiently at fixed witching frequency and duty ratio applied, and it feature trapezoidal voltage waveform on all witche. Full oft witching i achieved combining ZCS on, near ZCS off, ZVS on, and ZVS off within a wide load range, o the witching lo i minimized. In addition, compared to half/full-bridge converter (e.g. the C converter and dualactive-bridge converter), the propoed converter reduce the voltage tre on primary-ide witche to /3 of the input voltage, and thu enable more choice of low-voltage GaN device, which are more efficient becaue of their better figure of merit. Furthermore, the converter reduce tranformer turn ratio by /3, and thu enable le number of turn of the winding, lower winding lo and lower tranformer leakage inductance, making it uitable for high-frequency operation. For demontration, a 9-W, 88-V/9-V, 7-kHz prototype i built with -V egan FET. The tranformer deign and PCB layout are preented to minimize the tranformer leakage inductance and tray inductance. The prototype achieved a power denity of 7 W/inch3, and a flat efficiency curve with a peak value of 96 %. Furthermore, a 65-W, two-tage, off-line power adapter i deigned baed on the iolated QSC reonant converter. A 65-W, 38-V/9-V, -MHz iolated QSC reonant converter prototype i built with Enhancement-mode GaN HEMT. It ha an etimated high efficiency of 97.5%, and a high power denity of 75 W/inch 3. 88

122 The propoed iolated QSC reonant converter i not limited to low-power application. It alo ha the calability to be applied in high-voltage, high-power application. The reduced voltage tre on witche and tranformer are of particular interet for high voltage converter uch a the olid-tate tranformer, where challenge exit in the development and application of high-voltage (> kv) SiC power device and alo the inulation deign of the high-voltage tranformer. Effort hould be made thu in uch direction to explore and expand the application of the propoed converter. 89

123 Chapter 5. Semiconductor-baed Galvanic Iolation Thi chapter preent the tudy of a tranformational paradigm for galvanic-iolated power converter. The propoed galvanic iolation principle i fundamentally different from that of the traditional galvanic iolation olution, uch a the magnetic field-baed olution, electric field-baed olution, and optic-baed olution. Thi olution deliver the DM load power via emiconductor witche during their ON tate, while utaining the CM voltage and blocking the CM leakage current with thoe witche during their OFF tate. It i enabled by the unprecedented characteritic of WBG emiconductor power device, and it fully utilize thoe characteritic to yield ignificant circuit topology implification, dramatic power denity improvement, and effective galvanic-iolation that meet indutry afety tandard. 5.. Galvanic Iolation Requirement in the Safety Standard IEC695 Iolated power converter mut meet afety tandard requirement to validate their galvanic iolation. IEC695 i the mot widely applied afety tandard for power upplie today. It i intended for ue with information technology, buine, and telecom equipment. Other tandard exit for other indutrie, uch a IEC665 for audio and video, IEC66 for medical, IEC6 for laboratory upplie, IEC685 for electric vehicle charging ytem, and other. 9

124 5... Inulation Voltage Requirement IEC695 define five categorie of inulation, including: ) Functional inulation, which i only neceary for circuit operation. It i aumed to provide no afety protection. ) Baic inulation, which provide baic protection againt electric hock with a ingle level. Safety i provided by a econd level of protection uch a Supplementary inulation or protective earthing. 3) Supplementary inulation, which normally i ued in conjunction with Baic inulation to provide a econd level of protection in the event that the Baic level fail. 4) Double inulation, which i a two-level ytem, uually coniting of Baic inulation plu Supplementary inulation. 5) Reinforced inulation, which i a ingle-inulation ytem equivalent to Double inulation. Electric circuit rely upon inulation for operator protection, but deigning for afety require the premie that anything can fail. Therefore, afety tandard demand a redundant ytem with at leat two level of protection under the aumption that any ingle level may experience a failure, but the chance of two imultaneou failure in the ame pot i o improbable that it repreent an acceptable rik. The general requirement are that a ingle level of inulation i acceptable if the circuit i not acceible, but wherever there are acceible component, they mut be inulated from hazardou voltage by a Double-level ytem, and each level mut meet the inulation 9

125 pecification appropriate to the application. One qualification to thi tatement i that one level of protection could be protective earth provided by a conductive grounded encloure. Categorie are ued to define different clae of circuit and the type of inulation needed for each, a: ) Cla I Equipment: Sytem which ue protective earthing (e.g., a grounded metal encloure) a one level of protection and thu require only Baic inulation between the encloure and any part at hazardou voltage. ) Cla II Equipment: The ue of Double or Reinforced inulation to eliminate the need for a grounded metal encloure a well a a grounded power plug. 3) Cla III Equipment: Powered from a afety extra low voltage (SEV) ource ( 4.4 Vpk, ac or 6 Vdc) with no potential for generation of hazardou voltage internally, and therefore, requiring only Functional inulation. In IEC695, the tet voltage for the equipment inulation tet are pecified. For mot off-line power upplie, the tet voltage i.5 kvac, rm for functional, baic/upplementary inulation, and 3 kvac, rm for reinforced inulation Touch Current and Protective Conductor Current Requirement In IEC695, touch current (TC) i defined a the electric current through a human body when it touche one or more acceible part. A hown in Fig. 5. [4], if the circuit i unearthed, the current through the human body i "leakage" through tray or added capacitance acro the iolation tage, which i the tranformer in the figure. Thi current come from a relatively high voltage, high impedance ource, and it value i largely 9

126 unaffected by the operating voltage on the electronic circuit. In IEC695, the TC i meaured uing an impedance network (ZTC) a the meauring intrument, a hown in Fig. 5., which roughly imulate a human body. Figure 5.. Touch current from a floating circuit (with unearthed output) [4]. A B. µf 5.5 k k nf V out Figure 5.. TC meauring intrument an impedance network to roughly imulate a human body [4]. If the electronic circuit i earthed by protective earthing conductor, any leakage current from the iolation tage will be conducted to earth and will not pa through the human body. However, IEC695 alo ha pecified the limit for the protective conductor current (PCC), which i defined a the current flowing through the protective earthing conductor under normal operating condition. In IEC695, PCC i limited to 5% of the input current, for tationary, permanently connected equipment or tationary, pluggable equipment type B that ha a protective earthing conductor. 93

127 5.. Background of Exiting Galvanic Iolation Solution and Reearch Motive A dicued in Chapter, traditionally, there are three general olution to achieve galvanic iolation in power converter, including: ) the magnetic field-baed galvanic iolation; ) the electric field-baed galvanic iolation; and 3) the optic-baed galvanic iolation. In addition, for PV inverter application, tranformerle inverter topologie and aociated control cheme are propoed to limit the ground-loop current, which i a CM leakage current. The limitation of each olution are dicued below imitation of Magnetic Field-Baed Galvanic Iolation Magnetic field-baed galvanic iolation i provided either by air/magnetic-core tranformer or by a coupled inductor with dc-bia current (uch a the flyback converter tranformer). Traditionally, mot power converion ytem achieve galvanic iolation with thi olution, a dicued in Chapter. For grid-tied application, a line-frequency tranformer may be added at the grid interface, but it large volume and heavy weight caue low power denity. To improve the ytem power denity and reduce the ytem cot, iolated dc/dc converter with a high-frequency tranformer are employed in increaingly more application. Magnetic-core tranformer with high permeability material (e.g., Mn- Zn ferrite) are generally applied in iolated dc/dc converter in the witching frequency region between multi-khz and multi-mhz. Air-core tranformer have low permeability and thu are le effective to confine the magnetic field within a limited pace. For thi reaon, it i ued primarily for long-ditance wirele power tranfer application. However, in the VHF (3-3 MHz) witching-frequency region, air-core inductor or 94

128 magnetic-core inductor with low-permeability RF magnetic material (for core lo reduction) are built to achieve improved converter power denity [56-58]. In mot cae, magnetic component are the larget and mot expenive component in power electronic circuit and are reponible for a large portion of the power lo [78-8]. For a given converter topology, the value of magnetic component and capacitor and the total required energy torage vary inverely with the witching frequency, directly motivating increae in frequency to achieve miniaturization. However, the caling of paive component ize with frequency i a far more complex iue. In magnetic component, the caling depend on winding lo effect, magnetic material core lo characteritic, and heat tranfer limit, among other conideration. Currently, in the hundred-of-khz witching frequency region, the power denity of tranformer for iolated dc/dc converter ha reached.7 W/mm 3, and in the multi-mhz witching frequency region, the power denity ha reached.7 W/mm 3 [4-4]. In effort to further improve the power denity, reearch on magnetic component ha extended to a micro-fabricated on-chip or imilar cale [78-8]. With a ufficiently mall volume, the magnetic can be embedded in the ubtrate of the power circuit or within a econdary ubtrate and flip-bonded above the power circuit, helping to reduce the volume of the ytem. To date, though increaed dramatically in the lat two decade, energy denitie of magnetic component are till order of magnitude lower than thoe of capacitor [3] [56-57] [78-8], a hown in Table 5.. Thi i mainly becaue that, for the inductor, energy i limited by the current limit, whether thee arie from a thermal limit or magnetic aturation. A a reult, magnetic component remain the bottleneck toward further 95

129 improvement of power denity for iolated power converter. Furthermore, to build iolated dc/dc converter baed on tranformer, multiple circuit tage are required aide from the tranformer, including an inverter circuit and a rectifier circuit, which all contribute to ytem volume, power lo, and cot. For example, the tate-of-the-art power denity of the C converter with a MHz matrix tranformer and GaN HMET achieve.5 W/mm 3 [4]. Table 5.. Power denitie and energy denitie of the tate-of-the-art capacitor and inductor. Type f max (MHz) Power denity per area (W/mm ) Energy denity per volume (µj/mm 3 ) Metacapacitor [3] Deep trench capacitor X7R MCC ceramic capacitor 5 6 Metallized polymer film capacitor Tantalum electrolytic capacitor Aluminum electrolytic capacitor Microfabricated air-core toroid inductor [78] Microfabricated magnetic-core toroid inductor [78]..6 - Microfabricated magnetic-core racetrack inductor [78] imitation of Electric Field-Baed Galvanic Iolation Electric field-baed galvanic iolation ha been applied for ED driver [-4], battery charger [5-7], and power upply for liquid terilization [8]. Traditionally, electric field- 96

130 baed galvanic iolation i alo applied in iolated data tranfer application, uch a the digital iolator [9-] and iolated gate drive [-3]. In uch application, high CM impedance i required and embodied a a CM tranient immunity (CMTI) ratio to block CM noie in the preence of high CM dv/dt (e. g. 5 kv/µ). To meet the iolation afety tandard (e.g., IEC695), electric field-baed iolated power converter need to perform both high inulation voltage (.5 kvac, rm for the functional/baic/upplementary inulation, and 3 kvac, rm for the reinforced inulation) and low TC or PPC. Bulky Y-type film capacitor have been choen a the iolation capacitor for it high voltage rating and afety characteritic [-]. In [3], to achieve high power denity, high cot 3 kv ceramic capacitor are utilized. In either cae, inductor are till neceary in the power tage to create reonance. In addition, becaue an inverter circuit and a rectifier circuit are till required, there i no reduction of circuit tage. Thu, compared to the magnetic field-baed olution, power denity improvement of electric field-baed iolation i quite limited imitation of Optic-Baed Galvanic Iolation The optic-baed galvanic iolation, epecially the power over fiber [6, 7], provide the bet CM performance. However, thi olution uffer from low power denity and low efficiency, which i much lower than thoe of tranformer-baed or capacitive couplingbaed olution. Thi i mainly becaue laer tranmitter and receiver are bulky and inefficient. For example, a typical multi-junction photovoltaic-baed receiver uually ha 97

131 an efficiency lower than 5%. A power denity and efficiency are key requirement for power electronic circuit, optic-baed olution are uitable only for niche application imitation of Tranformerle Grid-tied Inverter In PV inverter application, the paraitic capacitance between the PV panel and the ground caue a CM leakage current, which mut be limited in order to meet the indutrial afety tandard and code, uch a the IEC 6755, VDE 6--, and VDE-AR-N 45. Tranformerle inverter topologie and their control cheme are derived to reduce thi CM leakage current [43-48]. The approach i to achieve contant CM voltage within the aymmetrical inductor-baed topologie, or to implement dc or ac decoupling within the ymmetrical inductor-baed topologie. With uch approache applied, the CM leakage current of the inverter i uccefully limited to ten of ma [43-48]. However, uch approache are not applicable to achieve galvanic iolation in general application for two reaon. Firt, they focu merely on the CM leakage current reduction, while other galvanic iolation related iue uch a the CM iolation voltage are not addreed. Secondly, when compared to with the limit in the afety tandard for off-line power upplie, uch a the IEC659 and U, it can be een that the CM leakage current level after reduction with thee approache i till much higher than the general TC limit and PCC limit. Thu, more tudy i required to extend thee approache to other application that require galvanic iolation. 98

132 5.3. Semiconductor-baed Galvanic Iolation Baic Circuit Structure and Potential Benefit: Thi reearch propoe a emiconductor-baed galvanic iolation olution. The baic idea of thi olution, a hown in Fig. 5.3, i to deliver the DM load power via active ac emiconductor witche during their ON tate, while utaining the CM voltage and blocking the CM leakage current with thoe ac witche during their OFF tate. When the ac witch i ON: When the ac witch i OFF: C OSS DM current CM leakage current (a) Figure 5.3. (a) Baic idea of the emiconductor-baed iolation; and (b) an example of the ac witch with bidirectional blocking capability. (b) A baic topology of the dc/dc converter with emiconductor-baed galvanic iolation i preented in Fig It i the SC iolation cell circuit dicued in [85-86]. Two pair of witche (S and S are in one pair, while S3 and S4 are in another pair) operate complementarily, o that the DM power flow are decoupled. Fig. 5.5 how the two phae of the circuit in one witching cycle, with the DM and CM current flow ignified, repectively. It how that, at any time, the converter ha at leat a pair of witch turned 99

133 off, erving a the iolation barrier. The witch output capacitance i connected in erie in the CM leakage current loop. The witche turned off erve to utain the CM iolation voltage and witch output capacitance limit the CM leakage current. Such function are very imilar to thoe of the iolation capacitor in the electric field-baed galvanic iolation hown in Fig... However, while the electric field-baed galvanic iolation uffer a continuou CM leakage current caued by the line input, the propoed olution uffer a repetitive pule CM leakage current, which i relevant to the witching operation of the iolated dc/dc tage, a dicued in more detail in ection 5.4. S 3 S V in C C 3 R oad S S 4 Figure 5.4. The SC iolation cell circuit -- a baic topology of the dc/dc converter with emiconductor-baed galvanic iolation (all witche are ac witche with bidirectional blocking capability). Phae I Phae II V in I DM C C 3 R oad V in C C o_s4 C o_s C o_s3 C o_s I DM C 3 R oad V CM I TC V CM I TC Z TC DM current in the t half witching cycle CM touch current (a) Z TC DM current in the nd half witching cycle CM touch current (b) Figure 5.5. DM and CM current flow in the SC iolation cell circuit in (a) Phae I, and (b) Phae II.

134 An application cenario of the propoed converter in off-line power upplie i illutrated in Fig The converter ha a two-tage tructure, including a rectifier tage with PFC function, and a dc/dc tage with the emiconductor-baed galvanic iolation. The dc/dc tage work a a dc tranformer (DCX). According to IEC695, a human-body impedance network (ZTC) i inerted to meaure the touch current (TC, or ITC), which i a CM leakage current caued by the line input. C CM V AC Active/Diode Rectifier I DM DC/DC Converter with Semiconductor-baed Galvanic Iolation R C CM I TC B A Z TC (Body Impedance) A B. µf 5.5 k k nf V out DM current for load power delivery CM touch current Figure 5.6. An off-line power upply application of the emiconductor-baed iolation. Compared with iolated dc/dc converter with traditional magnetic field or electric field-baed galvanic iolation olution, thi dc/dc converter with emiconductor-baed galvanic iolation ha the following benefit. ) It achieve direct iolated dc/dc converion without uing the inverter and rectifier circuit, reulting in a lower number of component.

135 ) It eliminate the magnetic component in the dc/dc tage, implifying the tructure and lowering the deign and manufacturing complexity. More importantly, thi olution can potentially achieve a higher power denity. Thi i becaue capacitor perform much higher power denity and energy denity compared with magnetic component, and they alo are eaier to integrate into power module with packaging technique Challenge The propoed method i baed on SC circuit with ac witche. It look imple, but ha many challenge a dicued below. The firt challenge i the CM leakage current. In order to meet the afety tandard requirement, the converter mut limit the CM leakage current to a low level (e.g..5 maac, rm TC limit in IEC695). A dicued in detail in ection 5.4, the normal operation of the SC iolation cell circuit uffer an impule CM leakage current at every turn-on event, becaue of the witch output capacitance. Therefore, the output capacitance of the witche need to be very mall. In addition, the witching frequency and ize reduction of paive component in the circuit are limited. The econd challenge i the converter voltage tranfer ratio. Thi challenge i addreed by tacking baic SC cell together or adapting more advanced SC circuit baed converter topologie. The third challenge i voltage regulation. A dicued in ection.3, SC converter, including reonant SC converter, uually do not have good voltage regulation capability. Thu, to achieve good voltage regulation, new circuit topologie with emiconductor-baed

136 galvanic iolation need to be derived. The voltage regulation alo can be provided by other circuit in the ytem. Some poible olution for both challenge and 3 are preented in ection 5.6. The fourth challenge, which i the one challenge that ha prevented the realization of emiconductor-baed galvanic iolation, i the limited characteritic of traditional ilicon (Si)-baed power device, including limited breakdown voltage, high ON reitance, high output capacitance, and low witching peed. The low breakdown voltage limit the iolation voltage rating. The high ON reitance limit the efficiency of the circuit. The high output capacitor provide a low impedance path for the CM mode current CM eakage Current Analyi Iolation Voltage Stre in Off-line Power Supplie In off-line power upplie, the primary ide of the iolated dc/dc tage i linked to the ac/dc tage, o in operation it ha acce to the ac line input. Meanwhile, a human body ha acce to the econdary ide of the iolated dc/dc tage. The iolated dc/dc tage mut utain the CM iolation voltage, and provide high impedance to limit the TC or PPC. During the operation of off-line power upplie, the iolation voltage tre acro the iolated dc/dc tage varie. Fig. 5.7 how the potential at different terminal of the iolated dc/dc tage in off-line power upplie with a Boot PFC circuit. For the analyi of the iolation voltage tre on the dc/dc tage, it i aumed that: ) the neutral power connection hare the ame potential with the ground; and ) the initial voltage drop acro the ZTC i aumed to be zero. The econd aumption i made becaue the pule CM 3

137 leakage current i dicontinuou and it damp to zero before every witching event. Thi mechanim i dicued in more detail in the following CM leakage current tudy in ection In off-line power upplie with a Boot PFC, the dc-link ground rail ha the earth potential during the poitive half line cycle where the line voltage i poitive, a hown in Fig. 5.7 (a) and (b). In the negative half line cycle where the line voltage i negative, the dc-link ground rail i applied with the line voltage, a hown in Fig. 5.7 (c) and (d). The dc-link i connected to the primary ide of the iolated dc/dc tage. On the econdary ide of the iolated dc/dc tage, depending on where the human body touche, the earth potential i applied to either the output poitive rail or the output ground rail. Vdc Vdc Vdc GND Vac N (+) Iolated DC/DC Stage R Vac N (+) Iolated DC/DC Stage R GND GND GND -Vdc GND GND Z TC Z TC (a) (b) Figure 5.7. Iolation voltage acro the iolated dc/dc tage in off-line power upplie with a Boot PFC circuit. (a) and (b) are during the poitive half line cycle where the line input voltage i poitive; (c) and (d) are during the negative half line cycle where the line input voltage i negative. Continued 4

138 Figure 5.7.: Continued Vac+ Vdc Vdc Vac+ Vdc GND Vac N (-) Iolated DC/DC Stage R Vac N (-) Iolated DC/DC Stage R Vac (<) GND Vac (<) -Vdc GND GND Z TC Z TC (c) (d) A a reult, in a Cla-I, off-line power upply with a Boot-PFC, if the output ground i earthed, the iolation voltage (VCM) acro the iolated dc/dc tage i a hown in Fig The voltage i zero during the poitive half line cycle, but equal to the line voltage during the negative half line cycle. V ac t V CM Figure 5.8. Iolation voltage acro the iolated dc/dc tage in a Boot-PFC baed, Cla- I, off-line power upply with an earthed output negative rail. In off-line power upplie with a Totem-pole PFC, the dc-link ground rail ha the earth potential during the poitive half line cycle where the line voltage i poitive, a hown in Fig. 5.9 (a) and (b). In the negative half line cycle where the line voltage i negative, the dc-link ground rail i applied with negative dc-link voltage, a hown in Fig. 5.9 (c) and 5

139 (d). The dc-link i connected to the primary ide of the iolated dc/dc tage. On the econdary ide of the iolated dc/dc tage, depending on where the human body touche, the earth potential i applied to either the output poitive rail or the output ground rail. Vdc Vdc Vdc GND (+) Vac N Iolated DC/DC Stage R (+) Vac N C Iolated DC/DC Stage R GND GND GND -Vdc GND GND Z TC Z TC (a) (b) GND Vdc GND GND (-) Vac N C Iolated DC/DC Stage R (-) Vac N C Iolated DC/DC Stage R -Vdc GND -Vdc -Vdc GND GND Z TC Z TC (c) (d) Figure 5.9. Iolation voltage acro the iolated dc/dc tage in off-line power upplie with a Totem-pole PFC circuit. (a) and (b) are during the poitive half line cycle where the line input voltage i poitive; (c) and (d) are during the negative half line cycle where the line input voltage i negative. A a reult, in a Cla-I, off-line power upply with a Totem-Pole PFC, if the output ground i earthed, the CM inulation voltage acro the iolated dc/dc tage i a hown in Fig. 5.. The voltage i zero during the line input poitive half cycle, but equal to the negative dc-link voltage during the line input negative half cycle. 6

140 V ac t -V dc V CM Figure 5.. Iolation voltage acro the iolated dc/dc tage in a Totem-Pole PFC baed, Cla-I, off-line power upply with an earthed output ground. With the iolation voltage applied acro the iolated dc/dc tage, the paraitic CM capacitance, which i the witch output capacitance in the propoed iolation olution, caue a CM leakage current. The analyi of the CM leakage current i a follow Generation mechanim of the CM leakage current In the SC iolation cell circuit, a pule CM leakage current i generated at every turnon event, charging up the output capacitance of the witche. Thi energy, tored in the output capacitance, diipate by the ame witche in the next turn-on event. Thi mechanim i illutrated in Fig. 5., where the output capacitance of S i charged up, while S3 diipate it own output capacitance energy that i tored earlier in the previou turn-on event. It i the major caue of the CM leakage current through human body or earth-connected protective conductor. To clarify, the CM leakage current we tudy in thi work i caued only by thi mechanim, wherea other portion of the CM leakage current caued by the paraitic CM capacitance to ground are out of the cope of dicuion. 7

141 C OSS C OSS C OSS energy get diipated S : OFF CM leakage current S 3 : ON V d_s3 Figure 5.. CM leakage current generation mechanim at every turn-on event (of S3 for example). Thi pule CM leakage current repeat at the witching frequency, reulting in an accumulated TC, which ha an envelope in phae with the line input, a hown in Fig. 5.. For analyzing the pule TC (ITC), the loop tray inductance (tray) and witch output capacitance (Co) all have zero initial condition, and the CM iolation voltage i applied a a tep input. Converter equivalent circuit a the TC path 6 nh 3 pf ~3 tray C o R d_on+r tray V DM 6 nh 3 pf ~3 C or C 3 V ac V CM tray C o R d_on+r tray. µf.5 k k I TC V CM t I TC 5 nf V out Human-body impedance (Z TC ) Figure 5.. TC equivalent circuit and the accumulated TC profile, in a Boot-PFC baed off-line power upply, when a human body touche the output ground (the circuit parameter are extracted in thi cae tudy, auming.7-kv SiC MOSFET CM7D). 8

142 Quantitative analyi of the TC In the quantitative analyi of the ITC, the DM voltage ource and the capacitor C and C3 equivalent circuit in Figure 5. i aumed to have zero impedance for analyi implification. Baed on the equivalent circuit, the ITC at every turn-on event with an ideal tep input voltage i decribed a: I TC ( t) V CM e tr tray t inh C o (C C o tray o R C R o tray tray ) C o (C o R tray ), (5.) where VCM i the magnitude of the CM voltage ource at the turn-on moment; tray i the loop tray inductance; Co i the witch output capacitance; and R i the 5-Ω reitance in the human-body impedance (ZTC), which dominate the total erie loop reitance. The plot of the ITC with different value of Co and tray are hown in Fig It can be een that: ) larger Co caue greater energy and RMS value of the ITC, and thu i not preferred; ) larger tray increae the loop CM impedance and thu damp the ITC. It reduce the peak current, but it doe not reduce the RMS value of the ITC, when the witching cycle i much larger than the circuit time contant. 9

143 C o = 3 pf, tray = 6 nh C o = 3 nf, tray = 6 nh C o = 3 pf, tray = 6 uh Figure 5.3. The calculated ITC at a ingle turnning-on event with different value of Co and tray at VTC=7 Vdc. A parametric tudy further explore the impact of Co and witching frequency (fw) on TC. Switching circuit model are built in the Matlab, baed on the equivalent circuit hown in Fig. 5., uing ideal witche in parallel with a contant Co. The firt tudy explore the impact of Co on TC. The parameter etting are hown in Tab. 5., and the reult are plotted in Fig Table 5.. Simulation parameter for tudying the impact of Co on ITC (embodied a the output votlage of ZTC) in the baic SC iolation cell circuit. Item Decription Specification Vac ine input (only the negative half line cycle applie a the CM voltage ource) 6 Hz / Vac, rm tray oop inductance 6 nh Co Switch output capacitance 3 pf nf fw Switching frequency khz

144 Simulation reult of the equipment without the protective earth conductor IEC695 limit for hand-held equipment with Z TC connected to protective earth conductor (if any) IEC695 limit for all equipment with acceible part not connected to protective earth Figure 5.4. RMS value of the ZTC output voltage in the imulation of the baic SC iolation cell circuit. The equivalent circuit i hown in Fig. 5. and the circuit parameter etting lited are in Table 5.. The econd tudy explore the impact of fw on TC. The ame Matlab witching circuit model are ued. The circuit parameter etting are lited in Tab. 5.3, and the reult are plotted in Fig Table 5.3. Simulation parameter for tudying the impact of fw on ITC (embodied a the output voltage of ZTC) in the baic SC iolation cell circuit. Item Decription Specification Vac ine input (only the negative half line cycle applie a the CM voltage ource) 6 Hz / Vac, rm tray oop inductance 6 nh Co Switch output capacitance 3 pf fw Switching frequency - khz

145 Simulation reult of the equipment without the protective earth conductor IEC695 limit for hand-held equipment with Z TC connected to protective earth conductor (if any) IEC695 limit for all equipment with acceible part not connected to protective earth Figure 5.5. RMS value of the ZTC output voltage in the imulation of the baic SC iolation cell circuit. The equivalent circuit i hown in Fig. 5. and the circuit parameter etting are lited in Table 5.3. From Figure 5.4 and 5.5 it can be een that TC increae a Co or fw increae. However, it i poible to meet the TC requirement in IEC695. In order to reduce TC, it i preferred to have low Co and low fw. Neverthele, low fw ha a ignificant negative impact on the power denity, a dicued in ection 5.7. Therefore, the tudy continue to explore TC reduction approache, a preented in the following ection TC Reduction Approache Increaing the CM Impedance The firt approach i to block the TC with a larger CM impedance. CM choke can be added to increae the CM impedance, and thi i valid ince the ac/dc tage of the off-line

146 power upply ha EMI filter. However, a hown in Fig. 5.6, adding extra CM choke with reaonable value (up to multi mh) into the TC loop doe not caue any ignificant change of the TC. Thi i becaue the TC loop already ha a dominating CM impedance, which i the 5-Ω reitance in the ZTC. The added CM impedance can reduce the peak value of ITC, a hown in Fig However, it doe not reduce it RMS value when the witching cycle i much greater than the circuit time contant, o it doe not reduce the output RMS voltage of ZTC. IEC695 limit for hand-held equipment with Z TC connected to protective earth conductor (if any) Simulation reult of the equipment without the protective earth conductor IEC695 limit for all equipment with acceible part not connected to protective earth Figure 5.6. RMS value of the ZTC output voltage in the imulation of the baic SC iolation cell circuit. The equivalent circuit i hown in Fig. 5. and the circuit parameter etting are lited in Table

147 Table 5.4. Simulation parameter for tudying the impact of fw on the ITC (embodied a the output voltage of ZTC) in the baic SC iolation cell circuit. Item Decription Specification Vac ine input (only the negative half line cycle applie a the CM voltage ource) 6 Hz / Vac, rm tray oop inductance 6 nh - mh Co Switch output capacitance 3 pf fw Switching frequency - khz Bypaing the TC The idea of thi approach i to bypa the TC from the ZTC with a hunt path which ha lower CM impedance, o that the TC ened by the ZTC can be reduced. One attempt i to add Y capacitor between the output end and the earthing ground. Thi i, however, infeaible for equipment without the protective earthing conductor. In addition, there alo exit a regulation on the ground fault current level, which et a limit on the Y capacitance. Furthermore, becaue the output end where a human body touche i random, it i poible to form a diagonal connection between the CM voltage ource and the ZTC. If thi happen, a hown in Fig. 5.7, the parallel CM-path circuit branche between point C and D are not ymmetrical becaue of the witching equence. In thi cae, intead of reducing the TC, additional TC will be reulted by the DM power delivery. 4

148 C V in S C C S 3 S S 4 C 3 R oad D V CM I TC Z TC (Body Impedance) C Y C Y Figure 5.7. Unymmetrical CM conduction path caued by the diagonal connection between the CM voltage ource and the ZTC, with Y capacitor added at the output. Thi reult in additional TC caued by the DM power delivery. Another attempt to bypa the TC from the ZTC i to add a hunt current ource in parallel with the converter, a hown in Fig Added hunt current ource I hunt V in S I DM C S 3 I DM C 3 R load DM current in the firt half witching cycle DM current in the next half witching cycle S S 4 CM compenation current provided by the added hunt current ource V CM I TC Reidual CM touch current een by the Z TC Z TC Figure 5.8. Adding a hunt current ource in parallel with the converter to bypa the ITC from the ZTC. 5

149 Thi added hunt current ource compenate the Co charging current by providing lower impedance for the CM leakage current to flow. A a reult, it reduce the TC ened by the ZTC. A imulation i conducted in PSIM to verify thi olution. Thi imulation i baed on a detailed circuit model, where device paraitic are conidered and each witch i compoed of two MOSFET in an anti-erie connection. The imulation circuit parameter are hown in Table 5.5. The imulation reult before and after adding thi hunt current ource are preented in Fig Note that thi i an effective approach to reduce the TC ened by the ZTC, o a to meet the IEC695 requirement. However, thi approach require a high band-width currentening circuit and current ource circuit, both of which are challenging to deign and implement. In addition, the current ource circuit i bridging the two iolated ide of the converter, and thu it alo need to utain high inulation voltage, which i 3kVac, rm for the reinforced inulation. Table 5.5. Simulation parameter for the hunt current ource olution to reduce the TC of the baic SC iolation cell circuit. Item Decription Specification Vac ine input (only the negative half line cycle applie a the CM voltage ource) 6 Hz / Vac, rm tray oop inductance 6 nh Co Switch output capacitance 3 pf fw Switching frequency khz 6

150 (a) (b) Figure 5.9. Simulation reult (a) before and (b) after adding a hunt current ource to bypa the TC from the ZTC. 7

151 Preventing the TC Generation The idea of thi approach i to prevent the pule TC generation at the turn-on event. To be more pecific, it i to recycle the Co energy diipated in the witche, and to utilize that energy to charge up the Co of the complementary witche during the dead time. Thu, it no longer draw energy from the CM voltage ource to charge up the Co at turnon event, and therefore, the pule TC can be eradicated. The principle i the ame a the ZVS operation of traditional power converter. In the SC iolated cell circuit, if the ZVS operation can be achieved during the dead time a hown in Fig. 5. (b), the Co energy can be tranferred to the complementary witche. V CM V d_s3 & V d_s4 S & S ON Dead band S 3 & S 4 ON (a) Dead band S & S ON V CM V d_s3 & V d_s4 S & S ON Dead band ZVS S 3 & S 4 ON (b) ZVS Dead band S & S ON Figure 5.. Operation waveform (a) before and (b) after implementing the ZVS operation to prevent the TC generation. However, in the SC iolated cell circuit, ZVS operation cannot be achieved naturally. Thi i becaue the load current doe not flow into or out of the junction point between the complementary witch pair (e.g., S and S3). It mean there are no witching interval where load current can be ued to dicharge the Co of one witch and charge the Co of it complementary witch, a if in a phae leg of traditional half/full-bridge converter. In 8

152 fact, the attempt to achieve ZVS operation utilizing the load current i to cycle the energy between Co and the external CM voltage ource. While thi i infeaible becaue of the circuit tructure, another external voltage ource can be utilized to force ZVS operation. The gate-drive power upply i choen a the alternative voltage ource. In the gatedrive circuit, auxiliary circuit are added to manually force the charging and dicharging of the Co. A hown in Fig. 5., for each ac witch, two bidirectional current ource circuit can be added into the gate-drive circuit. Equivalently, they erve a ditributed current ource charging or dicharging the Co, a hown in Fig. 5.. Gate Driver with Auxiliary Circuit to Force ZVS Operation Bidirectional Current Source D C o Gate Driver G S Bidirectional Current Source Gate-Drive Power Supply D C o Figure 5.. The olution to manually force ZVS operation by adding bidirectional currentource circuit in the gate drive to charge or dicharge the witch Co. The centralized current ource olution hown in Fig. 5.8 i a feedback compenation for the TC reduction. It ene the TC online, and then generate a cancelling current to reduce the TC. However, the forced ZVS operation olution hown in Figure 5. and 5. i a feed-forward compenation. It generate the command for ditributed current 9

153 ource to charge the Co voltage to the ened VCM, o that TC will be eliminated in the following witching event. Online VCM ening or prediction i therefore required for thi olution. A dicued in ection 5.4., the VCM i predictable for Cla I off-line power upplie with grounded output, o thi feed-forward TC compenation i achievable. S S S 3 S 3 V in C C3 R load S S S 4 S 4 V CM I TC Z TC (body Impedance) Figure 5.. Equivalent circuit to manually force ZVS operation with bidirectional currentource circuit in the gate drive to charge or dicharge the witch Co. Compared with the centralized current ource olution hown in Fig. 5.8, thi olution ha it own pro and con. The pro include: ) becaue the charging and dicharging are both implemented in the dead time, the bandwidth of the current ource can be lower; and ) there i no need for additional power upplie becaue the current ource hare the ame power upply of the gate-drive circuit. The con are the challenge in the deign and control of the current ource circuit. Thee circuit mut charge one witch and dicharge it complementary witch imultaneouly and the charging and dicharging current mut be coordinated, otherwie additional TC will reult, a dicued in detail below.

154 A erie of analye and imulation are conducted to invetigate how the operation of the ditributed current ource influence the TC. The firt cae tudied i hown in Fig It i to enable the current ource to charge only two witche (S3 and S4) during dead time, without charging or dicharging any other witche. The initial voltage acro the witche are labeled in purple on top of the witche in the figure. I COM V CM S S S 3 S 3 I COM V in V CM C C 3 R load S S S 4 S 4 I TC V CM Z TC (body Impedance) Figure 5.3. The firt cae tudied to implement forced ZVS operation. It i only to charge two witche (S3 and S4) during the deadtime, without charging or dicharging any other witche. The imulation reult how that additional TC i generated. In thi cae tudy, it can be een from the imulation reult that: ) the Co of S3 and S4 are not fully charged to VCM; ) the Co of S3, S4, S, and S are charged unintentionally, and the Co of S and S are dicharged unintentionally; and 3) an additional TC reult in dead time a a reult of the operation of the current ource. The reaon behind the reult i the KV applied for the VCM and the voltage acro all the

155 witche. Without coordinated dicharging of the complementary witche (S and S), the compenation current flow through ZTC, which i againt our intention. The econd cae tudied i hown in Fig It i to enable the current ource to charge two group of witche (S3 and S3 in one group, and S4 and S4 in the other group) during the dead time, without charging or dicharging the other witche. The initial voltage of the witche are labeled in purple on top of the witche in the figure. I COM V CM S S S 3 S 3 I COM V in V CM C C 3 R load S S S 4 S 4 I TC V CM Z TC (body Impedance) Figure 5.4. The econd cae tudied to implement forced ZVS operation. It i to charge two group of witche together, without dicharging any other witche. The reult how additional TC i generated. In thi cae tudy, it can be een from the imulation reult that: ) the Co of S3 and S4 are not fully charged to VCM; ) the Co of S, and S are charged unintentionally, and the Co of S and S are dicharged unintentionally; and 3) an additional TC reult in dead time a a reult of the operation of the current ource. The ame reaon tand behind the reult, which i the KV for the VCM and the voltage acro all the witche. It may

156 then be inferred that coordinated dicharging of the complementary witche (S and S) mut be implemented at the ame time, which lead to a third cae tudy. The third cae tudy i hown in Fig It charge two group of witche (S3 and S3 in one group, and S4 and S4 in the other group) during dead time, and in the meantime dicharge their complementary witche (S and S). The initial voltage of the witche are labeled in purple on top of the witche in the figure. In thi cae tudy, it can be een from the imulation reult that: ) the voltage acro S and S are fully tranferred to S3 and S3, o forced ZVS operation i uccefully achieved; and ) no additional TC i caued in the dead time. A a reult, the touch current i eliminated in thi cae tudy. I COM I COM V CM S S S 3 S 3 I COM I COM V in V CM C C 3 R load S S S 4 S 4 I TC V CM Z TC (body Impedance) Figure 5.5. The third cae tudied to implement forced ZVS operation. It i to charge two group of witche together, while dicharging their complementary witche. The reult how the voltage acro the witche i fully tranferred, and the TC i eliminated. Although the third cae tudy how that forced ZVS operation i achievable, the implementation of the ditributed current ource i till challenging. Two type of current 3

157 ource circuit are conidered, including a witching-type current ource circuit and a linear-type current ource circuit. A witching-type current ource circuit can be deigned baed on a bidirectional boot converter, a hown in Fig An enabling witch Sen i required to turn on and off the current ource, o a to prevent the continuou charging of com when the main power-loop witch Sx i cloed (i.e., the Co i horted by Sx). However, the deign of the converter i challenging for multiple reaon. Firt, the witche in the boot converter mut have the ame breakdown voltage rating a the main power-loop witche, becaue the iolation voltage alo i impoed on them. In order to meet the IEC695 iolation voltage requirement, the breakdown voltage rating need to be higher than 3 kvac,rm for reinforced inulation. Second, when built a a contant current ource, the boot converter need a large inductance and freewheeling path to hunt the inductor current. However, the converter i difficult to dicharge the witch Co with the large inductance. Third, the voltage ratio of the boot converter i high (>), and voltage control i difficult with a capacitive load. atly, the witch Co to be charged and dicharged i non-linear, o the charging and dicharging current are difficult to coordinate. S en com S com VCC S com C o + V DS - S x Compenation Current-Source Circuit Main-powerloop witch Figure 5.6. Example of a witching-type current ource circuit, baed on a bidirectional boot converter. 4

158 On the other hand, a linear current ource circuit can be deigned baed on BJT operating in their aturation region. Such a current ource i able to upply a relatively contant current depite the variation of output voltage. An example of a unidirectional linear current ource uing PSSISAY i hown in Fig It can be witched on or off by controlling the enable pin (i.e., the IN/OUT pin). However, the linear current ource only work when the input voltage i higher than the output voltage, o it i impoible to ue the gate drive power upply (~ V) to charge the witch Co up to the line input voltage. In addition, the linear current ource i a unidirectional circuit, o two et of the linear current ource circuit are neceary for charging and dicharging, repectively. A a reult, ixteen linear current ource circuit are required in total for the entire SC iolated dc/dc converter, which increae the circuit complexity ignificantly. C o Figure 5.7. Example of a unidirectional, linear-type current ource circuit. In ummary, both the witching-type current ource circuit and the linear-type current ource circuit have their unique limitation in implementation to achieve the forced ZVS 5

159 operation, which aim to fully eliminate the TC. However, in fact it doe not necearily need the complete elimination of TC to meet the IEC695 requirement. Intead, it alo work if the TC i partially compenated uch that it i regulated below the TC limit in the IEC695. Thi lead to the fourth olution, a dicued in detail below Partially Compenating the Switch Co Charging Current The idea of thi approach i to partially compenate the witch Co charging current at the turn-on tranient, o that it draw le energy out of VCM, and thu TC i reduced below the IEC695 limit. To provide the compenation charging current, ditributed currentource circuit are added to the gate-drive circuit, a hown in Figure 5. and 5.. The attempt to achieve ZVS operation i, in fact, to cycle the energy between Co and the external voltage ource, o the Co energy i not lot. However, in thi olution the Co energy i not recycled, o an external voltage ource i needed to repetitively tranfer the energy to Co. For thi reaon, the olution to partially compenate the witch Co charging current generate more power lo and thu, i le energy efficient. To implement the compenation current ource, a bidirectional boot converter can be deigned, a hown in Fig However, a dicued in ection 5.5.3, uch a deign ha many limitation. Thu, a buck-boot converter-baed current ource circuit i propoed, a hown in Fig Thi circuit i unidirectional becaue it need to upply only the compenation charging current (Icom) at the turn-on tranient, o only one active witch (Scom) i needed. The negative power upply required by the circuit i generated from the 6

160 gate drive power upply, a they hare the ource of the main power-loop witch a the ground reference. S Main-powerloop witch S com D com VCC com I com C o + V DS - I TC Compenation Current-Source Circuit S 3 Main-powerloop witch Figure 5.8. Example of a witching-type current ource circuit baed on the buck-boot converter, with the current flow ignified at the S turn-on event. The operation of waveform of thi current ource circuit i hown in Fig S COM ON S ON t t I TC I com t V CM V DS t t Figure 5.9. Operation of waveform of the buck-boot current ource circuit. 7 t

161 The key parameter of the circuit are derived a follow. After the witch Scom i activated, the inductor current i charged up linearly. At t, the inductor current i charged up to: V t. (5.) CC Icom( t) com At t, Scom i turned off, and then com tart to reonate with Co, tranferring it energy to Co, until the voltage of Co reache VCM. Auming Co ha contant capacitance and it voltage i charged only with the energy from com, the total energy tranferred from com to Co i: com I com ( t ) Co CM V. (5.3) Combining (5.) and (5.3), the on time of the witch Scom i derived a: VCM COM Co t V. (5.4) CC In order to reduce the TC effectively, the energy tranfer from com to Co hould occur a quickly a poible. The reonance frequency between com and Co determine the energy tranfer peed. Auming that the energy tranfer i completed within the voltage rie time (tf) of the main-power-loop witch during the witching tranient: t f T 4 com 4 C o. (5.5) 8

162 Baed on (5.5), the com to achieve the required energy tranfer peed i: com t f C o. (5.6) The imulation reult of the buck-boot converter-baed current ource circuit are hown in Fig TC i partially compenated by the Icom at the turn-on tranient. Becaue of uch compenation at every turn-on tranient, the overall TC i reduced. Figure 5.3. Operation waveform of the buck-boot current ource circuit. 9

163 5.6. Extended Topologie with Semiconductor-baed Galvanic Iolation Iolated DC/DC Converter with a High Voltage Tranfer Ratio The SC iolation cell hown in Fig. 5.4 i a baic topology without a voltage tranfer ratio. It can erve a a baic building block to derive advanced topologie with high voltage tranfer ratio. By tacking up thee building block, an iolated converter with a 3X voltage tranfer ratio i derived, a hown in Fig S S 3 Phae. C C V in C C 3 C 5 S S 4 S 5 S 7 Phae. C 3 C 4 R oad C C V in S 6 S 8 S 9 S C 3 C 4 R oad C 5 C 6 C 5 C 6 S S (a) (b) Figure 5.3. (a) A 3X iolated boot dc/dc converter (where all witche are ac witche with bidirectional blocking) and (b) the two witching phae of the converter. Following thi idea, advanced SC circuit alo can be modified to achieve galvanic iolation. For example, the Dickon converter can be modified into an iolated dc/dc converter, a hown in Fig

164 C S S 3 S S 4 S 5 S 6 S 7 S 8 S 8 Switche w/ unidirectional AC AC blocking Switche C Switche 4 C C 3 C out R oad S 9 S 9 (a) Phae. Phae. C C 3 C C 4 R oad Cout C C C 3 C 4 C out R oad (b) Figure 5.3. (a) A 4X iolated Dickon converter, and (b) the equivalent circuit of the two witching phae Iolated DC/DC Converter with Extended Iolation Voltage The iolation voltage rating of the baic SC iolation cell circuit equal the witch breakdown voltage. To achieve a higher iolation voltage, iolated dc/dc converter can be derived from the baic SC iolation cell circuit. A hown in Fig (a), a converter i compoed of everal SC iolation cell connected in erie. Thee cell take turn operating and delivering energy to the next one. The enabling ignal of the cell are hown in Fig (b). Thi tructure and control trategy enable a higher iolation voltage. A cell that 3

165 i not enabled ha the ame iolation voltage rating a the witch voltage rating. When it i enabled and begin to operate, it loe it iolation voltage blocking capability becaue it witch body diode would conduct. However, out of the n erie-connected cell, there i only one cell operating at a time, o the other (n-) connected cell will continue to provide the iolation voltage blocking capability. The number n needed in the converter depend upon the voltage rating of the witche. For example, to meet the 3 kvac, rm reinforced iolation voltage requirement in IEC695, if. kv rated witche are ued, the converter need four cell in erie, to provide a 4.8 kv iolation voltage rating. If 4.5 kv rated witche are ued, the converter need only one cell. Iolation Voltage (3-kV rm ) Tet Schematic The Converter Iolation Voltage Rating = n Switch Breakdown Voltage V in SC Iolation Cell SC Iolation Cell... SC Iolation Cell n V out (a) Cell Enable Signal Cell Enable Signal Cell 3 Enable Signal (b) Figure (a) Iolated dc/dc converter with extended iolation voltage and the inulation tet chematic; (b) enabling ignal of the SC iolation cell (n=3, for example). 3

166 Iolated DC/DC Converter with a Voltage Regulation Function The baic SC iolation cell circuit and the iolated dc/dc converter hown in Figure all have fixed voltage tranfer ratio, which lack the voltage regulation function. Thee converter can erve a the DCX in two-tage ac/dc or dc/ac converter, where the voltage regulation function i provided by the ac/dc or dc/ac tage. For application where voltage regulation of the ioalted dc/dc converter i needed, inductor mut be integrated into the converter. Fig how a derived buck-boot converter with emiconductorbaed galvanic iolation. An additional witch S5 provide the freewheeling current path for the inductor during dead time. S S 3 V in m S 5 C out R oad S S 4 V CM I CM (I TC ) Z TC (body Impedance) DM current in the firt half witching cycle DM current in the next half witching cycle ine-frequency CM leakage current Inductor free-wheeling current during the dead time Figure An iolated buck-boot dc/dc converter with a voltage regulation function (all witche are ac witche with bidirectional blocking capability). 33

167 Iolated AC/DC converter and Iolated DC/AC converter Iolated ac/dc converter can be deigned with a two-tage tructure, including an ac/dc tage with PFC function, and a DCX with the emiconductor-baed galvanic iolation, a hown in Fig Such converter can be ued in off-line power upplie, uch a the vehicle on-board charger, ED driver, power adapter for conumer electronic, etc. Vac Bridge/ Bridgele PFC Circuit DCX with Semiconductorbaed Iolation R oad Figure Two-tage tructure of an ac/dc converter. Iolated dc/ac converter alo may be deigned with a two-tage tructure, including a DCX with a emiconductor-baed galvanic iolation, a hown in Fig Application of uch converter include the PV inverter. V DC DCX with Semiconductorbaed Iolation Inverter Vac Figure Two-tage tructure of a dc/ac converter Deign toward High Efficiency and High Power Denity Thi ection preent the deign conideration of the baic SC iolation cell circuit, to achieve high efficiency and high power-denity for the DM power delivery. 34

168 5.7.. Switche The firt tep of the deign i to elect witche for the converter. To meet the IEC695 iolation voltage requirement, the witche mut have high breakdown voltage to utain.5 kvac, rm for the baic and upplementary iolation, or 3 kvac, rm for the reinforced inulation. In addition to the high breakdown voltage, the witche alo need to have bidirectional blocking capability, becaue the applied iolation voltage in the tet i bidirectional. For each ac witch, intead of uing two dicrete power device in anti-erie connection, it i preferred to ue a ingle dicrete device or device die with bidirectional blocking, to achieve lower device paraitic, a maller footprint, and higher power denity. In addition, to reduce the TC, the witche alo need to have low output capacitance, a dicued in ection To perform at high efficiency, the witche mut have low on-reitance (Rd_on), to reduce the conduction lo. The ideal converter efficiency i: Rload, (5.7) R n R load d_ on where Rload i the load reitance and n i the total number of witche (n=8 if each ac witch i compoed of two witche in anti-erie connection). In addition, it i preferred to have fat witching peed, to reduce the witching lo. Alo, to perform high converter power denity, the witche need to have high thermal conductivity and high maximum junction temperature. A comparion between the critical parameter of tate-of-the-art SiC MOSFET v. Si MOSFET/IGBT i hown in Table 5.6. It can be een that it i impractical to implement 35

169 the emiconductor-baed galvanic olution with Si device becaue they either caue low efficiency becaue of the high on-reitance, or caue exceive TC becaue of the large output capacitance. To apply multiple device in parallel i a common practice to reduce the device on-reitance, but it will increae the witching lo and caue a higher TC becaue of the increaed device output capacitance. The latet SiC device, the coming vertical GaN device [49-5], and the emerging bidirectional power device [5] provide unprecedented propertie, which potentially enable their practical implementation. Table 5.6. Comparion between critical parameter of tate-of-the-art SiC MOSFET v. Si MOSFET/IGBT. Part Number Mat eria l Continuou Drain 5 C Drain- Source Breakdown Voltage Drain-Source On-State Reitance (Rd_on) Output Capacitance Vd= V CM5D SiC 9 A V.5 Ω 35 pf CM75DU-4F Si 75 A V.5 Ω 9 pf CM7D SiC 4.9 A 7 V. Ω 9 pf WPH43 Si.5 A 7 V 8. Ω 85 pf Switching Frequency The next tep i to determine the witching frequency baed on the output capacitance of the elected witche and the TC and PPC limit in IEC695. A dicued in ection 5.4.3, if no meaure are taken to actively reduce the TC, the converter need to operate at a low witching frequency to uppre the TC below the IEC695 limit. However, a low witching frequency ha ignificantly negative impact on the power denity and energy efficiency. At a low witching frequency, the converter require higher energy tored in 36

170 the witched capacitor, and thi lead to large capacitance of the witched capacitor and thu, lower power denity. In addition, to achieve the ame average DM output current, the RMS current of the witche and witched capacitor increae a the witching frequency decreae, which caue higher conduction lo and thu, lower efficiency. Neverthele, a dicued in ection 5.5, the witching frequency can be increaed by adding auxiliary current ource circuit to reduce the TC Paive Component Once the witching frequency i elected, the witched capacitor (C and C3) of the SC iolation cell circuit can be deigned baed on the DM power delivery requirement. In operation, the energy tranferred by the witched capacitor C i: C V C V E C V dc V dc, (5.8) where V and V are the C voltage before and after the energy tranfer; Vdc i the average C voltage; and ΔVdc i C voltage ripple. The energy tranferred by C alo i determined by the load power (Pload) within the half witching cycle (Tw), a decribed in: Pload Tw Pload E, (5.9) f w Baed on (5.8) and (5.9), the required capacitance of C i derived: Pload C f V V. (5.) w 37 dc dc

171 Choice of the tate-of-the-art capacitor are lited in Table 5.. All capacitor electrical characteritic hould be conidered in the capacitor election, including the capacitance, voltage rating, current rating, ESR, ES, and operation temperature. The DM current can be configured into two general pattern, including: (a) the hardwitching current pattern; and (b) the reonant current pattern with ZCS on and off [86], a hown in Fig (a) (b) Figure Two DM current pattern including (a) the hard-witching current pattern, and (b) the reonant current pattern with ZCS on and off. The equivalent circuit for the DM current loop i a erie RC circuit, where the loop reitance i a paraitic reitance of the PCB trace and the component, and the loop inductance i the tray inductance of the PCB trace and the component. The hardwitching current pattern can be achieved with a large capacitance of the witched capacitor. The reonant current pattern can be achieved when the witching frequency 38

172 matche the frequency of the reonance between the witched capacitor and the DM current loop inductance. To achieve both high efficiency and high power denity, it i preferred to operate the converter at a high witching frequency and achieve the reonant current with ZCS on and off, with the TC actively uppreed to meet the afety tandard. In thi way, both the witching lo and conduction lo i minimized and a high power denity i achieved Preliminary Prototype and Experimental Verification A preliminary 4-V, 4-W prototype of an SC iolation cell circuit i hown in Fig The pecification of thi converter are hown in Table 5.7. The prototype i built to verify both the DM power delivery performance and the CM iolation performance. To verify the TC without the compenation current ource circuit firt, thi preliminary prototype i built to work at khz. Figure A preliminary 4-V, 4-W prototype of the SC iolation cell circuit. 39

173 Table 5.7. Specification of the preliminary SC iolation cell circuit prototype. Item Decription Specification V in Input voltage rating 4 V P out Output power rating 4 W C, C, C 3 Input/output capacitor and witched capacitor 45-V/56-µF, Electrolytic tray Stray inductance 46 nh S ~S 4.7-kV SiC MOSFET CM7D f Switching frequency khz Prototype dimenion 83 mm 73 mm 65 mm DM power delivery tet The converter ha hard-witching DM current. The DM power delivery experimental waveform are hown in Fig At low witching frequency ( khz), the witching lo i negligible. The conduction lo caued by the high on-reitance of the witche i the major lo of the converter. The converter efficiency curve i hown in Fig µ/div V g_s3 (5 V/div) V g_s (5 V/div) I S3 ( ma/div) I S ( ma/div) Figure Experimental waveform of the DM power delivery at -W output power. 4

174 DM Power Efficiency (%) DM Output Power (W) Figure 5.4. Experimental DM power delivery efficiency of the prototype TC Meaurement A TC tet i conducted with the SC iolation cell circuit prototype connected after a diode rectifier circuit, a hown in Fig The tet i done without any auxiliary circuit to actively reduce the TC. The experimental waveform are hown in Fig C CM V ac Diode Rectifier SC Iolation Cell Circuit R I TC B A Z TC (Body Impedance) C CM A V AB B. µf 5.5 k k nf V TC Figure 5.4. TC tet of the ioaltion cell circuit prototype in an off-line power upply application. 4

175 V TC (Z TC output ) ( V/div) V AB (voltage acro Z TC ) (5 V/div) V ac (line input) (5 V/div) Figure 5.4. Experimental reult of the TC meaurement with a -Vrm CM voltage ource. The weighted touch current reult i.4 ma, which meet the IEC695 tandard requirement (.5 ma). Fig. 5.4 how that the weighted touch current reult i.4 ma, which meet the IEC695 tandard requirement (.5 ma). The tet reult i without any auxiliary circuit to actively reduce the TC Tet of the TC Reduction Circuit A dicued in 5.5.4, TC can be reduced by partially compenating the witch Co charging current at the turn-on tranient. To implement thi olution, a et of buck-boot converter baed current ource circuit are deigned and added to each witch, to charge up the witch Co. The circuit diagram i hown in Fig. 5.8 and repeated in Fig The tet waveform are hown in Fig By adjuting the pule width of Scom, the Co charging current upplied by the current ource circuit can be modulated. 4