DIGITAL SIGNAL PROCESSING IV

Transcription

1 DIGITAL SIGNAL PROCESSING IV Learning Guide First Semester 208 Module Code: EIDSV4A VUT Vaal University of Technology

2 Learning Guide Digital Signal Processing IV ii INDEX PART I Module Information. Word of welcome.... iii 2. Contact persons.. iii 3. Rationale for the module.... iii 4. Prerequisites iii 5. Learning material and reference textbooks. iii 6. Assessment..... iii 7. Icons used in this study guide v PART II Learning Units Unit. Chapter Discrete Systems and Signals Chapter 2 Time Domain Analysis Chapter 3 Z Transform Unit 2 4. Chapter 4 Frequency Domain Analysis Chapter 5 Discrete Fourier Transform Chapter 6 Digital Filters Unit 3 7. Project 7. Project outcome Project schedule Assessment

3 Learning Guide Digital Signal Processing IV iii. WORD OF WELCOME The Department of Process Control and Computer Systems welcomes you as a student to the Faculty of Engineering at the Vaal University of Technology. The department strives towards integration of existing knowledge with new knowledge and to afford the student the ability to think logically, gain knowledge of Electrical Engineering, and specifically Digital Signal Processing, in order to make a positive contribution to the field of Industrial Instrumentation and Electrical Engineering, once you have completed your studies. 2. CONTACT PERSONS Title and Surname Office Telephone number and address Prof MO Ohanga (HOD) R marcelo@vut.ac.za Ms. R Mwale (Administrator) R refilwem@vut.ac.za Mr. TV Maloka (Lecturer) S malokat@vut.ac.za 3. RATIONALE FOR THE MODULE On completion of this module you should be knowledgeable in the basic concepts underlying linear discrete-time systems, sampling of analogue signals, difference equations, convolution summation, z-transform, frequency response, digital Fourier transform techniques and digital filters. 4. PREREQUISITES The z transform as well as complex algebra, are used extensively in this course. It is therefore strongly recommended that students successfully complete the courses in Control Systems III (EIBEH III) and Mathematics II (AMISK II), before commencing with their studies in Digital Signal Processing IV. 5. LEARNING MATERIAL AND REFERENCE TEXTBOOKS This learning guide as well as the course material and previous evaluations, will be made available to students at the beginning of the semester. Additional reference textbooks: a) Lynn, P.A. and Fuerst, W., Introductory Digital Signal Processing withcomputer Applications. b) Mayhan, R.J., Discrete-Time and Continuous Linear Systems. c) Oppenheim A.V. and Schafer R.W., Digital Signal Processing. Additional information may be available from: The lecturer will not respond to from students. 6. ASSESSMENT Module assessment will take place on a continuous basis, and for this purpose the module is divided into three units. Unit : Chapters to 3 (weight = 40%) Unit 2: Chapters 4 to 6 (weight = 40%) Unit 3: Project (weight = 20%)

4 Learning Guide Digital Signal Processing IV iv i) Module assessment: To successfully complete each unit, students must receive a unit mark of at least 50%. To successfully complete the module, students must complete all the units. A student that successfully completes the module will receive a module mark according to the following summative assessment schedule: Module% = 0.4Unit% 0.4unit2% 0.2unit3% The continuous assessment programme does not allow for supplementary or rewritten examinations. Students that fail to complete this module, must resume their studies by completing all units again during a subsequent semester. ii) Unit assessment (½ hour session): Assessment of unit is scheduled for Thursday March 208 at 0h00. Students that fail to receive 50% for unit, will be offered a second and final opportunity to complete unit on Thursday 0 May 208 at 0h00. Students who successfully complete the final assessment, will however receive a maximum mark of 50% for unit. Students who were unable to attend the first assessment session, will receive the full mark obtained for the final assessment of unit. A student that fails to receive 50% for the final attempt to complete unit, fails the module. The assessment venue is lecture room S205 (main campus), and as arranged at the Secunda campus. iii) Unit 2 assessment (½ hour session): Assessment of unit 2 is scheduled for Thursday 29 March 208 at 0h00. Students that fail to receive 50% for unit 2, will be offered a second and final opportunity to complete unit 2 on Thursday 0 May 208 at h35. Students who successfully complete the final assessment, will however receive a maximum mark of 50% for unit 2. Students who were unable to attend the first assessment session, will receive the full mark obtained for the final assessment of unit 2. A student that fails to receive 50% for the final attempt to complete unit 2, fails the module. The assessment venue is lecture room S205 (main campus), and as arranged at the Secunda campus. ivi) Unit 3 assessment: For the purpose of assessing unit 3 (project), each student will prepare and demonstrate a Finite Impulse Response digital filter of length three, constructed according to the guidelines given in the learner guide for unit 3. A clear photograph showing the project with the student s student card (or other clear identification), must also be available for assessment and moderation. Assessment of unit 3 is scheduled for Thursday 9 April 208 at 0h00. Students that fail to receive 50% for unit 3, will be offered a second and final opportunity to complete unit 3 on Thursday 26 April 208 at 0h00. Students who successfully complete the final assessment, will however receive a maximum mark of 50% for unit 3. Students who were unable to attend the first assessment session, will receive the full mark obtained for the final assessment of unit 3. A student that fails to receive 50% for the final attempt to complete unit 3, fails the module. The assessment venue is the lecture room, S205.

5 Learning Guide Digital Signal Processing IV v v) Module Portfolio: Students will not be required to assemble a module portfolio individually. The lecturer, however, will assemble a module portfolio that will include all question papers and memoranda, as well as the study guide, mark sheets and class registers. The examination office currently archives all examination scripts in order to be available as assessment evidence for unit and unit 2. Lecturers should include each student s project photograph in the module portfolio, as assessment evidence for unit 3. The module portfolio must be safeguarded for at least three years for moderation purposes. 7. ICONS USED IN THIS STUDY GUIDE Estimated study time 7. Opening remarks and introduction Outcomes Study the following passage thoroughly Practical work Exam questions and assessment Section still under construction

6 EIDSV4 Discrete Systems and signals Learning Guide Unit -. LEARNING GUIDE - UNIT : DISCRETE SYSTEMS AND SIGNALS The objective of this learning unit is to introduce students to the fundamental properties of discrete systems and signals. You should spend approximately 0 hours on this learning unit. LEARNING UNIT OUTCOME After completion of this learning unit, students should be able to: Define Shannon s sampling theorem. Define the impulse and step function. Sketch and perform elementary algebraic operations with discrete signals. Construct difference equations and block diagrams for discrete systems. Determine the response of linear, time invariant system to various inputs.

7 EIDSV4 Time Domain Analysis Learning Guide Unit 2-2. LEARNING GUIDE UNIT : TIME DOMAIN ANALYSIS The objective of this learning unit is to introduce students to the analysis of discrete systems in the time domain, using the principle of the convolution sum. You should spend approximately 5 hours on this learning unit. LEARNING UNIT OUTCOME After completion of this learning unit, students should be able to: Describe digital signals in terms of impulse functions. Determine the impulse response of a discrete system. Use the convolution method to calculate the response of a discrete system for typical input signals.

8 EIDSV4 Frequency Domain Analysis Learning Guide Unit 3-3. LEARNING GUIDE UNIT : Z TRANSFORM The objective of this learning unit is to introduce students to the powerful z transform method to analyze discrete systems in the frequency domain. You should spend approximately 20 hours on this learning unit. LEARNING UNIT OUTCOME After completion of this learning unit, students should be able to: Define the z transform X(z). Verify the important properties of the z transform. Determine the z transform X(z) for time functions x(k). Use the method of long division and partial fractions to find the inverse z transform of X(z).

9 EIDSV4 Frequency Domain Analysis Learning Guide Unit LEARNING GUIDE UNIT 2: FREQUENCY DOMAIN ANALYSIS The objective of this learning unit is to introduce students to the response of discrete systems to sinusoidal input signals. You should spend approximately 0 hours on this learning unit. LEARNING UNIT OUTCOME After completion of this learning unit, students should be able to: Relate the transient response of a system to the roots of the denominator of the system function H(z). Determine the frequency response of the system H(), from H(z).

10 EIDSV4 Discrete Fourier Transform Learning Guide Unit LEARNING GUIDE UNIT 2: DISCRETE FOURIER TRANSFORM The objective of this learning unit is to introduce students to the discrete Fourier transform as an instrument for finding the frequency spectrum of discrete signals, You should spend approximately 0 hours on this learning unit. LEARNING UNIT OUTCOME After completion of this learning unit, students should be able to: Determine the frequency spectrum of non periodic signals. Determine the frequency spectrum of periodic signals.

11 EIDSV4 Digital Filters Learning Guide Unit LEARNING GUIDE UNIT 2: DIGITAL FILTERS The objective of this learning unit is to introduce students to some of the important techniques used when designing digital filters. You should spend approximately 20 hours on this learning unit. LEARNING UNIT OUTCOME After completion of this learning unit, students should be able to: Design finite impulse response filters. Design infinite impulse response filters.

12 EIDSV4 Project Learning Guide Unit LEARNING GUIDE UNIT 3: PROJECT LOW PASS FIR FILTER The objective of this learning unit is to give students the opportunity to design a Finite Impulse Response filter of length three, and to use the filter to recover the fundamental frequency from a rectangular input signal. You should spend approximately 20 hours on this learning unit. 7. Project Outcome After completion of this project, students will be able to demonstrate the operation of a low pass FIR structure, filtering the fundamental frequency from a rectangular input signal. 7.2 Project Schedule To complete this project, students will be required to construct a FIR low pass filter of length three with cut off frequency c of rad/sec. A pulse generator will provide the input signal of rad/sec, and the filter must extract the fundamental harmonic from this input. Both the input signal and the output signal will be displayed by means of LED s. A block diagram of the system is shown in Figure P. x(t) y(k) Pulse generator LED display Low pass FIR filter LED display Figure P

13 EIDSV4 Project 7-2 Learning Guide Unit Filter design guide For simplicity, a filter of length N = 3 will be constructed. The impulse response of a low pass FIR filter is given by: c T sin(k - ) c T h(k) = (k - ) c T. Equation P We will use a sampling frequency s = 0 r/s and cut-off frequency c = r/s. (which is also the frequency of the input square wave). Therefore c = 0. s. With T = 2/ s, N = 3, = (N-)/2 = and using Equation P, we find for h(k): 0 (2/ ) sin[(k -)(0 )(2/ )] h(k) = s s s s [(k -)(0 )(2/ )] s s sin[(k -)(0.2)] h(k) = 0.2, for k = 0, and 2. Equation P2 [(k -)(0.2)] From Equation P2, h(0) = 0.87, h() = 0.2 and h(2) = To simplify the electronics and to amplify the output signal somewhat, we will assume h(0) = h() = h(2) = 0,25. The final structure is shown in Figure P2. x(k) 0.25 x(k-) z y(k) x(k-2) z Figure P2 The transfer function of the filter is given by: H(z) = z z -2. Equation P3 Because of the low order of the filter (N = 3), the cut-off characteristics of this filter is not very good. Nevertheless, using a sampling frequency s = 0 r/s (f s =.595 Hz.) which is ten times the cut-off frequency c = r/s (f c = Hz.), will result in the attenuation of the third harmonic (=3), fifth harmonic (=5) and seventh harmonic (=7) frequencies contained in the input signal. Given that the sampling period T = /f s = /.595 = sec, the frequency response of the filter, H(e jt ), may be calculated. From Equation P3: H(e jt ) = e -jt 0.25e -j2t H(e j0.628 ) = e -j e -j.256 = 0.25[ ] The values of H(e jt ), also just denoted by H(), for = 0 to 0, are tabulated in Figure P3. A graph of the frequency response H() is also shown.

14 (rad/sec.) H() H() EIDSV4 Project Learning Guide Unit 3 Figure P3 H() Ideal c s /2 7-3 The network shown in Figure P4 will be used to implement this filter. The bucket brigade x(k) x(k-) x(k-2) 00k MAC 00k 00k v - y(k) 00k x(t) S0 x(k) S x(k-) S2 x(k-2) x(t) CP2 - CP - CP0 - C0 C C2 CP0 CP CP2 CP0 CP CP2 CP0 Sampling period = sec Start of sampling period Next sampling period Start of next sampling period Figure P4

15 EIDSV4 Project Learning Guide Unit Capacitor C0 is used to store the most recent sample x(k) obtained from the input signal. Capacitor C is used to store the previous value x(k-) of the input signal while capacitor C2 stores the oldest sample x(k-2). At the start of each sampling interval, all the stored values are shifted one position to the right. First, clock pulse CP0 closes switch S2 and transfers the stored value on C, to C2 (which is the value of x(k-2) during this sampling interval). Next clock pulse CP closes switch S and transfers the stored value on C0 to C (which is the value of x(k-) during this sampling period). Finally clock pulse CP3 operates switch S0 and sample the current value x(k) of the input signal. The filter output y(k) is calculated by means of the MAC operational amplifier. From Figure P4, y(k) is equal to v, the voltage at the positive input of the MAC operational amplifier that is connected in voltage follower mode. Applying Kirchoff s current law at the v node: [x(k)-v]/00k [x(k-)-v]/00k [x(k-2)-v]/00k = v/00k [x(k)-v] [x(k-)-v] [x(k-2)-v] = v 4v = x(k) x(k-) x(k-2) v = ¼x(k) ¼x(k-) ¼x(k-2) But y(k) = v, y(k) = ¼x(k) ¼x(k-) ¼x(k-2). This is the required filter response for our low pass filter. Strictly speaking, we should sample the output value of the MAC operational amplifier only after x(k), x(k-) and x(k-2) have been shifted into their correct positions (that is after clock pulse CP3). For our purposes however, the continuous output of the operational amplifier will be a good enough representation of y(k) Clock generation The CD4022 is a divide by 8 counter and will be used to generate the CP0, CP and CP2 clock pulses. A 555 timer generates the master clock to the CD4022 counter and after every eighth master clock pulse, a pulse (CP0) will appear on pin 2 of the CD4022 counter, as shown in Figure P5. One master clock pulse after this, a pulse (CP) will appear on pin 3 of the CD4022 counter. After another master clock pulse, a pulse (CP2) will appear on pin of the CD4022 counter. This process will repeat itself after 8 master clock pulses (the other five pulses available from the CD4022 are not used). The sampling period starts when clock pulse CP0 goes high and ends just before clock pulse CP0 goes high again (the sampling period is equal to sec which corresponds to the sampling frequency of 0 rad/sec). The complete circuit to generate clock pulses CP0, CP and CP2, is shown in Figure P6.

16 EIDSV4 Project Learning Guide Unit Master clock (provided by 555 timer) Duration of 8 pulses = sec. Next sample period (8 master clock pulses) Clock pulse 0 (CP0) pulse 0 on pin 2 of CD4022 Clock pulse (CP) pulse 2 on pin 3 of CD4022 Clock pulse 2 (CP2) pulse 4 on pin of CD4022 Figure P5 2.7 k reset inhibit 4.7 k clock CP CD V battery CP0 CP Master clock k 0F Test probe LED Figure P6 A test probe consisting of a k resistor in series with a LED, may be used to check whether the master clock and clock pulses CP0, CP and CP2 are present. The master clock frequency is a bit more than 0 Hz and the LED flickering can still be observed. The frequency of clock pulses CP0, CP and CP2 is low and can be easily monitored with the test probe. (Note: The master clock, CP0, CP and CP2 do not have to be displayed when demonstrating the final system.)

17 7.2.3 Filter circuit EIDSV4 Project Learning Guide Unit 3 The filter network outlined in Figure P4, will be realized with the circuit in Figure P7. Three of the four available switches on the CD4066 quad switch are used to sample x(t), x(k) and x(k-) ½LM358 (I-a) CP2 3 S0 enable 2 8 x(k) x(t) Input signal CP x(k) 5 4 S CD4066 S enable 2 3 C0 C F ½LM358 (I-b) F 00k x(k-) 00k ½LM358 (II-b) 6 5 MAC 7 y(k) 9V battery ½LM358 (II-a) CP0 x(k-) 6 8 S2 enable 7 9 C2 0.F x(k-2) 00k 00k k LED Figure P7 This circuit can only be tested if clock pulses CP0, CP and CP2 from the circuit in Figure P6, are connected to S2 enable (pin 6 of the CD4066), S enable (pin 5 of the CD4066) and S0 enable (pin 3 of the CD4066) respectively. If 9V from the battery is applied to the x(t) input (pin of the CD4066), the y(k) output from the MAC operational amplifier must increase, which may be verified with the y(k) LED becoming progressively brighter. Zero volt (negative battery voltage) connected to the x(t) input, must result in the LED becoming progressively dimmer.

18 EIDSV4 Project Learning Guide Unit Pulse generator Another 555 timer will be used to generate the pulsed input signal x(t). This signal will be presented to the input of the filter with the aim that the filter will allow the fundamental harmonic to pass through while suppressing the higher harmonics. As we did not employ an anti-aliasing analog filter before the digital filter, harmonics near multiples of the sampling frequency, will pass through because of the characteristic repetitive behavior of digital systems. Fortunately the higher harmonics in a square wave, diminishes fairly rapidly. The pulse generator must generate a frequency equal to the cut off frequency of the filter which is rad/sec or Hz., which implies a period of 6.28 seconds. The circuit for the pulse generator is given in Figure P8. Again the correct operation of the pulse generator may be confirmed with a LED test probe k F 220 k 5 4 k LED x(t) Figure P8 T 6 sec Input signal to digital filter 9V battery Complete system A block diagram of the complete system is shown in Figure P9. Clock generator (Figure P6) Input signal x(t) (Figure P8) CP0 CP CP2 x(t) LED Three tap FIR filter (Figure P7) y(k) LED 9V battery Figure P9 Students must display the input signal x(t) and the output signal y(k) with LED s when demonstrating their system.

19 EIDSV4 Project Learning Guide Unit LM385 Single Supply Operational Amplifier (Practical note) Top view 3, 5 8, 7 9 V LM , Figure P0 The LM385 package contains two operational amplifiers with pin out configuration as shown in Figure P0. If it is suspected that the LM385 operational amplifier is faulty, a simple technique to check whether both amplifiers are working is to connect each one in voltage follower mode, shown in Figure P0. If the non-inverting input is connected to the positive supply (9V), the output should be high (8V) while if connected to the negative rail, the output should be zero volt. If the non-inverting input is left open, the output should be high Additional information on 555 timer Figure P, shows the 555 timer connected as an astable multivibrator. R A R B Top view V Output Output time C T L T H Figure P T L = 0.7R B C T H = 0.7(R A R B )C Total period = T = 0.7(R A 2R B )C

20 EIDSV4 Project Learning Guide Unit Pin out details for CD4022 and CD Vcc X 4 Vcc Reset Y 2 3 Enable Clock 2Y Enable Inhibit 2X 4 4X Carry out 2 Enable 5 0 4Y NC Enable 6 9 3Y GND 7 8 3X GND 8 9 NC Parts List 2 LM358 (dual operational amplifier) CD4022 (8 bit counter) CD4066 (quad switch) (timer) 2 k (¼ watt resistor) 2.7 k (¼ watt resistor) 4.7 k (¼ watt resistor) 0 k (¼ watt resistor) 4 00 k (¼ watt resistor) 220 k (¼ watt resistor) 3 0. F (non electrolytic) 0 F (64 V electrolytic capacitor) 22 F (64 V electrolytic capacitor) 2 LED (red)

21 EIDSV4 Project Learning Guide Unit Assessment Students will prepare this project and demonstrate their work in class on the scheduled date and time. A very clear photograph (or print), showing the project together with the student s student card (or other clear identification), will also be prepared as part of the demonstration and assessment. A student that demonstrates the successful filtering of the fundamental harmonic frequency from the rectangular input pulses, will meet the required outcome for this unit, and will receive at least 50% for unit 3. Please note:. A project submitted without accompanying photo s, will not be assessed, and a photograph displayed on a camera or cell phone or sent via , will not be acceptable, as a hard copy is needed for final assessment and moderation of the project. A well defined photo printed on a color printer (A4), is preferred. 2. The demonstration system must include the LED display of the input signal x(t) and the output signal y(k). 3. Students that demonstrate a system crudely constructed on a medium such as breadboard, but with the system operating perfectly, will receive 60 %. If, in addition, special attention is given to the construction (for example the circuit is assembled on veroboard), 0% will be added. If, in addition, a student displays exceptional initiative, for instance increasing the length and sampling frequency of the system, 75% or more will be awarded according to the judgment and discretion of the assessor. Construction on PC boards will not be allowed.