Design Analysis of Reference Oscillator, Regulator Circuit and Protector Circuit (Power Supply) of Marine Radar System

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1 Design Analysis of eference Oscillator, egulator Circuit and Protector Circuit (Power Supply) of Marine adar System San Hlaing Oo, and Sai Seng Lynn Abstract n any radar system, the power supply should be stable to get an accurate reading on the display screen. When the power supply system does not operate properly, the individual sections of the whole radar system will be damaged. The power supply system in the marine radar system is mainly comprised inverter circuit, regulator circuit with reference oscillator and protector circuit. n this paper, the design analyses of reference oscillator in the regulator circuit and protector circuit in the power supply for the marine radar system with test and results have been presented. Keywords Marine radar system, protector circuit, reference oscillator, regulator circuit, test and result F. NTODUCTON S 48 marine radar system is consisted of two main parts:.antenna unit and.display unit. n the antenna unit, the transmitter, the receiver and the antenna are included. Display unit consists of power supply, trigger unit and CT display. The major part of the power supply is a DC to AC inverter. The inverter circuit receives 4 DC from the main source and then is converted to (0,, 0,00,600 and 30) AC. These AC voltages are sent to the rectifier main transformer to get the various AC voltages to supply other components in the radar system. n FS 48 radar, the power supply is built with protector circuits, regulator circuit with reference oscillator, reset pulse generator, inverter and rectifier. The regulator circuit consists of Two JK flip flops: synchronous JK flip flop, U (A) and asynchronous JK flip flop, U () and three NAND gates, U (A), U () and U (C) as shown in Fig. eset pulse generator composed of Q through Q 4 and D 4 to reset asynchronous JK flip flop. 600 pps pulse train at the base ( ) of Q is applied to the synchronous flip-flop where it is converted into 800 Hz square wave. The asynchronous flip-flop provides 600 Hz square wave to two NAND gates U (A) and (). When a positive pulse comes onto the base of Q 4, Q 4 conducts and its collector drops to zero potential, and cuts off San Hlaing Oo is with the Mandalay Technological University, Mandalay, Myanmar (phone: (Electronic Engineering Department), fax: , sanhlaingoo@gmail.com). Sai Seng Lynn was with Mandalay Technological University, Mandalay, Myanmar. He is now with the Department of Electronic Engineering, Government Technical nstitute, Pyin Oo Lwin ( xylynn@gmail.com). D 4. Q 4 turns off immediately due to a narrow pulse width input to Q 4 base. Then C is charged up through 6 and internal resistance of Q 3. The rate of voltage increase is subject to Q base current, controlled by. When the voltage across C reaches 7 to 9, D 4 causes a breakdown and a sharp positive pulse appears across 7. Once D 4 breaks over, it keeps drawing the current form the supply line through 7, thus preventing charge in C. This current flows until next pulse comes to Q 4. Positive pulse at 7 is phase-inverted through the NAND U (C) which acts like an inverter and a negative reset pulse is taken out to the asynchronous flip flop. At this moment, the output point Q of the asynchronous flip flop turns high level to low level. Output at Q and Q of the synchronous flip flop and Q of the asynchronous flip flop are sent to the NAND gate (A) and (). The waveform relation is indicated in Fig. Thus the inverter output pulse width is controlled by the regulator circuit. y this way, it maintains constant in DC average value against ship's input fluctuation.. Fig. egulator Circuit with reference oscillator for FS 48 The function of the regulator circuit is given below when the ship's mains supply has increased.. oltage across C 5 rises.. Q base current increases. 396

2 3. Q 3 collector current increases. 4. Turn on timing of D 4 is advanced. 5. eset timing of U () is advanced. 6. Pulse width at Q of U () becomes narrower. Normally, potentiometer is set for +6.5 across C 5 at the rated radar input voltage. The typical waveforms of regulator circuit are as shown in Fig. At peak point, E = P and = P when UJT turns on. < P () P At the valley or dip point, E = and E = when UJT turns off, > (3) The range of is limited by the following equation. < < P (4) P During the charging period, the charging current passes through and C. So the charging time can be calculated by Fig. Typical waveforms at the significant points of regulator circuit t = C ln ( ) ( ) p (5). EFEENCE OSCLLATO AND DESGN CALCULATON This circuit consists of resistors ( ) and ( ), variable resistor ( ), capacitor (C ) and unijunction transistor (UJT) in Fig 3.The oscillation frequency is adjusted to 600 Hz by mean of the time constant of C, and. At the breakdown level of UJT (Q ), C is simultaneously discharged and positive pulse is obtained through 3. Then C is again charged to turn Q on and positive pulse train appears again at the rate of 600 Hz as adjusted by. n FS 48, the pulse length is only used at 800 Hz and 600 Hz. f the frequency is altered, the whole system is in malfunction. So the frequency should be kept at 600 Hz. This 600 Hz or pulse per second at the base ( ) of the UJT is applied to the asynchronous JK flip flop and the synchronous JK flip flop which is converted into 800 Hz in the regulator circuit. During the discharging period, only E passes through and in Fig. 4 and then the discharging time by t = - ( + ) C ln p (6) where P = in the discharging condition The period of time to complete one cycle is defined by T, T = t + t (7) The oscillation frequency is determined by F osc = T Where is (regulator reset voltage), P is the peak point voltage, is the dip point voltage, P is the peak point current and is the dip point current. (8) Fig. 3 eference Oscillator Circuit For charging condition, the current passes through and C and the value of is calculated by = E () Fig. 4 Equivalent circuit when UJT turns on There are two states to choose resistance. First, the resistance must be chosen small enough to ensure that the other device (that direct connect with resistance ) is not turned on by the voltage when E =0A as shown in Fig. 4. The voltage can be calculated by following equation, For E =0 and at charging time, 397

3 = + τ = C τ = ( + )C (9) From Fig. 3, + = 3 kω For maximum value of = 0 kω, choose = kω. When is adjusted to be 6.4 kω, + = 8.4 kω. Substitute the standard values of resistors and capacitor to verify the value of the oscillation frequency. τ = ( + )C T = (8.4 k x 0.0μ ) ln ( ) ln () F osc = Hz POTECTO CCUT AND DESGN ANALYSE Fig. 5 Charging and discharging time The applied emitter potentials ( E ) greater than = η by the forward voltage-drop of the diode, D (0.35 to 0.7) the diode will fire, and E will begin to flow through. So, the emitter firing potential is defined by p = η + D (0) Where D is diode voltage and η is intrinsic stand-off ratio. UJT model type SH0 or SH4 is chosen in this design. According to the specification of UJT, and assume η = 0.8, = 6 kω, = 4, = 6 ma and P = 3 μ A. Suppose the regulator reset DC voltage ( ) = 6.5 and D = 0.7. To design the value of from (4) P must be known. From (0), P = 3.9 and from (4), 083 < < 867 k Choose = 3 kω to be within the above limit. To design the value of, consider two states: UJT on and off. At UJT off condition, = 0.6 and from (9), = 96 Ω Choose = 00 Ω for the standard value. To design the value of C, firstly calculate by the following equation for UJT on condition in Fig. 4. At UJT on condition, = 3.5. (P 0.7) = + 00(P 0.7) 3.5 = 00 + = 77 Ω Choose = 330 Ω. The oscillation frequency is adjusted to 600 Hz by mean of the time constant of C, and. F osc = = = 600 () T t + t Substitution (5) and (6) into (), C = μ F. For the standard value, C = 0.0 μ F. The protection circuit is comprised of the transistors Q 9, Q 0, Q and their associated components. The transistors in this protection circuit are used as the switching mode. The transistors Q 0 and Q forms the Schmitt trigger circuit. The Schmitt trigger circuit is an emitter couple binary trigger circuit. t is termed a binary trigger circuit since two stable states occur: the transistor Q may be ON and Q 0 OFF or Q may be OFF and Q 0 ON.The protection circuit functions at the following conditions:. When the supply voltage exceeds 0% above the rated voltage (8.8 for 4 ). When the regulator reset voltage of 6.5 exceeds 7.5 across C5 3. When the radar is supply with input in wrong polarity 4. When there is an over current in the radar system Fig. 6 Protector Circuit The base bias of Q is set by 3 so that Q 0 is cut off and Q is conductive. The base current of Q is constant given by the regulated output of D 0 (zener diode) through, 3, 3, T and 4. t is set at a critical point of turn-on region of Q. ncrease of voltage across C 5 causes potential rise at Q collector, and current flows in Q 0 base. Since the emitter potential of Q increases, reducing the base current of Q. As a result, Q 0 and Q change the states reversely. When Q is cut off and Q 0 conducts, Q 9 becomes off. The power supply circuit is disabled and the radar set is protected against abnormal voltage rise in the radar system. Negative half-cycle of 800 Hz AC inverter output in T is rectified through D and applied to the and 3. f the supply exceeds 0% above the rated voltage at the junction of 398

4 and 3, it is applied through D 6, T, 4 and 3 to the base of Q. The reduction of base potential of Q turns Q off and Q 0 on. n Fig. 6, Q 0 and Q are the same models. For the normal condition, set = 3.3 to be at the critical turn on region by the following equivalent circuit in Fig. 7. Fig. 7 Equivalent circuit when Q on Fig. 8 Equivalent circuit when Q 0 on From Fig. 7, i = (3) + Substituting = in (3), the value of can be calculated by = (4) i To determine the value of E, E must be known and gained by from Fig. 7, E = - Esat (5) E =.6 and suppose Cmax = 5 ma and β = 5. Then, Cmax = β max and max = 0.6 ma. Assume Emax = Cmax. E E = = 73 Ω Emax Choose E = 80 Ω for the standard value. Consider Q off condition. When the supply voltage becomes 9.8 to ensure Q off, E must be greater than 3.3. Therefore, set E =3.5. From (5), = E + Esat = = 4. When the supply voltage is 9.8, Q turns off and Q 0 turns on. So, consider the equivalent circuit of Q 0 on in Fig. 8. f there is no in the circuit, the value of will be the maximum value. From (3), i becomes 9.8, = 4. and neglect. Therefore, max is 6 kω. f there is in the equivalent circuit, must be less than 6 kω.choose = 4.3 kω. From (4), =.38 kω. Choose =.4 kω for the standard value. From Fig. 8, the value of C can be obtained by C = CC CEdst E (6) Cmax C =.07 kω, where CC = 9.8, CEsat = 0. (by theoretical), E = 3.5 and Cmax = 5 ma. Choose C =. kω for the standard value. From the calculation, =.4 kω = 4.3 kω C =. kω E = 80Ω Use these values of resistors to check for the design limitation. From Fig. 8, = + = 7.09 CC (7) From (5), E = = This voltage of E is greater than the minimum setting voltage = 3.5 for Q off and Q 0 on. From Fig. 8, C = CC CE E = = ma C.k t shows that C < Cmax. Consider Q on condition. For normal condition, the supply voltage is between 6.5 and 7.8, set =3.3. At the Q on condition, consider the equivalent circuit in Fig. 7. f there is no in this circuit, the value of will be the maximum value. From (3), max =.83 kω Where i = 5, = 3.3, and neglect. f there is in the equivalent circuit, must be less than.83 kω. Choose = 480Ω. From (4), =. kω where = 0.6 ma (Q and Q 0 are equal types.) Choose = kω for the standard value. From Fig. 7, C + 4 = 4.3 kω. f 4 = 3. kω, C =. kω. Choose C =. kω. 399

From the calculation, = kω = 480Ω C =. kω E = 80Ω Use these values of resistors to check for the design limitation. From Fig. 7, = (8) i + = 4.

Waveform at the output Q of JK flip flop, U (A) (pointed by C in the regulator circuit). TESTS AND ESULT The waveforms at the significant points A,, C, D, E, F, G and H from Fig.

These waveforms can be compared with the typical waveforms in Fig.. Fig. 3 Waveform at the output Q of JK flip flop, U () (pointed by F in the regulator circuit) Fig.

5 From the calculation, = kω = 480Ω C =. kω E = 80Ω Use these values of resistors to check for the design limitation. From Fig. 7, = (8) i + = 4.03 This voltage of is greater than the minimum setting voltage to turn Q on and Q 0 off. Fig. Waveform at the output Q of JK flip flop, U (A) (pointed by C in the regulator circuit). TESTS AND ESULT The waveforms at the significant points A,, C, D, E, F, G and H from Fig. are shown in the following figures. These figures are waveforms from the constructed circuits and are given on the oscilloscope. These waveforms can be compared with the typical waveforms in Fig.. Fig. 3 Waveform at the output Q of JK flip flop, U () (pointed by F in the regulator circuit) Fig. 9 Waveform at the emitter of UJT Fig. 4 Waveform at the output of D 4 (pointed by D in the regulator circuit) Fig. 0 Waveform at the base of UJT (pointed by A in the regulator circuit) Fig. Waveform at the output Q of JK flip flop, U (A) (pointed by in the regulator circuit) Fig. 5 Waveform at the output of U (C) (pointed by E in the regulator circuit) 400

University. would like to thank to Sai Seng Lynn for his advice and support. Specially, would like to thank Ms. Khin Trar Trar Soe for her encouragement.

6 University. would like to thank to Sai Seng Lynn for his advice and support. Specially, would like to thank Ms. Khin Trar Trar Soe for her encouragement. would like to acknowledge many friends at MTU and Ela who have contributed to the development of this paper. would like to express my gratitude to my parents, my brother and my sisters. Fig. 6 Waveform at the output of U (A) (pointed by G in the regulator circuit) EFEENCES [] Thomas L. Floyd, Electronic Devices, 4th ed, 000. [] Clifford D. Ferris, Element of Electronic Design. [3] obert olestad Louios Naselsky, Electronic Devices and Circuit Theory, 5th ed, 999. [4] FS-48 Marine adar System, Annon, 983. Fig. 7 Waveform at the output of U () (pointed by H in the regulator circuit) San Hlaing Oo was born in War Yon Gan, Shwebo Township, Sagaing Division, Myanmar. His date of birth is 3 rd December, 98. Graduated in August, 004 with.e (Electronics) from Mandalay Technological University (MTU) and finished Master degree on March, 006 with M.E (Electronics) from Yangon Technological University (YTU). Now, he is a PhD Candidate of Electronic Engineering Department, Mandalay Technological University (MTU), Myanmar. He served as a Demonstrator at Mandalay GTC from January, 00 to January, 004 when he was attending the Special Engineering Course in MTU. From 4, November, 004 to 3, March, 008, he promoted as an Assistant Lecturer of MTU and from, April, 008 to now, he promoted as a Lecturer, Department of Technical and ocational Education, Myanmar. For his Master Thesis, he wrote the results of his research Design and Construction of Wireless Transmitter. Now, he is making his PhD research at Mandalay Technological University (MTU), Myanmar. Mr. San Hlaing Oo made his first publication of nternational Paper at this paper Design Analysis of eference Oscillator, egulator Circuit and Protector Circuit (Power Supply) of Marine adar System. Fig. 8 Constructed Power Supply Circuit of Marine adar System. CONCLUSON The power supply circuit is the main device in the radar system because if there is an invalid supply such as over current, overloaded and wrong polarity, the whole radar system will be damaged. These invalid supplies can be protected and regulated by the protector and regulator, which is composed in power supply circuit. This paper intends to modify from the basic power supply circuit to the advanced power supply circuit. n the future design the circuits can be constructed with C base. ACKNOWLEDGMENT would like to express the deepest gratitude to Dr. Maung Maung Latt and Dr. Yin Mon Myint, Mandalay Technological 40

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