Lecture 6-1. Data Path Circuits

Transcription

1 Lecture 6 Data Path Circuit Kontantino Maelo Department of Electrical & Electronic Engineering Imperial College London URL: k.maelo@ic.ac.uk Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6 -

2 aed on lide/material by J. Rabaey Digital Integrated Circuit: A Deign Perpective, Prentice Hall D. Harri Wete and Harri, CMOS VLSI Deign: A Circuit and Sytem Perpective, Addion Weley Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-2

3 Recommended Reading J. Rabaey et. al. Digital Integrated Circuit: A Deign Perpective : Chapter Wete and Harri, CMOS VLSI Deign: A Circuit and Sytem Perpective : Chapter 0 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-3

4 A Generic Digital Proceor MEMORY INPUT-OUTPUT CONTROL DATAPATH Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-4

5 it liced deign Control it 3 Data-In Regiter Adder Shifter Multiplexer it 2 it it 0 Data-Out Tile identical proceing element Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-5

6 Outline Adder Multiplier Shifter Comparator Layout iue Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-6

7 Full Adder A Cin Full adder Sum Cout Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-7

8 The inary Adder A Cin Full adder Sum Cout S = A C i = AC i + AC i + AC i + AC i C o = A + C i + AC i Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-8

9 Expre Sum and Carry a a function of P, G, D/K Define 3 new variable which ONLY depend on A, Generate (G) = A Propagate (P) = A Delete/Kill = A Can alo derive expreion for S and C o baed on D and P Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-9

10 Full Adder Deign I rute force implementation from eqn S = A C Cout = MAJ( AC,, ) A A C C A A A C A C MAJ S C out C C C S C A C C A A C out A A A Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-0

11 Full Adder Deign II Factor S in term of C out S = AC + (A + + C)(~C out ) Critical path i uually C to C out in ripple adder MINORITY A C C out S S C out Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6 -

12 Full Adder Deign III Complementary Pa Tranitor Logic (CPL) Slightly fater, but more area C A C C S C C out A C C A C S C C out A Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-2

13 Full Adder Deign IV Dual-rail domino Very fat, but large and power hungry Ued in very fat multiplier C_h φ A_h C out _h C_l φ A_l C out _l A_h _h _h A_l _l _l S_l φ S_h C_h C_l C_h _h _l _h A_h A_l Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-3

14 Complementary Static CMOS Full Adder V DD A V DD C i A A C i A C i A X C i V DD S A V DD A C i C i A C o Data Path Circuit 28 Tranitor Introduction to Digital Integrated Circuit Deign Lecture 6-4

15 Inverion Critical path pae through majority gate uilt from minority + inverter Eliminate inverter and ue inverting full adder A 4 4 A 3 3 A 2 2 A C out C in C 3 C 2 C S 4 S 3 S 2 S Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-5

16 Inverion Property A A C i FA C o C i FA C o S S Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-6

17 Minimize Critical Path by Reducing Inverting Stage Even Cell Odd Cell A 0 0 A A 2 2 A 3 3 C i,0 C o,0 C o, C o,2 C o,3 FA FA FA FA S 0 S S 2 S 3 Exploit Inverion Property Note: need 2 different type of cell Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-7

18 The better tructure: the Mirror Adder Generate (G) = A Propagate (P) = A V DD Delete = A V DD V DD A "0"-Propagate A C i A Kill C o A C i C i S ""-Propagate A Generate C i A A C i A Data Path Circuit 24 tranitor Introduction to Digital Integrated Circuit Deign Lecture 6-8

19 Carry Propagate Adder N-bit adder called CPA Each um bit depend on all previou carrie How do we compute all thee carrie quickly? A N... N... C out C + in S N... C out C in C out C in carrie A S 4... Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-9

20 Carry-Ripple Adder Simplet deign: cacade full adder Critical path goe from Cin to Cout Deign full adder to have fat carry delay A 4 4 A 3 3 A 2 2 A C out C in C 3 C 2 C S 4 S 3 S 2 S Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-20

21 The Ripple-Carry Adder A 0 0 A A 2 2 A 3 3 C i,0 C o,0 C o, C o,2 FA FA FA FA (= C i, ) C o,3 S 0 S S 2 S 3 Wort cae delay linear with the number of bit t d = O(N) t adder ( N )t carry + t um Goal: Make the fatet poible carry path circuit Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-2

22 Carry-Ripple Adder Generate / Propagate A 4 4 A 3 3 A 2 2 A C in G 4 P 4 G 3 P 3 G 2 P 2 G P G 0 P 0 G 3:0 G 2:0 G :0 G 0:0 C 3 C 2 C C 0 C 4 C out S 4 S 3 S 2 S Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-22

23 Mancheter Carry Chain V DD φ P 0 P P 2 P 3 P 4 C i,0 G 0 G G 2 G 3 G 4 φ Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-23

24 Sizing Mancheter Carry Chain Dicharge Tranitor R R 2 R R 4 R 5 R 6 Out M C C M 0 M M 2 M 3 M 4 C 2 C 3 C 4 C 5 C 6 25 t p = N i 0.69 C i R j i = j = Speed 5 0 Area k Speed (normalized by 0.69RC) k Area (in minimum ize device) Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-24

25 Mancheter-Carry Implementation P 0 C i,0 P G 0 G P 2 G 2 P 3 G 3 P C o,3 P Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-25

26 Carry-Skip Adder Carry-ripple i low through all N tage Carry-kip allow carry to kip over group of n bit Deciion baed on n-bit propagate ignal A 6:3 6:3 A 2:9 2:9 A 8:5 8:5 A 4: 4: P 6:3 P 2:9 P 8:5 P 4: C C 2 C 8 C 4 out C in S 6:3 S 2:9 S 8:5 S 4: Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-26

27 Carry-ypa Adder P 0 G P 0 G P 2 G 2 P 3 G 3 C i,0 C o,0 C o, C o,2 FA FA FA FA C o,3 P 0 G P 0 G P 2 G 2 P 3 G 3 P=P o P P 2 P 3 C i,0 C o,0 C o, C o,2 FA FA FA FA Multiplexer C o,3 Idea: If (P0 and P and P2 and P3 = ) then C o3 = C 0, ele kill or generate. Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-27

28 Carry-ypa Adder (cont.) it 0-3 it 4-7 it 8- it 2-5 Setup Setup Setup Setup Carry Carry Carry Carry C i,0 Propagation Propagation Propagation Propagation Sum Sum Sum Sum Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-28

29 Carry Ripple veru Carry ypa t p ripple adder bypa adder 4..8 N Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-29

30 Carry-Select Adder Trick for critical path dependent on late input X Precompute two poible output for X = 0, Select proper output when X arrive Carry-elect adder precompute n-bit um For both poible carrie into n-bit group A 6:3 6:3 A 2:9 2:9 A 8:5 8:5 A 4: 4: C out + C 2 + C 8 + C 4 + C in S 6:3 S 2:9 S 8:5 S 4: Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-30

31 Carry-Select Adder Setup P,G "0" "0" Carry Propagation "" "" Carry Propagation C o,k- Multiplexer Co,k+3 Sum Generation Carry Vector Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-3

32 Carry Select Adder: Critical Path it 0-3 it 4-7 it 8- it 2-5 Setup Setup Setup Setup "0" "0" Carry "0" "0" Carry "0" "0" Carry "0" "0" Carry "" "" Carry "" "" Carry "" "" Carry "" "" Carry Multiplexer Multiplexer Multiplexer Multiplexer C i,0 C o,3 C o,7 C o, C o,5 Sum Generation Sum Generation Sum Generation Sum Generation S 0-3 S 4-7 S 8- S 2-5 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-32

33 Linear Carry Select it 0-3 it 4-7 it 8- it 2-5 Setup Setup Setup Setup () "0" () "0" Carry "0" "0" Carry "0" "0" Carry "0" "0" Carry "" (5) "" Carry (5) Multiplexer "" "" Carry (5) "" "" Carry (5) "" "" Carry (5) (6) (7) (8) M ultip lexer Multiplexer M ultip lexer C i,0 (9) Sum Generation Sum Generation Sum Generation Sum Generation S 0-3 S 4-7 S 8- S 2-5 (0) Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-33

34 Square Root Carry Select it 0- it 2-4 it 5-8 it 9-3 it 4-9 Setup Setup Setup Setup () "0" Carry "0" () "0" "0" Carry "0" "0" Carry "0" "0" Carry C i, 0 "" Carry "" Carry "" Carry "" Carry "" "" "" "" (3) (3) (4) (5) (6) (4) (5) (6) (7) M ultiplexer M ultiplexer M ultiplexer Multiplexer (7) Mux (8) Sum Generation Sum Generation Sum Generation Sum Generation Sum S 0- S 2-4 S 5-8 S 9-3 S 4-9 (9) Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-34

35 Adder Delay - Comparion ripple adder 30.0 tp linear elect quare root elect N Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-35

36 Carry-Lookahead Adder Carry-lookahead adder compute G for many bit in parallel. A 6:3 6:3 A 2:9 2:9 A 8:5 8:5 A 4: 4: C out G 6:3 P 6:3 C 2 G 2:9 P 2:9 C 8 G 8:5 P 8:5 C 4 G 4: P 4: C in S 6:3 S 2:9 S 8:5 S 4: i:k k-:l l-:m m-:j i:j G i:k P i:k G k-:l P k-:l G l-:m P l-:m G m-:j P m-:j G i:j P i:j Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-36

37 LookAhead - aic Idea A 0, 0 A, A N-, N-... C i,0 P 0 C i, P C i,n - P N-... Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-37

38 Look-Ahead: Topology V DD G 3 G 2 G G 0 C i,0 Co,3 P 0 P P 2 P 3 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-38

39 Tree Adder If lookahead i good, lookahead acro lookahead! Recurive lookahead give O(log N) delay Many variation on tree adder Ideal N-bit tree adder would have L = log N logic level Fanout never exceeding 2 No more than one wiring track between level Decribe adder with 3-D taxonomy (l, f, t) Logic level: L + l Fanout: 2 f + Wiring track: 2 t Known tree adder it on plane defined by l + f + t = L- Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-39

40 Logarithmic Look-Ahead Adder A 0 F A A 2 A 3 A 4 A 5 A 6 A 7 A 0 A t p N A 2 A 3 A 4 A 5 A 6 A 7 F t p log 2 (N) Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-40

41 rent-kung Adder (G 0,P 0 ) (G,P ) C o,0 Co, C o,2 C o,4 (G 2,P 2 ) C o,3 C o,5 (G 3,P 3 ) (G 4,P 4 ) (G 5,P 5 ) C o,6 (G 6,P 6 ) C o,7 (G 7,P 7 ) t add log 2 (N) Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-4

42 Tree Adder Taxonomy (f) Ladner-Ficher (b) Sklanky :4 3:2 :0 9:8 7:6 5:4 3:2 :0 5:4 3:2 :0 9:8 7:6 5:4 3:2 :0 5:2 4:2 :8 0:8 7:4 6:4 3:0 2:0 l (Logic Level) 5:2 :8 7:4 3:0 5:8 4:8 3:8 2:8 5:04:03:02:0:00:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 f (Fanout) Sklanky Ladner- Ficher Ladner- Ficher 2 (6) rent- Kung 3 (7) 5:8 (a) rent-kung 3:8 5:8 3:0 :0 9:0 7:0 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 5:0 (e) Knowle [2,,,] (9) 2 (5) (3) 0 (2) 0 (4) 0 () (5) Han- Carlon 5 5:4 5:2 5:8 4 3:2 3 2 :0 :8 0 9: :6 7:4 7:0 6 5: :2 3:0 2 :0 0 5:4 4:3 3:2 2: :0 0:9 5:2 4: 3:0 2:9 :8 0:7 9:8 9:6 8:7 8:5 7:6 7:4 6:5 6:3 5:4 5:2 4:3 4: 3:2 3:0 2: 2:0 :0 Knowle [4,2,,] New (,,) :0 5:8 4:7 3:6 2:5 :4 0:3 9:2 8: 7:0 6:0 5:0 4:0 (2) 3:0 9:0 5:0 5:04:03:02:0:00:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 Knowle [2,,,] 2 (4) Han- Carlon (d) Han-Carlon 5:04:03:02:0:00:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 (c) Kogge-Stone :4 4:3 3:2 2: :0 0:9 9:8 8:7 7:6 6:5 5:4 4:3 3:2 2: :0 0 Kogge- Stone 3 (8) 5:4 5:2 3:2 3:0 :0 :8 9:8 9:6 7:6 7:4 5:4 5:2 3:2 3:0 :0 5:2 4: 3:0 2:9 :8 0:7 9:6 8:5 7:4 6:3 5:2 4: 3:0 2:0 5:8 3:6 :4 9:2 7:0 5:0 5:8 4:7 3:6 2:5 :4 0:3 9:2 8: 7:0 6:0 5:0 4:0 t (Wire Track) 5:04:03:0 2:0:00:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 5:04:03:02:0:00:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-42

43 Multi Input Adder Suppoe we want to add k N-bit word Ex: = 0 Straightforward olution: k- N-input CPA Large and low Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-43

44 Carry Save Addition A full adder um 3 input and produce 2 output Carry output ha twice weight of um output N full adder in parallel are called carry ave adder Produce N um and N carry out X 4 Y 4 Z 4 X 3 Y 3 Z 3 X 2 Y 2 Z 2 X Y Z C 4 S 4 C 3 S 3 C 2 S 2 C S X N... Y N... Z N... n-bit CSA C N... S N... Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-44

45 CSA Application Ue k-2 tage of CSA Keep reult in carry-ave redundant form Final CPA compute actual reult _ 4-bit CSA 0 5-bit CSA 000_ _ 00_ _ 000_ X Y Z S C X Y Z S C A S Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-45

46 Outline Adder Multiplier Shifter Comparator Layout iue Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-46

47 Multiplication Example: 00 : : : 60 0 multiplicand multiplier partial product product M x N-bit multiplication Produce N M-bit partial product Sum thee to produce M+N-bit product Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-47

48 General Form Multiplicand: Y = (y M-, y M-2,, y, y 0 ) Multiplier: X = (x N-, x N-2,, x, x 0 ) Product: P = y x = x y M N N M j 2 i i j j i2 + i j2 j= 0 i= 0 i= 0 j= 0 y 5 y 4 y 3 y 2 y y 0 x 5 x 4 x 3 x 2 x x 0 multiplicand multiplier x 0 y 5 x 0 y 4 x 0 y 3 x 0 y 2 x 0 y x 0 y 0 p x y 5 x y 4 x y 3 x y 2 x y x y 0 x 2 y 5 x 2 y 4 x 2 y 3 x 2 y 2 x 2 y x 2 y 0 x 3 y 5 x 3 y 4 x 3 y 3 x 3 y 2 x 3 y x 3 y 0 x 4 y 5 x 4 y 4 x 4 y 3 x 4 y 2 x 4 y x 4 y 0 x 5 y 5 x 5 y 4 x 5 y 3 x 5 y 2 x 5 y x 5 y 0 p0 p 0 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p partial product product Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-48

49 Dot Diagram Each dot repreent a bit x 0 partial product multiplier x x 5 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-49

50 Array Multiplier y 3 y 2 y y 0 x 0 x CSA Array x 2 x 3 CPA p 7 p 6 p 5 p 4 p 3 p 2 p p 0 Sin A Cin A critical path A A Cout Sout = Cout Sin Cin Sout Cout Sout Cin = Cout Sout Cin Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-50

51 Array Multiplier X 3 Y X 2 X X 0 Z 0 HA FA FA HA X 3 Y 2 X 2 X X 0 Z FA FA FA HA X 3 Y 3 X 2 X X 0 Z 2 FA FA FA HA Z 7 Z 6 Z 5 Z 4 Z 3 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-5

52 Rectangular Array Squah array to fit rectangular floorplan y 3 y 2 y y 0 x 0 x p 0 x 2 p x 3 p 2 p 3 p 7 p 6 p 5 p 4 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-52

53 The MxN Array Multiplier Critical Path HA FA FA HA FA FA FA HA Critical Path Critical Path 2 Critical Path & 2 FA FA FA HA Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-53

54 Carry-Save Multiplier HA HA HA HA HA FA FA FA HA FA FA FA HA FA FA HA Vector Merging Adder Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-54

55 Multiplier Floorplan X 3 X 2 X X 0 Y 0 Y C S C S C S C S Z 0 HA Multiplier Cell FA Multiplier Cell Y 2 C S C S C S C S Z Vector Merging Cell Y 3 C S C S C S C S Z 2 X and Y ignal are broadcated through the complete array. ( ) C S C S C S C S Z 7 Z 6 Z 5 Z 4 Z 3 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-55

56 Wallace-Tree Multiplier y 0 y y 2 FA C i- y 0 y y 2 y 3 y 4 y 5 y 3 FA FA C i FA C i- C i C i C i- C i- y 4 FA C i FA C i- C i C i- y 5 C i FA FA C S C S Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-56

57 Fewer Partial Product Partial product reult from the logical AND of multiplicand Y with a multiplier bit X i. Each row in the partial product array i either a copy of the multiplicand or a row of zero (depending on the multiplier bit) In mot cae the partial product array ha many zero row that have no impact on the reult and thu repreent a wate of effort when added Careful optimization of the partial product generation can lead to ome ubtantial delay and area reduction In the cae of a multiplier coniting of all all the partial product exit, while in the cae of all 0 there i none Thi allow u to reduce the number of generated partial product by half 00 a multiplier produce 6 non-zero partial product row The number of non zero row can be reduced by recoding the multiplier in the form 00000(-)0 ooth recoding Only two partial product need to be added but the final adder ha to perform ubtraction a well Reduced number of partial product: peedup + area reduction Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-57

58 ooth Encoding Modified ooth recoding i mot often ued to avoid variable ize partial product array Multiplier i partitioned into three bit group that overlap by one bit (the mb of the previou group if we move from lb to mb) Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-58

59 ooth Hardware ooth encoder generate control line for each PP ooth elector chooe PP bit y j y j- X i x 2i- x 2i 2X i M i ooth Encoder x 2i+ ooth Selector PP ij Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-59

60 Sign Extenion Partial product can be negative Require ign extenion, which i cumberome High fanout on mot ignificant bit PP 0 PP PP 2 PP 3 PP 4 0 x - x 0 multiplier x PP 5 PP 6 PP 7 PP x 5 x 6 x 7 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-60

61 Lecture 6-6 Introduction to Digital Integrated Circuit Deign Data Path Circuit Simplified Sign Extenion Sign bit are either all 0 or all Note that all 0 i all + in proper column Ue thi to reduce loading on MS PP 0 PP PP 2 PP 3 PP 4 PP 5 PP 6 PP 7 PP 8

62 Simplified Sign Extenion II No need to add all the in hardware Precompute the anwer! PP 0 PP PP 2 PP 3 PP 4 PP 5 PP 6 PP 7 PP 8 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-62

63 Advanced Multiplication Signed v. unigned input Higher radix ooth encoding Array v. tree CSA network Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-63

64 Multiplier Summary Optimization Goal Different V inary Adder Once Again: Identify Critical Path Other poible technique - Logarithmic veru Linear (Wallace Tree Mult) - Data encoding (ooth) - Pipelining FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-64

65 Outline Adder Multiplier Shifter Comparator Layout iue Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-65

66 Shifter Logical Shift: Shift number left or right and fill with 0 0 LSR = 00 0 LSL = 00 Arithmetic Shift: Shift number left or right. Rt hift ign extend 0 ASR = 0 0 ASL = 00 Rotate: Shift number left or right and fill with lot bit 0 ROR = 0 0 ROL = 0 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-66

67 The inary Shifter Right nop Left A i i A i- i- it-slice i... Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-67

68 The arrel Shifter A 3 3 Sh A 2 2 A Sh2 : Data Wire : Control Wire A 0 Sh3 0 Sh0 Sh Sh2 Sh3 Area Dominated by Wiring Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-68

69 Logarithmic Shifter Sh Sh Sh2 Sh2 Sh4 Sh4 A 3 3 A 2 2 A A 0 0 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-69

70 Funnel Shifter A funnel hifter can do all ix type of hift Select N-bit field Y from 2N-bit input Shift by k bit (0 k < N) 2N- N- 0 C offet + N- offet Y Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-70

71 Funnel Shifter Operation Computing N-k require an adder Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-7

72 Simplified Funnel Shifter Optimize down to 2N- bit input Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-72

73 Funnel Shifter Deign N N-input multiplexer Ue -of-n hot elect ignal for hift amount nmos pa tranitor deign (V t drop!) k[:0] left Inverter & Decoder Y 3 Y 2 Z 6 Y Z 5 Y 0 Z 4 Z 3 Z 2 Z Z 0 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-73

74 Funnel Shifter Deign 2 Log N tage of 2-input muxe k k 0 No elect decoding needed left Z 0 Y 0 Z Y Z 2 Y 2 Z 3 Y 3 Z 4 Z 5 Z 6 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-74

75 Outline Adder Multiplier Shifter Comparator Layout iue Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-75

76 Comparator 0 detector: A = detector: A = Equality comparator: A = Magnitude comparator: A < Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-76

77 & 0 Detector detector: N-input AND gate 0 detector: NOT + detector (N-input NOR) A 7 A 6 A 5 A 4 A 3 A 2 allone A 3 A 2 A A 0 allzero A A 0 A 7 A 6 A 5 A 4 A 3 A 2 allone A A 0 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-77

78 Equality Comparator Check if each bit i equal (XNOR, aka equality gate) detect on bitwie equality [3] A[3] [2] A[2] [] A[] A = [0] A[0] Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-78

79 Magnitude Comparator Compute -A and look at ign -A = + ~A + For unigned number, carry out i ign bit 3 A C N A A 3 2 A 2 Z A = A 0 A 0 Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-79

80 Signed v. Unigned For igned number, comparion i harder C: carry out Z: zero (all bit of A- are 0) N: negative (MS of reult) V: overflow (input had different ign, output ign ) Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-80

81 Outline Adder Multiplier Shifter Comparator Layout iue Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-8

82 Layout Strategie for it-sliced Datapath Control Wire (M) Wire (M) Signal Wire (M2) GND Well V DD Signal Wire (M2) Well GND GND V DD GND Approach I Approach II Signal and power line parallel Signal and power line perpendicular Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-82

83 Layout of it-liced Datapath Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-83

84 Layout of it-liced Datapath (a) Datapath without feedthrough and without pitch matching (area = 4.2 mm 2 ). (b) Adding feedthrough (area = 3.2 mm 2 ) (c) Equalizing the cell height reduce the area to 2.2 mm 2. Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-84

85 Deign a a Trade-Off t p (nec) tatic mirror mancheter bypa elect look-ahead 0.2 Area (mm 2 )0.4 look-ahead elect tatic bypa mirror mancheter N N Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-85

86 Important Deign Concept The mot important rule i to elect the right tructure before tarting an elaborate circuit optimization. Going for the optimal performance of a complex tructure by rigorouly optimizing tranitor ize and topologie probably will not give the bet reult. Optimization at the higher level of abtraction (logic or architectural level) can often generate more dramatic reult. Simple firt order calculation can help give a global picture of the pro and con of a propoed tructure Determine the critical timing path through the circuit and focu mot of your optimization effort on that part of the circuit. Hand analyi + CAD tool for critical path analyi and tranitor izing Non critical part can be downized to reduce power Circuit ize i not only determined by the number and ize of tranitor but alo by other factor uch a wiring and number of via and contact. An obcure optimization can ometime help to get a better reult however it may alo lead to irregular and convoluted topology. Regularity and modularity are very important propertie Power and peed can be traded off through a choice of circuit izing, upply voltage and tranitor threhold. Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-86

87 Summary A data path i bet implemented in a bit-liced fahion. A ingle layout i ued repetitively for every bit in the data word. Thi regular approach eae the deign effort and reult in fat and dene layout. A ripple carry adder ha a performance that i linearly proportional to the number of bit. Circuit optimization concentrate on reducing the delay of the carry path. A number of circuit topologie exit proving that careful optimization of the circuit topology and the tranitor ize help to reduce the capacitance on the carry bit Other adder tructure ue logic optimization to increae the performance (carry-bypa, carry elect, carry lookahead) Performance increae come at the cot of area A multiplier i nothing more than a collection of cacaded adder. Critical path i far more complex and optimization are different compared to adder. Carry ave technique: logic manipulation to turn the adder array into a regular tructure with well defined critical timing path eay to optimize ooth recoding and partial product accumulation in a tree reduce the complexity and delay of large multiplier The performance and the area of a programmable hifter are dominated by the wiring. The exploitation of regularity can help to minimize the impact of the interconnect wire. Data Path Circuit Introduction to Digital Integrated Circuit Deign Lecture 6-87