In/Parallel-Out Constant Current Driver

Transcription

1 StarChips Technology V01_02; Jul/12 8-bit Serial-In/Parallel Product escription The serialinterfaced LE driver sinks 8 LE clusters with constant current to keep the uniform intensity of LE displays. In applications, an external resistor is used to set the fullscale constant output current from 5mA up to 45mA. The guarantees each output can endure maximum 17V C voltage stress. The builtin shift registers and data latches making the effective solution in driving LE display. The output enable function gates all 8 outputs on and off, and is fast enough to be used as PWM input for LE intensity control. Since the serial data input rate can be reached up to 25MHz, the will satisfy system which needs high volume data transmission to control the LE Features 8 constant current sinkers with output voltage sustainable to 17V Constant output current : 5 30/45mA@3.3/5V Excellent regulation to load, supply voltage and temperature Temperature regulation: ±0.005%/ C load regulation: ±0.1%/V line regulation: ±0.5%/V High current matching accuracy: ±1% between outputs, ±2% between ICs Fine grayscale response with 180ns PWM pulse width ropout voltage 0.5V@20mA, V =5V CMS Schmitt trigger inputs with clock rate up to cascade connection The constant current value of 8 outputs is set by a single external resistor Interlaced 30ns delay of output, preventing instant current surge and output bouncing overstress Builtin power on reset(pr) circuit forces all the outputs off while power on Package: SSP16 and SP16 Applications: LE isplays, Variable Message Signs, Illumination, LE Traffic Signs

2 Pin Configurations GN 1 SI 2 3 LA/ 4 UT0 5 UT1 6 UT2 7 UT3 8 CSSG CSG 16 V 15 REXT 14 S 13 E/ 12 UT7 11 UT6 10 UT5 9 UT4 Terminal escription Pin Name Pin No. I/ GN 1 Ground terminal Function SI 2 I Serial input terminal of data shift register 3 I LA/ 4 I Clock input terminal of shift register, data is sampled at the rising edge of. ata is latched when LA/ is low. ata on shift register goes through when LA/ is high. UT[0:7] 512 pendrain, constantcurrent outputs. E/ 13 I Input terminal of output enable signal. utput is enabled when E/ is low. S 14 utput terminal of serialdata output to the SI of next. REXT 15 I/ Synchronous signal, daisy chain output terminal. V 16 Supply voltage terminal Block iagram UT0 UT1 UT2 UT6 UT7 REXT Current Regulator utput Sink river PR E/ ST ST ST ST ST LA/ SI S C C C C C Page 2 of 16

3 Truth Table LA/ E/ SI UT0 ~ UT7 S H L n n n1 n6 n7 n7 L L n+1 No change n6 H L n+2 n+2 n+1 n4 n5 n5 X L n+3 n+2 n+1 n4 n5 n5 X H n+3 ff n5 Timing iagram (MSB)=0 6=1 5=1 43=0 2=1 1=0 0(LSB)=1 SI LA/ E/ UT0 (LSB) UT1 UT2 UT30 UT4 UT5 UT6 UT7 (MSB) FF N FF N FF N FF N FF N FF N FF N S Previous data 7(MSB)=0 Page 3 of 16

4 Equivalent Circuits of Inputs (1) Equivalent Circuits of Input (2) V V V V V E/ LA/ GN GN GN GN GN Equivalent Circuits of Inputs (3) Equivalent Circuits of utput V V V V SI S GN GN GN GN Selector Guide Part Number of utputs Max utput Current (ma) Min PWM Pulse Width (ns) Supply Voltage (V) Error etection SCT NA SCT /5 NA SCT /5 Yes /5 NA SCT NA SCT /5 NA SCT /5 Yes SCT /5 NA rdering Information Part Marking Package Unit per reel(pcs) CSSG CSSG Green SSP CSG CSG Green SP StarChips Technology, Inc. 4F, No.5, Technology Rd., ScienceBased Industrial Park, HsinChu, Taiwan, R..C. Tel : Ext.555, Fax: , service@starchips.com.tw Page 4 of 16

5 Maximum Ratings (T A = 25 C) Characteristic Symbol Rating Unit Supply voltage V 7.0 V Input voltage V IN 0.2 ~ V +0.2 V utput current I UT 60 ma/channel utput voltage utputs 0.2 ~ V +0.2 V UT0~UT7 V UT 0.2 ~ 17 V Total GN terminals current I GN 480 ma Power dissipation Thermal resistance SSP SP16 P 1.47 SSP SP16 R TH(ja) perating junction temperature T J(max) 150 C perating temperature T PR 40~+85 C Storage temperature T STG 55~+150 C 85 W C /W The absolute maximum ratings are a set of ratings not to be exceeded. Stresses beyond those listed under Maximum Ratings may cause the device breakdown, deterioration even permanent damage. Exposure to the maximum rating conditions for extended periods may affect device reliability. Recommended perating Conditions (T A = 40 to 85 C unless otherwise noted) Characteristic Symbol Conditions Min. Typ. Max. Unit Supply voltage V V utput voltage V UT utput FF 17 V utput N V utput current I UT V =3.3/5V, V UT =1V 5 30/45 ma Input voltage V IH 0.7V V V input signals 0 0.3V V V IL E/ pulse width t W(E) V =3.3V/5V 180 ns 1. The output current keep constant in range of 545mA if V UT=1V. However, user can minimize V UT to reduce power dissipation according to used current, e.g., set V UT to 0.6V if I UT=20mA. 2. The maximum Vout is package thermal limited, user should keep Vout under maximum power dissipation. Page 5 of 16

6 Electrical Characteristics (V =3.3/5V, T A =25 C unless otherwise noted) Characteristic Symbol Conditions Min. Typ. Max. Unit igital inputs voltage S output voltage V IH 0.7V V V V IL 0 0.3V V V H V =3.3/5V, I H = 1mA V 0.4 V V L V =3.3/5V, I L = +1mA 0.4 V utput leakage current I L V UT =17V 0.5 ua utput current I UT V UT =1V, R EXT =900N 21 ma Current bit skew 1 di UT1 V UT =1V, R EXT =900N ±1 ±2 % Chip skew 2 di UT2 V UT =1V, R EXT =900N ±2 ±5 % Line regulation 3 I UT vs. V Load regulation 4 I UT vs. V UT Temp. regulation 5 I UT vs. T A %/dv %/dv UT %/dt A 3V<V <5.5V, V UT >1V, R EXT =900N 1V<V UT <4V, I UT =42mA, R EXT =900N 20 C < T A < 80 C, I UT =10mA~90mA,V =5V ±0.5 ±1 %/V ±0.1 ±0.5 %/V ±0.005 %/ C Pullup resistor R UP E/ 420 KN Pulldown resistor R WN LA/ 400 KN Supply current FF I (FF)1 I (FF)2 N I (N) 1. Bit skew=(i UTI AVG) / I AVG, where I AVG=(I UT(max)+ I UT(min))/2 V =3.3/5V, R EXT =pen, UT[0:7]=FF V =3.3/5V, R EXT =900Q, UT[0:7]=FF V =3.3/5V, R EXT =900 Q, UT[0:7]=N / Chip skew=(i AVGI CEN) / I CEN*100(%), where I CEN is the statistics distribution center of output currents. 3. Line regulation=[i UT(V =5.5V)I UT(V =3V)] / {[I UT(V =5.5V)+I UT(V =3V)]/2} / (5.5V3V)*100(%/V) 4. Load regulation=[i UT(V UT=4V)I UT(V UT=1V)] / {[I UT(V UT=4V)+I UT(V UT=1V)]/2} / (4V1V)*100(%/V) 5. Temperature regulation=[i UT(T A=80 C)I UT(T A=20 C )] / {[I UT(T A=80 C)+I UT(T A=20 C )]/2} / (80 C+20 C)*100(%/ C) Test Circuit for Electrical Characteristics ma V C 1 =1uF SI LA/ E/ I V UT0 UT1 UTn I UT V LE R EXT ±1mA REXT S UT7 GN V UT C LE =10uF *Place C 1/C LE as close to IC V/UT pin(not supply source) as possible. Page 6 of 16

7 Switching Characteristics (T A =25 C unless otherwise noted) Propagation delay time ( L to H ) Characteristic Symbol Conditions Min. Typ. Max. Unit UTn t PLH ns LA/ UTn t PLH ns E/ UT0 t PLH ns S t PLH ns UTn t PHL ns Propagation delay LA/ UTn t PHL ns time ( H to L ) E/ UT0 t PHL3 V = 3.3/5V ns V S t LE = 5V PHL ns V IH = V t W() V IL = GN 20 ns Pulse width LA/ t W(L) R EXT = 900N 20 ns E/ t R L = 180N W(E) 180 ns C L = 10pF Setup time for SI t S() C 5 ns 1 = 1uF Hold time for SI t H) C LE = 10uF 15 ns Setup time for LA/ t S(L) 5 ns Hold time for LA/ t H(L) 5 ns S rise time t SR 20 ns S fall time t SF 20 ns utput rise time of I UT t R ns utput fall time of I UT elayed output t F ns t R UT EVEN to 30 ns UT 30 ns t F Slow rise time 1 t R 500 ns Cascade Slow fall time 500 ns t F 1. It may not be possible to achieve the timing required for data transfer between two cascaded drivers if t R/t F is large. Test Circuit for Switching Characteristics V IL * C 1 V IH t R = t F = 10 ns SI LA/ E/ V I V UT0 UT1 V LE I UT C LE * C L R EXT C L REXT S GN UT7 V UT R L *Place C 1/C LE as close to IC V/UT pin(not supply source) as possible. Page 7 of 16

8 Timing Waveform LA/ Control utput t W() t R t F 50% 50% 10% 90% 90% 50% 50% 10% t S() t H() SI 50% 50% t PLH/PHL S 50% 10% 90% t SR/SL t H(L) t S(L) LA/ 50% 50% t W(L) E/ LW = ALL UTPUTS ENABLE t PHL2/PLH2 HIGH = UTPUT FF UTn t PHL1/PLH1 50% LW = UTPUT N E/ Control utput E/ t W(E) t PHL3 t PLH3 UT 50% 50% t F t R 90% 90% UT EVEN 50% 10% 50% 10% tf tr Page 8 of 16

9 Adjusting utput Current The s output current (I UT ) are set by one external resistor at pin REXT. The output current I UT versus resistance of R EXT is shown as the following figure. 70 I UT vs. R A =25 C V<V UT<4V IUT(mA) R EXT(KΩ) According to IV curve, the output voltage should be larger than 1V to get 45 ma constant current. By applying proper output voltage, the output current set by an external resistor is approximate to: I UT = 30(630 / REXT) (ma) (chip skew < ±5%). Thus the output current is set to be about 21mA at REXT = 900Q. utput Characteristics The current characteristic of output curve is flat. The output current can be kept constant regardless of the variations of LE forward voltage when V UT > V (roput voltage). The relationship between I UT and V UT is shown below. The output voltage should be kept as low as possible to prevent the from being overheated. 70 I UT vs. V A =25 C IUT(mA) rop-out voltage is current dependent, e.g., V =0. =0.5V@I UT=20mA VUT(V) Page 9 of 16

10 45 I UT vs. V A =25 C IUT(mA) V UT(V) Excellent Temperature Regulation The constant current driver requires not only the characteristics of supply and load voltage independence, but also temperature invariance. A well thermal stable reference circuit is designed within the. Users can get the stable output current over recommended current range I UT =5mA~45mA with ambient temperature (T A ) widely varying from 40 C to 85 C. 50 I UT vs. T 40 IUT(mA) T A( C) Page 10 of 16

11 Power issipation The maximum power dissipation (P (max) ) of a semiconductor chip varies with different packages and ambient temperature. It s determined as P (max) =(T J(max) T A )/R TH(ja) where T J(max) : maximum chip junction temperature is usually considered as 150 C, T A : ambient temperature, R TH(ja) : thermal resistance. Since P=IV, for sinking larger I UT, users had better add proper voltage reducers on outputs to reduce the heat generated from the. 2 SCT20167 P (max) vs. T A 1.5 SP16:R TH(j0a) =85 C/W P (max) (W) 1 SSP16:R TH(j0a) =117 C/W T A ( C) Limitation on Maximum utput Current The maximum output current vs. duty cycle is estimated by: I UT(max) =(((T J(max) T A )/R TH(ja) )(V *I ))/V UT /uty/n where T J(max) =150 C, N=8(all N) 50 I UT(max) vs. C/W IUT(max)(mA) VUT =4V V UT =4V V UT =3V VUT =3V V UT =2V TA=85 C TA=25 C uty(%) Page 11 of 16

12 50 45 I UT(max) vs. C/W V UT =4V IUT(max)(mA) V UT =4V V UT =3V TA=85 C TA=25 C uty(%) Page 12 of 16

13 Load Supply Voltage (VLE) The can be operated very well when V UT ranges from 1V to 4V. However, it is recommended to use the lowest possible supply voltage or set a voltage reducer to reduce the V UT voltage, at the same time reduce the power dissipation of the. Suggested V UT is to be set greater than V and less than 1V. The V is dependent on the I UT current as indicated in section utput Characteristics. Follow the diagram instructions shown below to lower down the output voltage. This can be done by adding additional resistor or zener diode, thus V UT =V LE V RP V F. V LE V LE V RP V RP I UT V F I UT V F V UT V UT Typical Application ynamic Lighting VLE PWER MSFET ARRAY which is not needed in Static SCAN UT0 UT6 UT1 UT7 C.U. SI E/ LA/ S SI E/ LA/ S REXT REXT Page 13 of 16

14 PCB esign Considerations Use the following general guideline when designing printed circuit boards (PCB): ecoupling Capacitor Place a decoupling capacitor e.g. 1uF between V and GN pins of. Locate the capacitor as close to the as possible. This is normally adequate for static LE driving. For dynamic scan or PWM applications, it is suggested to add an additional capacitor of 4.7uF or more to each supply for every. The necessary capacitance depends on the LE load current, PWM switching frequency, and serialin data speed. Inadequate V decoupling can cause timing problems, and very noisy LE supplies can affect LE current regulation. V LE V LPF 10Q Clock 10Q V C LE 10pF 1/4.7uF R EXT REXT External Resistor (R EXT ) Locate the external resistor as close to the REXT pin as possible to avoid the noise influence. Power and Ground Maximizing the width and minimizing the length of V and GN trace improves efficiency and ground bouncing by effect of reducing both power and ground parasitic resistance and inductance. A small value of resistor, e.g., 10Q (higher if I UT is larger) series in power input of the in conjunction with decoupling capacitor shunting the IC is recommended. Separating and feeding the LE power from another stable supply terminal V LE, furthermore adding a capacitor C LE greater than 10uF beside the LE are recommended. Please adapt C LE according to total system current consumption. EMI Reduction To reduce the EMI radiation from system, an economical solution of RC low pass filter (LPF) is suggested to be used to lower the transient edge of clock input signal, as shown in the figure above. Using at least four layers PCB board with two interior power and ground planes is a good scheme to decrease the signal current path which is the source of radiation emission. As a result, EMI radiation can be decreased. Page 14 of 16

15 Package imension SSP16(check uptodate version) c StarChips Technology E1 E StarChips Technology Inc. L y c Z b e A1 A2 A SEATING PLANE 0.25 mm GAUGE PLANE θ Symbol imension (mm) imension (mil) Min. Nom. Max. Min. Nom. Max. A A A b c E E e 0.64 BSC 25.0 BSC L y Z 0.23 REF 9.0 REF θ Page 15 of 16

16 SP16(check uptodate version) ETAIL A StarChips E1 E Technology c StarChips Technology Inc. y C SEATING PLANE e b A2 A1 A 0.25 mm ETAIL A GAUGE PLANE L θ Symbol imension (mm) imension (mil) Min. Nom. Max. Min. Nom. Max. A A A b c E E e 1.27 BSC 50.0 BSC L θ y Revision History(check uptodate version) ata Sheet Version V01_02 Remark CSWG package removed & description added Information provided by StarChips Technology is believed to be accurate and reliable. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Starchips can not assume responsibility and any problem raising out of the use of the circuits. Starchips reserves the right to change product specification without prior notice. StarChips Technology, Inc. 4F, No.5, Technology Rd.,ScienceBased Industrial Park, HsinChu,Taiwan, R..C. Tel: # 555 Page 16 of 16